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-rw-r--r--arch/arm/mach-omap2/Kconfig4
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-apollon.c15
-rw-r--r--arch/arm/mach-omap2/board-h4.c14
-rw-r--r--arch/arm/mach-omap2/board-ldp.c57
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c180
-rw-r--r--arch/arm/mach-omap2/clock34xx.c2
-rw-r--r--arch/arm/mach-omap2/clock34xx.h36
-rw-r--r--arch/arm/mach-omap2/id.c305
-rw-r--r--arch/arm/mach-omap2/irq.c39
-rw-r--r--arch/arm/mach-omap2/mux.c44
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c6
13 files changed, 502 insertions, 205 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4832fcc7d04a..3754b79092ab 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -55,3 +55,7 @@ config MACH_OMAP_LDP
55config MACH_OVERO 55config MACH_OVERO
56 bool "Gumstix Overo board" 56 bool "Gumstix Overo board"
57 depends on ARCH_OMAP3 && ARCH_OMAP34XX 57 depends on ARCH_OMAP3 && ARCH_OMAP34XX
58
59config MACH_OMAP3_PANDORA
60 bool "OMAP3 Pandora"
61 depends on ARCH_OMAP3 && ARCH_OMAP34XX \ No newline at end of file
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index c69392372c99..f12c43e4932f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -32,4 +32,5 @@ obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
32obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o 32obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
33obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o 33obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
34obj-$(CONFIG_MACH_OVERO) += board-overo.o 34obj-$(CONFIG_MACH_OVERO) += board-overo.o
35obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
35 36
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 24688efaa445..6748de6e19a8 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -168,13 +168,13 @@ static inline void __init sdp2430_init_smc91x(void)
168 sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; 168 sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f;
169 udelay(100); 169 udelay(100);
170 170
171 if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) { 171 if (gpio_request(OMAP24XX_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
172 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", 172 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
173 OMAP24XX_ETHR_GPIO_IRQ); 173 OMAP24XX_ETHR_GPIO_IRQ);
174 gpmc_cs_free(eth_cs); 174 gpmc_cs_free(eth_cs);
175 goto out; 175 goto out;
176 } 176 }
177 omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); 177 gpio_direction_input(OMAP24XX_ETHR_GPIO_IRQ);
178 178
179out: 179out:
180 clk_disable(gpmc_fck); 180 clk_disable(gpmc_fck);
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 989ad152d7f8..d83035b436d5 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -236,13 +236,13 @@ static inline void __init apollon_init_smc91x(void)
236 udelay(100); 236 udelay(100);
237 237
238 omap_cfg_reg(W4__24XX_GPIO74); 238 omap_cfg_reg(W4__24XX_GPIO74);
239 if (omap_request_gpio(APOLLON_ETHR_GPIO_IRQ) < 0) { 239 if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
240 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", 240 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
241 APOLLON_ETHR_GPIO_IRQ); 241 APOLLON_ETHR_GPIO_IRQ);
242 gpmc_cs_free(APOLLON_ETH_CS); 242 gpmc_cs_free(APOLLON_ETH_CS);
243 goto out; 243 goto out;
244 } 244 }
245 omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); 245 gpio_direction_input(APOLLON_ETHR_GPIO_IRQ);
246 246
247out: 247out:
248 clk_disable(gpmc_fck); 248 clk_disable(gpmc_fck);
@@ -327,15 +327,15 @@ static void __init apollon_sw_init(void)
327 /* Enter SW - Y11 */ 327 /* Enter SW - Y11 */
328 omap_cfg_reg(Y11_242X_GPIO16); 328 omap_cfg_reg(Y11_242X_GPIO16);
329 omap_request_gpio(SW_ENTER_GPIO16); 329 omap_request_gpio(SW_ENTER_GPIO16);
330 omap_set_gpio_direction(SW_ENTER_GPIO16, 1); 330 gpio_direction_input(SW_ENTER_GPIO16);
331 /* Up SW - AA12 */ 331 /* Up SW - AA12 */
332 omap_cfg_reg(AA12_242X_GPIO17); 332 omap_cfg_reg(AA12_242X_GPIO17);
333 omap_request_gpio(SW_UP_GPIO17); 333 omap_request_gpio(SW_UP_GPIO17);
334 omap_set_gpio_direction(SW_UP_GPIO17, 1); 334 gpio_direction_input(SW_UP_GPIO17);
335 /* Down SW - AA8 */ 335 /* Down SW - AA8 */
336 omap_cfg_reg(AA8_242X_GPIO58); 336 omap_cfg_reg(AA8_242X_GPIO58);
337 omap_request_gpio(SW_DOWN_GPIO58); 337 omap_request_gpio(SW_DOWN_GPIO58);
338 omap_set_gpio_direction(SW_DOWN_GPIO58, 1); 338 gpio_direction_input(SW_DOWN_GPIO58);
339 339
340 set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQ_TYPE_EDGE_RISING); 340 set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQ_TYPE_EDGE_RISING);
341 if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt, 341 if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt,
@@ -359,9 +359,8 @@ static void __init apollon_usb_init(void)
359 /* USB device */ 359 /* USB device */
360 /* DEVICE_SUSPEND */ 360 /* DEVICE_SUSPEND */
361 omap_cfg_reg(P21_242X_GPIO12); 361 omap_cfg_reg(P21_242X_GPIO12);
362 omap_request_gpio(12); 362 gpio_request(12, "USB suspend");
363 omap_set_gpio_direction(12, 0); /* OUT */ 363 gpio_direction_output(12, 0);
364 omap_set_gpio_dataout(12, 0);
365} 364}
366 365
367static void __init omap_apollon_init(void) 366static void __init omap_apollon_init(void)
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 2fef2c845083..7de0506e1e29 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -19,6 +19,7 @@
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/workqueue.h> 20#include <linux/workqueue.h>
21#include <linux/i2c.h> 21#include <linux/i2c.h>
22#include <linux/i2c/at24.h>
22#include <linux/input.h> 23#include <linux/input.h>
23#include <linux/err.h> 24#include <linux/err.h>
24#include <linux/clk.h> 25#include <linux/clk.h>
@@ -392,11 +393,24 @@ static struct omap_board_config_kernel h4_config[] = {
392 { OMAP_TAG_LCD, &h4_lcd_config }, 393 { OMAP_TAG_LCD, &h4_lcd_config },
393}; 394};
394 395
396static struct at24_platform_data m24c01 = {
397 .byte_len = SZ_1K / 8,
398 .page_size = 16,
399};
400
395static struct i2c_board_info __initdata h4_i2c_board_info[] = { 401static struct i2c_board_info __initdata h4_i2c_board_info[] = {
396 { 402 {
397 I2C_BOARD_INFO("isp1301_omap", 0x2d), 403 I2C_BOARD_INFO("isp1301_omap", 0x2d),
398 .irq = OMAP_GPIO_IRQ(125), 404 .irq = OMAP_GPIO_IRQ(125),
399 }, 405 },
406 { /* EEPROM on mainboard */
407 I2C_BOARD_INFO("24c01", 0x52),
408 .platform_data = &m24c01,
409 },
410 { /* EEPROM on cpu card */
411 I2C_BOARD_INFO("24c01", 0x57),
412 .platform_data = &m24c01,
413 },
400}; 414};
401 415
402static void __init omap_h4_init(void) 416static void __init omap_h4_init(void)
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 1ea59986aa7a..43c7ac4b7f8f 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -38,11 +38,67 @@
38#include <asm/delay.h> 38#include <asm/delay.h>
39#include <mach/control.h> 39#include <mach/control.h>
40 40
41#define SDP3430_SMC91X_CS 3
42
43static struct resource ldp_smc911x_resources[] = {
44 [0] = {
45 .start = OMAP34XX_ETHR_START,
46 .end = OMAP34XX_ETHR_START + SZ_4K,
47 .flags = IORESOURCE_MEM,
48 },
49 [1] = {
50 .start = 0,
51 .end = 0,
52 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
53 },
54};
55
56static struct platform_device ldp_smc911x_device = {
57 .name = "smc911x",
58 .id = -1,
59 .num_resources = ARRAY_SIZE(ldp_smc911x_resources),
60 .resource = ldp_smc911x_resources,
61};
62
63static struct platform_device *ldp_devices[] __initdata = {
64 &ldp_smc911x_device,
65};
66
67static inline void __init ldp_init_smc911x(void)
68{
69 int eth_cs;
70 unsigned long cs_mem_base;
71 int eth_gpio = 0;
72
73 eth_cs = LDP_SMC911X_CS;
74
75 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
76 printk(KERN_ERR "Failed to request GPMC mem for smc911x\n");
77 return;
78 }
79
80 ldp_smc911x_resources[0].start = cs_mem_base + 0x0;
81 ldp_smc911x_resources[0].end = cs_mem_base + 0xf;
82 udelay(100);
83
84 eth_gpio = LDP_SMC911X_GPIO;
85
86 ldp_smc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
87
88 if (omap_request_gpio(eth_gpio) < 0) {
89 printk(KERN_ERR "Failed to request GPIO%d for smc911x IRQ\n",
90 eth_gpio);
91 return;
92 }
93 gpio_direction_input(eth_gpio);
94}
95
41static void __init omap_ldp_init_irq(void) 96static void __init omap_ldp_init_irq(void)
42{ 97{
43 omap2_init_common_hw(); 98 omap2_init_common_hw();
44 omap_init_irq(); 99 omap_init_irq();
45 omap_gpio_init(); 100 omap_gpio_init();
101 ldp_init_smc911x();
46} 102}
47 103
48static struct omap_uart_config ldp_uart_config __initdata = { 104static struct omap_uart_config ldp_uart_config __initdata = {
@@ -64,6 +120,7 @@ static int __init omap_i2c_init(void)
64static void __init omap_ldp_init(void) 120static void __init omap_ldp_init(void)
65{ 121{
66 omap_i2c_init(); 122 omap_i2c_init();
123 platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
67 omap_board_config = ldp_config; 124 omap_board_config = ldp_config;
68 omap_board_config_size = ARRAY_SIZE(ldp_config); 125 omap_board_config_size = ARRAY_SIZE(ldp_config);
69 omap_serial_init(); 126 omap_serial_init();
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
new file mode 100644
index 000000000000..7236c7be05b3
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -0,0 +1,180 @@
1/*
2 * board-omap3pandora.c (Pandora Handheld Console)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
16 * 02110-1301 USA
17 *
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/platform_device.h>
23
24#include <linux/spi/spi.h>
25#include <linux/spi/ads7846.h>
26#include <linux/i2c/twl4030.h>
27
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31
32#include <mach/board.h>
33#include <mach/common.h>
34#include <mach/gpio.h>
35#include <mach/hardware.h>
36#include <mach/mcspi.h>
37
38#define OMAP3_PANDORA_TS_GPIO 94
39
40static struct omap_uart_config omap3pandora_uart_config __initdata = {
41 .enabled_uarts = (1 << 2), /* UART3 */
42};
43
44static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
45 .gpio_base = OMAP_MAX_GPIO_LINES,
46 .irq_base = TWL4030_GPIO_IRQ_BASE,
47 .irq_end = TWL4030_GPIO_IRQ_END,
48};
49
50static struct twl4030_usb_data omap3pandora_usb_data = {
51 .usb_mode = T2_USB_MODE_ULPI,
52};
53
54static struct twl4030_platform_data omap3pandora_twldata = {
55 .irq_base = TWL4030_IRQ_BASE,
56 .irq_end = TWL4030_IRQ_END,
57 .gpio = &omap3pandora_gpio_data,
58 .usb = &omap3pandora_usb_data,
59};
60
61static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = {
62 {
63 I2C_BOARD_INFO("tps65950", 0x48),
64 .flags = I2C_CLIENT_WAKE,
65 .irq = INT_34XX_SYS_NIRQ,
66 .platform_data = &omap3pandora_twldata,
67 },
68};
69
70static int __init omap3pandora_i2c_init(void)
71{
72 omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
73 ARRAY_SIZE(omap3pandora_i2c_boardinfo));
74 /* i2c2 pins are not connected */
75 omap_register_i2c_bus(3, 400, NULL, 0);
76 return 0;
77}
78
79static void __init omap3pandora_init_irq(void)
80{
81 omap2_init_common_hw();
82 omap_init_irq();
83 omap_gpio_init();
84}
85
86static void __init omap3pandora_ads7846_init(void)
87{
88 int gpio = OMAP3_PANDORA_TS_GPIO;
89 int ret;
90
91 ret = gpio_request(gpio, "ads7846_pen_down");
92 if (ret < 0) {
93 printk(KERN_ERR "Failed to request GPIO %d for "
94 "ads7846 pen down IRQ\n", gpio);
95 return;
96 }
97
98 gpio_direction_input(gpio);
99}
100
101static int ads7846_get_pendown_state(void)
102{
103 return !gpio_get_value(OMAP3_PANDORA_TS_GPIO);
104}
105
106static struct ads7846_platform_data ads7846_config = {
107 .x_max = 0x0fff,
108 .y_max = 0x0fff,
109 .x_plate_ohms = 180,
110 .pressure_max = 255,
111 .debounce_max = 10,
112 .debounce_tol = 3,
113 .debounce_rep = 1,
114 .get_pendown_state = ads7846_get_pendown_state,
115 .keep_vref_on = 1,
116};
117
118static struct omap2_mcspi_device_config ads7846_mcspi_config = {
119 .turbo_mode = 0,
120 .single_channel = 1, /* 0: slave, 1: master */
121};
122
123static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
124 {
125 .modalias = "ads7846",
126 .bus_num = 1,
127 .chip_select = 0,
128 .max_speed_hz = 1500000,
129 .controller_data = &ads7846_mcspi_config,
130 .irq = OMAP_GPIO_IRQ(OMAP3_PANDORA_TS_GPIO),
131 .platform_data = &ads7846_config,
132 }
133};
134
135static struct platform_device omap3pandora_lcd_device = {
136 .name = "pandora_lcd",
137 .id = -1,
138};
139
140static struct omap_lcd_config omap3pandora_lcd_config __initdata = {
141 .ctrl_name = "internal",
142};
143
144static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
145 { OMAP_TAG_UART, &omap3pandora_uart_config },
146 { OMAP_TAG_LCD, &omap3pandora_lcd_config },
147};
148
149static struct platform_device *omap3pandora_devices[] __initdata = {
150 &omap3pandora_lcd_device,
151};
152
153static void __init omap3pandora_init(void)
154{
155 omap3pandora_i2c_init();
156 platform_add_devices(omap3pandora_devices,
157 ARRAY_SIZE(omap3pandora_devices));
158 omap_board_config = omap3pandora_config;
159 omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
160 omap_serial_init();
161 spi_register_board_info(omap3pandora_spi_board_info,
162 ARRAY_SIZE(omap3pandora_spi_board_info));
163 omap3pandora_ads7846_init();
164}
165
166static void __init omap3pandora_map_io(void)
167{
168 omap2_set_globals_343x();
169 omap2_map_common_io();
170}
171
172MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
173 .phys_io = 0x48000000,
174 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
175 .boot_params = 0x80000100,
176 .map_io = omap3pandora_map_io,
177 .init_irq = omap3pandora_init_irq,
178 .init_machine = omap3pandora_init,
179 .timer = &omap_timer,
180MACHINE_END
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 084e11082f80..31bb7010bd48 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -475,7 +475,7 @@ int __init omap2_clk_init(void)
475 * Update this if there are further clock changes between ES2 475 * Update this if there are further clock changes between ES2
476 * and production parts 476 * and production parts
477 */ 477 */
478 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) { 478 if (omap_rev() == OMAP3430_REV_ES1_0) {
479 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 479 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
480 cpu_clkflg |= CLOCK_IN_OMAP3430ES1; 480 cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
481 } else { 481 } else {
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c38a8a09692f..7217a0824ec4 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2280,8 +2280,8 @@ static struct clk wkup_32k_fck = {
2280 .recalc = &followparent_recalc, 2280 .recalc = &followparent_recalc,
2281}; 2281};
2282 2282
2283static struct clk gpio1_fck = { 2283static struct clk gpio1_dbck = {
2284 .name = "gpio1_fck", 2284 .name = "gpio1_dbck",
2285 .parent = &wkup_32k_fck, 2285 .parent = &wkup_32k_fck,
2286 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2286 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2287 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2287 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@@ -2527,8 +2527,8 @@ static struct clk per_32k_alwon_fck = {
2527 .recalc = &followparent_recalc, 2527 .recalc = &followparent_recalc,
2528}; 2528};
2529 2529
2530static struct clk gpio6_fck = { 2530static struct clk gpio6_dbck = {
2531 .name = "gpio6_fck", 2531 .name = "gpio6_dbck",
2532 .parent = &per_32k_alwon_fck, 2532 .parent = &per_32k_alwon_fck,
2533 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2533 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2534 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2534 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@@ -2537,8 +2537,8 @@ static struct clk gpio6_fck = {
2537 .recalc = &followparent_recalc, 2537 .recalc = &followparent_recalc,
2538}; 2538};
2539 2539
2540static struct clk gpio5_fck = { 2540static struct clk gpio5_dbck = {
2541 .name = "gpio5_fck", 2541 .name = "gpio5_dbck",
2542 .parent = &per_32k_alwon_fck, 2542 .parent = &per_32k_alwon_fck,
2543 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2543 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2544 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2544 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@@ -2547,8 +2547,8 @@ static struct clk gpio5_fck = {
2547 .recalc = &followparent_recalc, 2547 .recalc = &followparent_recalc,
2548}; 2548};
2549 2549
2550static struct clk gpio4_fck = { 2550static struct clk gpio4_dbck = {
2551 .name = "gpio4_fck", 2551 .name = "gpio4_dbck",
2552 .parent = &per_32k_alwon_fck, 2552 .parent = &per_32k_alwon_fck,
2553 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2553 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2554 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2554 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@@ -2557,8 +2557,8 @@ static struct clk gpio4_fck = {
2557 .recalc = &followparent_recalc, 2557 .recalc = &followparent_recalc,
2558}; 2558};
2559 2559
2560static struct clk gpio3_fck = { 2560static struct clk gpio3_dbck = {
2561 .name = "gpio3_fck", 2561 .name = "gpio3_dbck",
2562 .parent = &per_32k_alwon_fck, 2562 .parent = &per_32k_alwon_fck,
2563 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2563 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2564 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@@ -2567,8 +2567,8 @@ static struct clk gpio3_fck = {
2567 .recalc = &followparent_recalc, 2567 .recalc = &followparent_recalc,
2568}; 2568};
2569 2569
2570static struct clk gpio2_fck = { 2570static struct clk gpio2_dbck = {
2571 .name = "gpio2_fck", 2571 .name = "gpio2_dbck",
2572 .parent = &per_32k_alwon_fck, 2572 .parent = &per_32k_alwon_fck,
2573 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2573 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2574 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2574 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@@ -3170,7 +3170,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
3170 &usim_fck, 3170 &usim_fck,
3171 &gpt1_fck, 3171 &gpt1_fck,
3172 &wkup_32k_fck, 3172 &wkup_32k_fck,
3173 &gpio1_fck, 3173 &gpio1_dbck,
3174 &wdt2_fck, 3174 &wdt2_fck,
3175 &wkup_l4_ick, 3175 &wkup_l4_ick,
3176 &usim_ick, 3176 &usim_ick,
@@ -3192,11 +3192,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
3192 &gpt8_fck, 3192 &gpt8_fck,
3193 &gpt9_fck, 3193 &gpt9_fck,
3194 &per_32k_alwon_fck, 3194 &per_32k_alwon_fck,
3195 &gpio6_fck, 3195 &gpio6_dbck,
3196 &gpio5_fck, 3196 &gpio5_dbck,
3197 &gpio4_fck, 3197 &gpio4_dbck,
3198 &gpio3_fck, 3198 &gpio3_dbck,
3199 &gpio2_fck, 3199 &gpio2_dbck,
3200 &wdt3_fck, 3200 &wdt3_fck,
3201 &per_l4_ick, 3201 &per_l4_ick,
3202 &gpio6_ick, 3202 &gpio6_ick,
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index bf45ff39a7b5..b0f8e7d62798 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -22,40 +22,15 @@
22#include <mach/control.h> 22#include <mach/control.h>
23#include <mach/cpu.h> 23#include <mach/cpu.h>
24 24
25static u32 class; 25static struct omap_chip_id omap_chip;
26static void __iomem *tap_base; 26static unsigned int omap_revision;
27static u16 tap_prod_id;
28
29#define OMAP_TAP_IDCODE 0x0204
30#define OMAP_TAP_DIE_ID_0 0x0218
31#define OMAP_TAP_DIE_ID_1 0x021C
32#define OMAP_TAP_DIE_ID_2 0x0220
33#define OMAP_TAP_DIE_ID_3 0x0224
34
35/* system_rev fields for OMAP2 processors:
36 * CPU id bits [31:16],
37 * CPU device type [15:12], (unprg,normal,POP)
38 * CPU revision [11:08]
39 * CPU class bits [07:00]
40 */
41
42struct omap_id {
43 u16 hawkeye; /* Silicon type (Hawkeye id) */
44 u8 dev; /* Device type from production_id reg */
45 u32 type; /* combined type id copied to system_rev */
46};
47 27
48/* Register values to detect the OMAP version */
49static struct omap_id omap_ids[] __initdata = {
50 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
51 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
52 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
53 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
54 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
55 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
56};
57 28
58static struct omap_chip_id omap_chip; 29unsigned int omap_rev(void)
30{
31 return omap_revision;
32}
33EXPORT_SYMBOL(omap_rev);
59 34
60/** 35/**
61 * omap_chip_is - test whether currently running OMAP matches a chip type 36 * omap_chip_is - test whether currently running OMAP matches a chip type
@@ -70,135 +45,41 @@ int omap_chip_is(struct omap_chip_id oci)
70} 45}
71EXPORT_SYMBOL(omap_chip_is); 46EXPORT_SYMBOL(omap_chip_is);
72 47
73static u32 __init read_tap_reg(int reg) 48/*----------------------------------------------------------------------------*/
74{
75 unsigned int regval = 0;
76 u32 cpuid;
77
78 /* Reading the IDCODE register on 3430 ES1 results in a
79 * data abort as the register is not exposed on the OCP
80 * Hence reading the Cortex Rev
81 */
82 cpuid = read_cpuid(CPUID_ID);
83
84 /* If the processor type is Cortex-A8 and the revision is 0x0
85 * it means its Cortex r0p0 which is 3430 ES1
86 */
87 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
88
89 if (reg == tap_prod_id) {
90 regval = 0x000F00F0;
91 goto out;
92 }
93
94 switch (reg) {
95 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
96 /* Making DevType as 0xF in ES1 to differ from ES2 */
97 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
98 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
99 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
100 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
101 }
102 } else
103 regval = __raw_readl(tap_base + reg);
104
105out:
106 return regval;
107
108}
109 49
110/* 50#define OMAP_TAP_IDCODE 0x0204
111 * _set_system_rev - set the system_rev global based on current OMAP chip type 51#define OMAP_TAP_DIE_ID_0 0x0218
112 * 52#define OMAP_TAP_DIE_ID_1 0x021C
113 * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx() 53#define OMAP_TAP_DIE_ID_2 0x0220
114 * macros. 54#define OMAP_TAP_DIE_ID_3 0x0224
115 */
116static void __init _set_system_rev(u32 type, u8 rev)
117{
118 u32 i, ctrl_status;
119
120 /*
121 * system_rev encoding is as follows
122 * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
123 * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
124 * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
125 * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
126 * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
127 * system_rev & 0x000000c0 -> IDCODE revision[6:7]
128 * system_rev & 0x0000003f -> sys_boot[0:5]
129 */
130 /* Embedding the ES revision info in type field */
131 system_rev = type;
132 /* Also add IDCODE revision info only two lower bits */
133 system_rev |= ((rev & 0x3) << 6);
134
135 /* Add in the device type and sys_boot fields (see above) */
136 if (cpu_is_omap24xx()) {
137 i = OMAP24XX_CONTROL_STATUS;
138 } else if (cpu_is_omap343x()) {
139 i = OMAP343X_CONTROL_STATUS;
140 } else {
141 printk(KERN_ERR "id: unknown CPU type\n");
142 BUG();
143 }
144 ctrl_status = omap_ctrl_readl(i);
145 system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
146 OMAP2_SYSBOOT_4_MASK |
147 OMAP2_SYSBOOT_3_MASK |
148 OMAP2_SYSBOOT_2_MASK |
149 OMAP2_SYSBOOT_1_MASK |
150 OMAP2_SYSBOOT_0_MASK));
151 system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
152}
153
154
155/*
156 * _set_omap_chip - set the omap_chip global based on OMAP chip type
157 *
158 * Build the omap_chip bits. This variable is used by powerdomain and
159 * clockdomain code to indicate whether structures are applicable for
160 * the current OMAP chip type by ANDing it against a 'platform' bitfield
161 * in the structure.
162 */
163static void __init _set_omap_chip(void)
164{
165 if (cpu_is_omap343x()) {
166
167 omap_chip.oc = CHIP_IS_OMAP3430;
168 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
169 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
170 else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
171 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
172
173 } else if (cpu_is_omap243x()) {
174
175 /* Currently only supports 2430ES2.1 and 2430-all */
176 omap_chip.oc |= CHIP_IS_OMAP2430;
177
178 } else if (cpu_is_omap242x()) {
179
180 /* Currently only supports 2420ES2.1.1 and 2420-all */
181 omap_chip.oc |= CHIP_IS_OMAP2420;
182 55
183 } else { 56#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
184 57
185 /* Current CPU not supported by this code. */ 58struct omap_id {
186 printk(KERN_WARNING "OMAP chip type code does not yet support " 59 u16 hawkeye; /* Silicon type (Hawkeye id) */
187 "this CPU type.\n"); 60 u8 dev; /* Device type from production_id reg */
188 WARN_ON(1); 61 u32 type; /* Combined type id copied to omap_revision */
62};
189 63
190 } 64/* Register values to detect the OMAP version */
65static struct omap_id omap_ids[] __initdata = {
66 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
67 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
68 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
69 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
70 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
71 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
72};
191 73
192} 74static void __iomem *tap_base;
75static u16 tap_prod_id;
193 76
194void __init omap2_check_revision(void) 77void __init omap24xx_check_revision(void)
195{ 78{
196 int i, j; 79 int i, j;
197 u32 idcode; 80 u32 idcode, prod_id;
198 u32 prod_id;
199 u16 hawkeye; 81 u16 hawkeye;
200 u8 dev_type; 82 u8 dev_type, rev;
201 u8 rev;
202 83
203 idcode = read_tap_reg(OMAP_TAP_IDCODE); 84 idcode = read_tap_reg(OMAP_TAP_IDCODE);
204 prod_id = read_tap_reg(tap_prod_id); 85 prod_id = read_tap_reg(tap_prod_id);
@@ -220,18 +101,6 @@ void __init omap2_check_revision(void)
220 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 101 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
221 prod_id, dev_type); 102 prod_id, dev_type);
222 103
223 /*
224 * Detection for 34xx ES2.0 and above can be done with just
225 * hawkeye and rev. See TRM 1.5.2 Device Identification.
226 * Note that rev cannot be used directly as ES1.0 uses value 0.
227 */
228 if (hawkeye == 0xb7ae) {
229 system_rev = 0x34300000 | ((1 + rev) << 12);
230 pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
231 _set_omap_chip();
232 return;
233 }
234
235 /* Check hawkeye ids */ 104 /* Check hawkeye ids */
236 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 105 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
237 if (hawkeye == omap_ids[i].hawkeye) 106 if (hawkeye == omap_ids[i].hawkeye)
@@ -255,23 +124,115 @@ void __init omap2_check_revision(void)
255 j = i; 124 j = i;
256 } 125 }
257 126
258 _set_system_rev(omap_ids[j].type, rev); 127 pr_info("OMAP%04x", omap_rev() >> 16);
128 if ((omap_rev() >> 8) & 0x0f)
129 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
130 pr_info("\n");
131}
259 132
260 _set_omap_chip(); 133void __init omap34xx_check_revision(void)
134{
135 u32 cpuid, idcode;
136 u16 hawkeye;
137 u8 rev;
138 char *rev_name = "ES1.0";
261 139
262 pr_info("OMAP%04x", system_rev >> 16); 140 /*
263 if ((system_rev >> 8) & 0x0f) 141 * We cannot access revision registers on ES1.0.
264 pr_info("ES%x", (system_rev >> 12) & 0xf); 142 * If the processor type is Cortex-A8 and the revision is 0x0
265 pr_info("\n"); 143 * it means its Cortex r0p0 which is 3430 ES1.0.
144 */
145 cpuid = read_cpuid(CPUID_ID);
146 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
147 omap_revision = OMAP3430_REV_ES1_0;
148 goto out;
149 }
266 150
151 /*
152 * Detection for 34xx ES2.0 and above can be done with just
153 * hawkeye and rev. See TRM 1.5.2 Device Identification.
154 * Note that rev does not map directly to our defined processor
155 * revision numbers as ES1.0 uses value 0.
156 */
157 idcode = read_tap_reg(OMAP_TAP_IDCODE);
158 hawkeye = (idcode >> 12) & 0xffff;
159 rev = (idcode >> 28) & 0xff;
160
161 if (hawkeye == 0xb7ae) {
162 switch (rev) {
163 case 0:
164 omap_revision = OMAP3430_REV_ES2_0;
165 rev_name = "ES2.0";
166 break;
167 case 2:
168 omap_revision = OMAP3430_REV_ES2_1;
169 rev_name = "ES2.1";
170 break;
171 case 3:
172 omap_revision = OMAP3430_REV_ES3_0;
173 rev_name = "ES3.0";
174 break;
175 default:
176 /* Use the latest known revision as default */
177 omap_revision = OMAP3430_REV_ES3_0;
178 rev_name = "Unknown revision\n";
179 }
180 }
181
182out:
183 pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
267} 184}
268 185
186/*
187 * Try to detect the exact revision of the omap we're running on
188 */
189void __init omap2_check_revision(void)
190{
191 /*
192 * At this point we have an idea about the processor revision set
193 * earlier with omap2_set_globals_tap().
194 */
195 if (cpu_is_omap24xx())
196 omap24xx_check_revision();
197 else if (cpu_is_omap34xx())
198 omap34xx_check_revision();
199 else
200 pr_err("OMAP revision unknown, please fix!\n");
201
202 /*
203 * OK, now we know the exact revision. Initialize omap_chip bits
204 * for powerdowmain and clockdomain code.
205 */
206 if (cpu_is_omap243x()) {
207 /* Currently only supports 2430ES2.1 and 2430-all */
208 omap_chip.oc |= CHIP_IS_OMAP2430;
209 } else if (cpu_is_omap242x()) {
210 /* Currently only supports 2420ES2.1.1 and 2420-all */
211 omap_chip.oc |= CHIP_IS_OMAP2420;
212 } else if (cpu_is_omap343x()) {
213 omap_chip.oc = CHIP_IS_OMAP3430;
214 if (omap_rev() == OMAP3430_REV_ES1_0)
215 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
216 else if (omap_rev() > OMAP3430_REV_ES1_0)
217 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
218 } else {
219 pr_err("Uninitialized omap_chip, please fix!\n");
220 }
221}
222
223/*
224 * Set up things for map_io and processor detection later on. Gets called
225 * pretty much first thing from board init. For multi-omap, this gets
226 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
227 * detect the exact revision later on in omap2_detect_revision() once map_io
228 * is done.
229 */
269void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) 230void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
270{ 231{
271 class = omap2_globals->class; 232 omap_revision = omap2_globals->class;
272 tap_base = omap2_globals->tap; 233 tap_base = omap2_globals->tap;
273 234
274 if (class == 0x3430) 235 if (cpu_is_omap34xx())
275 tap_prod_id = 0x0210; 236 tap_prod_id = 0x0210;
276 else 237 else
277 tap_prod_id = 0x0208; 238 tap_prod_id = 0x0208;
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index c40fc378a251..636e2821af7d 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -23,6 +23,7 @@
23#define INTC_REVISION 0x0000 23#define INTC_REVISION 0x0000
24#define INTC_SYSCONFIG 0x0010 24#define INTC_SYSCONFIG 0x0010
25#define INTC_SYSSTATUS 0x0014 25#define INTC_SYSSTATUS 0x0014
26#define INTC_SIR 0x0040
26#define INTC_CONTROL 0x0048 27#define INTC_CONTROL 0x0048
27#define INTC_MIR_CLEAR0 0x0088 28#define INTC_MIR_CLEAR0 0x0088
28#define INTC_MIR_SET0 0x008c 29#define INTC_MIR_SET0 0x008c
@@ -60,6 +61,30 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
60 return __raw_readl(bank->base_reg + reg); 61 return __raw_readl(bank->base_reg + reg);
61} 62}
62 63
64static int previous_irq;
65
66/*
67 * On 34xx we can get occasional spurious interrupts if the ack from
68 * an interrupt handler does not get posted before we unmask. Warn about
69 * the interrupt handlers that need to flush posted writes.
70 */
71static int omap_check_spurious(unsigned int irq)
72{
73 u32 sir, spurious;
74
75 sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
76 spurious = sir >> 6;
77
78 if (spurious > 1) {
79 printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
80 "posted write for irq %i\n",
81 irq, sir, previous_irq);
82 return spurious;
83 }
84
85 return 0;
86}
87
63/* XXX: FIQ and additional INTC support (only MPU at the moment) */ 88/* XXX: FIQ and additional INTC support (only MPU at the moment) */
64static void omap_ack_irq(unsigned int irq) 89static void omap_ack_irq(unsigned int irq)
65{ 90{
@@ -70,6 +95,20 @@ static void omap_mask_irq(unsigned int irq)
70{ 95{
71 int offset = irq & (~(IRQ_BITS_PER_REG - 1)); 96 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
72 97
98 if (cpu_is_omap34xx()) {
99 int spurious = 0;
100
101 /*
102 * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
103 * it is the highest irq number?
104 */
105 if (irq == INT_34XX_GPT12_IRQ)
106 spurious = omap_check_spurious(irq);
107
108 if (!spurious)
109 previous_irq = irq;
110 }
111
73 irq &= (IRQ_BITS_PER_REG - 1); 112 irq &= (IRQ_BITS_PER_REG - 1);
74 113
75 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset); 114 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index b1393673d95d..dacb41f130c0 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -203,6 +203,15 @@ MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1)
203MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1) 203MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1)
204 204
205/* 2430 McBSP */ 205/* 2430 McBSP */
206MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1)
207
208MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1)
209MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1)
210MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1)
211MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1)
212MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1)
213MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1)
214
206MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1) 215MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1)
207MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1) 216MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1)
208MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1) 217MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1)
@@ -211,6 +220,31 @@ MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1)
211MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1) 220MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1)
212MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1) 221MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1)
213MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) 222MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
223
224MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1)
225MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1)
226MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1)
227MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1)
228
229MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1)
230MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1)
231MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1)
232MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1)
233
234MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1)
235MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1)
236MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1)
237MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1)
238
239/* 2430 MCSPI1 */
240MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1)
241MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1)
242MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1)
243MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1)
244
245/* Touchscreen GPIO */
246MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1)
247
214}; 248};
215 249
216#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) 250#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins)
@@ -417,6 +451,14 @@ MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
417MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a, 451MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
418 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 452 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
419 453
454
455/* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix.
456 * No internal pullup/pulldown without "_UP" or "_DOWN" suffix.
457 */
458MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa,
459 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
460MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
461 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
420}; 462};
421 463
422#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) 464#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
@@ -452,7 +494,7 @@ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 r
452#endif 494#endif
453 495
454#ifdef CONFIG_ARCH_OMAP24XX 496#ifdef CONFIG_ARCH_OMAP24XX
455int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) 497static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
456{ 498{
457 static DEFINE_SPINLOCK(mux_spin_lock); 499 static DEFINE_SPINLOCK(mux_spin_lock);
458 unsigned long flags; 500 unsigned long flags;
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 10ef464d6be7..15e509013def 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -12,11 +12,11 @@
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/gpio.h>
15 16
16#include <linux/usb/musb.h> 17#include <linux/usb/musb.h>
17 18
18#include <mach/gpmc.h> 19#include <mach/gpmc.h>
19#include <mach/gpio.h>
20#include <mach/mux.h> 20#include <mach/mux.h>
21 21
22 22
@@ -292,12 +292,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
292 ); 292 );
293 293
294 /* IRQ */ 294 /* IRQ */
295 status = omap_request_gpio(irq); 295 status = gpio_request(irq, "TUSB6010 irq");
296 if (status < 0) { 296 if (status < 0) {
297 printk(error, 3, status); 297 printk(error, 3, status);
298 return status; 298 return status;
299 } 299 }
300 omap_set_gpio_direction(irq, 1); 300 gpio_direction_input(irq);
301 tusb_resources[2].start = irq + IH_GPIO_BASE; 301 tusb_resources[2].start = irq + IH_GPIO_BASE;
302 302
303 /* set up memory timings ... can speed them up later */ 303 /* set up memory timings ... can speed them up later */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 14:19:26 -0500