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-rw-r--r--arch/arm/mach-omap2/sram34xx.S224
1 files changed, 170 insertions, 54 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index c080c82521e1..82aa4a3d160c 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -3,13 +3,12 @@
3 * 3 *
4 * Omap3 specific functions that need to be run in internal SRAM 4 * Omap3 specific functions that need to be run in internal SRAM
5 * 5 *
6 * (C) Copyright 2007 6 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Texas Instruments Inc. 7 * Copyright (C) 2008 Nokia Corporation
8 * Rajendra Nayak <rnayak@ti.com>
9 * 8 *
10 * (C) Copyright 2004 9 * Rajendra Nayak <rnayak@ti.com>
11 * Texas Instruments, <www.ti.com>
12 * Richard Woodruff <r-woodruff2@ti.com> 10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Paul Walmsley
13 * 12 *
14 * This program is free software; you can redistribute it and/or 13 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as 14 * modify it under the terms of the GNU General Public License as
@@ -37,61 +36,141 @@
37 36
38 .text 37 .text
39 38
39/* r1 parameters */
40#define SDRC_NO_UNLOCK_DLL 0x0
41#define SDRC_UNLOCK_DLL 0x1
42
43/* SDRC_DLLA_CTRL bit settings */
44#define FIXEDDELAY_SHIFT 24
45#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
46#define DLLIDLE_MASK 0x4
47
40/* 48/*
41 * Change frequency of core dpll 49 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 50 * FIXEDDELAY should be initialized to 0xf. This apparently was
43 * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for 51 * empirically determined during process testing, so no derivation
52 * was provided.
53 */
54#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
55
56/* SDRC_DLLA_STATUS bit settings */
57#define LOCKSTATUS_MASK 0x4
58
59/* SDRC_POWER bit settings */
60#define SRFRONIDLEREQ_MASK 0x40
61
62/* CM_IDLEST1_CORE bit settings */
63#define ST_SDRC_MASK 0x2
64
65/* CM_ICLKEN1_CORE bit settings */
66#define EN_SDRC_MASK 0x2
67
68/* CM_CLKSEL1_PLL bit settings */
69#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
70
71/*
72 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
73 *
74 * Params passed in registers:
75 * r0 = new M2 divider setting (only 1 and 2 supported right now)
76 * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
44 * SDRC rates < 83MHz 77 * SDRC rates < 83MHz
78 * r2 = number of MPU cycles to wait for SDRC to stabilize after
79 * reprogramming the SDRC when switching to a slower MPU speed
80 * r3 = increasing SDRC rate? (1 = yes, 0 = no)
81 *
82 * Params passed via the stack. The needed params will be copied in SRAM
83 * before use by the code in SRAM (SDRAM is not accessible during SDRC
84 * reconfiguration):
85 * new SDRC_RFR_CTRL_0 register contents
86 * new SDRC_ACTIM_CTRL_A_0 register contents
87 * new SDRC_ACTIM_CTRL_B_0 register contents
88 * new SDRC_MR_0 register value
89 * new SDRC_RFR_CTRL_1 register contents
90 * new SDRC_ACTIM_CTRL_A_1 register contents
91 * new SDRC_ACTIM_CTRL_B_1 register contents
92 * new SDRC_MR_1 register value
93 *
94 * If the param SDRC_RFR_CTRL_1 is 0, the parameters
95 * are not programmed into the SDRC CS1 registers
45 */ 96 */
46ENTRY(omap3_sram_configure_core_dpll) 97ENTRY(omap3_sram_configure_core_dpll)
47 stmfd sp!, {r1-r12, lr} @ store regs to stack 98 stmfd sp!, {r1-r12, lr} @ store regs to stack
48 ldr r4, [sp, #52] @ pull extra args off the stack 99
100 @ pull the extra args off the stack
101 @ and store them in SRAM
102 ldr r4, [sp, #52]
103 str r4, omap_sdrc_rfr_ctrl_0_val
104 ldr r4, [sp, #56]
105 str r4, omap_sdrc_actim_ctrl_a_0_val
106 ldr r4, [sp, #60]
107 str r4, omap_sdrc_actim_ctrl_b_0_val
108 ldr r4, [sp, #64]
109 str r4, omap_sdrc_mr_0_val
110 ldr r4, [sp, #68]
111 str r4, omap_sdrc_rfr_ctrl_1_val
112 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
113 beq skip_cs1_params @ do not use cs1 params
114 ldr r4, [sp, #72]
115 str r4, omap_sdrc_actim_ctrl_a_1_val
116 ldr r4, [sp, #76]
117 str r4, omap_sdrc_actim_ctrl_b_1_val
118 ldr r4, [sp, #80]
119 str r4, omap_sdrc_mr_1_val
120skip_cs1_params:
49 dsb @ flush buffered writes to interconnect 121 dsb @ flush buffered writes to interconnect
50 cmp r3, #0x2 122
51 blne configure_sdrc 123 cmp r3, #1 @ if increasing SDRC clk rate,
52 cmp r4, #0x1 124 bleq configure_sdrc @ program the SDRC regs early (for RFR)
125 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
53 bleq unlock_dll 126 bleq unlock_dll
54 blne lock_dll 127 blne lock_dll
55 bl sdram_in_selfrefresh @ put the SDRAM in self refresh 128 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
56 bl configure_core_dpll 129 bl configure_core_dpll @ change the DPLL3 M2 divider
57 bl enable_sdrc 130 mov r12, r2
58 cmp r4, #0x1 131 bl wait_clk_stable @ wait for SDRC to stabilize
132 bl enable_sdrc @ take SDRC out of idle
133 cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
59 bleq wait_dll_unlock 134 bleq wait_dll_unlock
60 blne wait_dll_lock 135 blne wait_dll_lock
61 cmp r3, #0x1 136 cmp r3, #1 @ if increasing SDRC clk rate,
62 blne configure_sdrc 137 beq return_to_sdram @ return to SDRAM code, otherwise,
138 bl configure_sdrc @ reprogram SDRC regs now
139return_to_sdram:
63 isb @ prevent speculative exec past here 140 isb @ prevent speculative exec past here
64 mov r0, #0 @ return value 141 mov r0, #0 @ return value
65 ldmfd sp!, {r1-r12, pc} @ restore regs and return 142 ldmfd sp!, {r1-r12, pc} @ restore regs and return
66unlock_dll: 143unlock_dll:
67 ldr r11, omap3_sdrc_dlla_ctrl 144 ldr r11, omap3_sdrc_dlla_ctrl
68 ldr r12, [r11] 145 ldr r12, [r11]
69 orr r12, r12, #0x4 146 bic r12, r12, #FIXEDDELAY_MASK
147 orr r12, r12, #FIXEDDELAY_DEFAULT
148 orr r12, r12, #DLLIDLE_MASK
70 str r12, [r11] @ (no OCP barrier needed) 149 str r12, [r11] @ (no OCP barrier needed)
71 bx lr 150 bx lr
72lock_dll: 151lock_dll:
73 ldr r11, omap3_sdrc_dlla_ctrl 152 ldr r11, omap3_sdrc_dlla_ctrl
74 ldr r12, [r11] 153 ldr r12, [r11]
75 bic r12, r12, #0x4 154 bic r12, r12, #DLLIDLE_MASK
76 str r12, [r11] @ (no OCP barrier needed) 155 str r12, [r11] @ (no OCP barrier needed)
77 bx lr 156 bx lr
78sdram_in_selfrefresh: 157sdram_in_selfrefresh:
79 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register 158 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
80 ldr r12, [r11] @ read the contents of SDRC_POWER 159 ldr r12, [r11] @ read the contents of SDRC_POWER
81 mov r9, r12 @ keep a copy of SDRC_POWER bits 160 mov r9, r12 @ keep a copy of SDRC_POWER bits
82 orr r12, r12, #0x40 @ enable self refresh on idle req 161 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
83 bic r12, r12, #0x4 @ clear PWDENA
84 str r12, [r11] @ write back to SDRC_POWER register 162 str r12, [r11] @ write back to SDRC_POWER register
85 ldr r12, [r11] @ posted-write barrier for SDRC 163 ldr r12, [r11] @ posted-write barrier for SDRC
164idle_sdrc:
86 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg 165 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
87 ldr r12, [r11] 166 ldr r12, [r11]
88 bic r12, r12, #0x2 @ disable iclk bit for SDRC 167 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
89 str r12, [r11] 168 str r12, [r11]
90wait_sdrc_idle: 169wait_sdrc_idle:
91 ldr r11, omap3_cm_idlest1_core 170 ldr r11, omap3_cm_idlest1_core
92 ldr r12, [r11] 171 ldr r12, [r11]
93 and r12, r12, #0x2 @ check for SDRC idle 172 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
94 cmp r12, #2 173 cmp r12, #ST_SDRC_MASK
95 bne wait_sdrc_idle 174 bne wait_sdrc_idle
96 bx lr 175 bx lr
97configure_core_dpll: 176configure_core_dpll:
@@ -99,36 +178,23 @@ configure_core_dpll:
99 ldr r12, [r11] 178 ldr r12, [r11]
100 ldr r10, core_m2_mask_val @ modify m2 for core dpll 179 ldr r10, core_m2_mask_val @ modify m2 for core dpll
101 and r12, r12, r10 180 and r12, r12, r10
102 orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val 181 orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
103 str r12, [r11] 182 str r12, [r11]
104 ldr r12, [r11] @ posted-write barrier for CM 183 ldr r12, [r11] @ posted-write barrier for CM
105 mov r12, #0x800 @ wait for the clock to stabilise
106 cmp r3, #2
107 bne wait_clk_stable
108 bx lr 184 bx lr
109wait_clk_stable: 185wait_clk_stable:
110 subs r12, r12, #1 186 subs r12, r12, #1
111 bne wait_clk_stable 187 bne wait_clk_stable
112 nop
113 nop
114 nop
115 nop
116 nop
117 nop
118 nop
119 nop
120 nop
121 nop
122 bx lr 188 bx lr
123enable_sdrc: 189enable_sdrc:
124 ldr r11, omap3_cm_iclken1_core 190 ldr r11, omap3_cm_iclken1_core
125 ldr r12, [r11] 191 ldr r12, [r11]
126 orr r12, r12, #0x2 @ enable iclk bit for SDRC 192 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
127 str r12, [r11] 193 str r12, [r11]
128wait_sdrc_idle1: 194wait_sdrc_idle1:
129 ldr r11, omap3_cm_idlest1_core 195 ldr r11, omap3_cm_idlest1_core
130 ldr r12, [r11] 196 ldr r12, [r11]
131 and r12, r12, #0x2 197 and r12, r12, #ST_SDRC_MASK
132 cmp r12, #0 198 cmp r12, #0
133 bne wait_sdrc_idle1 199 bne wait_sdrc_idle1
134restore_sdrc_power_val: 200restore_sdrc_power_val:
@@ -138,25 +204,46 @@ restore_sdrc_power_val:
138wait_dll_lock: 204wait_dll_lock:
139 ldr r11, omap3_sdrc_dlla_status 205 ldr r11, omap3_sdrc_dlla_status
140 ldr r12, [r11] 206 ldr r12, [r11]
141 and r12, r12, #0x4 207 and r12, r12, #LOCKSTATUS_MASK
142 cmp r12, #0x4 208 cmp r12, #LOCKSTATUS_MASK
143 bne wait_dll_lock 209 bne wait_dll_lock
144 bx lr 210 bx lr
145wait_dll_unlock: 211wait_dll_unlock:
146 ldr r11, omap3_sdrc_dlla_status 212 ldr r11, omap3_sdrc_dlla_status
147 ldr r12, [r11] 213 ldr r12, [r11]
148 and r12, r12, #0x4 214 and r12, r12, #LOCKSTATUS_MASK
149 cmp r12, #0x0 215 cmp r12, #0x0
150 bne wait_dll_unlock 216 bne wait_dll_unlock
151 bx lr 217 bx lr
152configure_sdrc: 218configure_sdrc:
153 ldr r11, omap3_sdrc_rfr_ctrl 219 ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
154 str r0, [r11] 220 ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
155 ldr r11, omap3_sdrc_actim_ctrla 221 str r12, [r11] @ store
156 str r1, [r11] 222 ldr r12, omap_sdrc_actim_ctrl_a_0_val
157 ldr r11, omap3_sdrc_actim_ctrlb 223 ldr r11, omap3_sdrc_actim_ctrl_a_0
158 str r2, [r11] 224 str r12, [r11]
159 ldr r2, [r11] @ posted-write barrier for SDRC 225 ldr r12, omap_sdrc_actim_ctrl_b_0_val
226 ldr r11, omap3_sdrc_actim_ctrl_b_0
227 str r12, [r11]
228 ldr r12, omap_sdrc_mr_0_val
229 ldr r11, omap3_sdrc_mr_0
230 str r12, [r11]
231 ldr r12, omap_sdrc_rfr_ctrl_1_val
232 cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
233 beq skip_cs1_prog @ do not program cs1 params
234 ldr r11, omap3_sdrc_rfr_ctrl_1
235 str r12, [r11]
236 ldr r12, omap_sdrc_actim_ctrl_a_1_val
237 ldr r11, omap3_sdrc_actim_ctrl_a_1
238 str r12, [r11]
239 ldr r12, omap_sdrc_actim_ctrl_b_1_val
240 ldr r11, omap3_sdrc_actim_ctrl_b_1
241 str r12, [r11]
242 ldr r12, omap_sdrc_mr_1_val
243 ldr r11, omap3_sdrc_mr_1
244 str r12, [r11]
245skip_cs1_prog:
246 ldr r12, [r11] @ posted-write barrier for SDRC
160 bx lr 247 bx lr
161 248
162omap3_sdrc_power: 249omap3_sdrc_power:
@@ -167,12 +254,40 @@ omap3_cm_idlest1_core:
167 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) 254 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
168omap3_cm_iclken1_core: 255omap3_cm_iclken1_core:
169 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1) 256 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
170omap3_sdrc_rfr_ctrl: 257
258omap3_sdrc_rfr_ctrl_0:
171 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0) 259 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
172omap3_sdrc_actim_ctrla: 260omap3_sdrc_rfr_ctrl_1:
261 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
262omap3_sdrc_actim_ctrl_a_0:
173 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) 263 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
174omap3_sdrc_actim_ctrlb: 264omap3_sdrc_actim_ctrl_a_1:
265 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
266omap3_sdrc_actim_ctrl_b_0:
175 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) 267 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
268omap3_sdrc_actim_ctrl_b_1:
269 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
270omap3_sdrc_mr_0:
271 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
272omap3_sdrc_mr_1:
273 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
274omap_sdrc_rfr_ctrl_0_val:
275 .word 0xDEADBEEF
276omap_sdrc_rfr_ctrl_1_val:
277 .word 0xDEADBEEF
278omap_sdrc_actim_ctrl_a_0_val:
279 .word 0xDEADBEEF
280omap_sdrc_actim_ctrl_a_1_val:
281 .word 0xDEADBEEF
282omap_sdrc_actim_ctrl_b_0_val:
283 .word 0xDEADBEEF
284omap_sdrc_actim_ctrl_b_1_val:
285 .word 0xDEADBEEF
286omap_sdrc_mr_0_val:
287 .word 0xDEADBEEF
288omap_sdrc_mr_1_val:
289 .word 0xDEADBEEF
290
176omap3_sdrc_dlla_status: 291omap3_sdrc_dlla_status:
177 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 292 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
178omap3_sdrc_dlla_ctrl: 293omap3_sdrc_dlla_ctrl:
@@ -182,3 +297,4 @@ core_m2_mask_val:
182 297
183ENTRY(omap3_sram_configure_core_dpll_sz) 298ENTRY(omap3_sram_configure_core_dpll_sz)
184 .word . - omap3_sram_configure_core_dpll 299 .word . - omap3_sram_configure_core_dpll
300
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-05 14:09:52 -0500