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-rw-r--r--arch/arm/mach-omap2/sram34xx.S129
1 files changed, 85 insertions, 44 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index c080c82521e1..f41f8d96ddba 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -3,13 +3,12 @@
3 * 3 *
4 * Omap3 specific functions that need to be run in internal SRAM 4 * Omap3 specific functions that need to be run in internal SRAM
5 * 5 *
6 * (C) Copyright 2007 6 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Texas Instruments Inc. 7 * Copyright (C) 2008 Nokia Corporation
8 * Rajendra Nayak <rnayak@ti.com>
9 * 8 *
10 * (C) Copyright 2004 9 * Rajendra Nayak <rnayak@ti.com>
11 * Texas Instruments, <www.ti.com>
12 * Richard Woodruff <r-woodruff2@ti.com> 10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Paul Walmsley
13 * 12 *
14 * This program is free software; you can redistribute it and/or 13 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as 14 * modify it under the terms of the GNU General Public License as
@@ -37,61 +36,112 @@
37 36
38 .text 37 .text
39 38
39/* r4 parameters */
40#define SDRC_NO_UNLOCK_DLL 0x0
41#define SDRC_UNLOCK_DLL 0x1
42
43/* SDRC_DLLA_CTRL bit settings */
44#define FIXEDDELAY_SHIFT 24
45#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
46#define DLLIDLE_MASK 0x4
47
48/*
49 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
50 * FIXEDDELAY should be initialized to 0xf. This apparently was
51 * empirically determined during process testing, so no derivation
52 * was provided.
53 */
54#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
55
56/* SDRC_DLLA_STATUS bit settings */
57#define LOCKSTATUS_MASK 0x4
58
59/* SDRC_POWER bit settings */
60#define SRFRONIDLEREQ_MASK 0x40
61#define PWDENA_MASK 0x4
62
63/* CM_IDLEST1_CORE bit settings */
64#define ST_SDRC_MASK 0x2
65
66/* CM_ICLKEN1_CORE bit settings */
67#define EN_SDRC_MASK 0x2
68
69/* CM_CLKSEL1_PLL bit settings */
70#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
71
40/* 72/*
41 * Change frequency of core dpll 73 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 74 * r0 = new SDRC_RFR_CTRL register contents
43 * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for 75 * r1 = new SDRC_ACTIM_CTRLA register contents
76 * r2 = new SDRC_ACTIM_CTRLB register contents
77 * r3 = new M2 divider setting (only 1 and 2 supported right now)
78 * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
44 * SDRC rates < 83MHz 79 * SDRC rates < 83MHz
80 * r5 = number of MPU cycles to wait for SDRC to stabilize after
81 * reprogramming the SDRC when switching to a slower MPU speed
82 * r6 = new SDRC_MR_0 register value
83 * r7 = increasing SDRC rate? (1 = yes, 0 = no)
84 *
45 */ 85 */
46ENTRY(omap3_sram_configure_core_dpll) 86ENTRY(omap3_sram_configure_core_dpll)
47 stmfd sp!, {r1-r12, lr} @ store regs to stack 87 stmfd sp!, {r1-r12, lr} @ store regs to stack
48 ldr r4, [sp, #52] @ pull extra args off the stack 88 ldr r4, [sp, #52] @ pull extra args off the stack
89 ldr r5, [sp, #56] @ load extra args from the stack
90 ldr r6, [sp, #60] @ load extra args from the stack
91 ldr r7, [sp, #64] @ load extra args from the stack
49 dsb @ flush buffered writes to interconnect 92 dsb @ flush buffered writes to interconnect
50 cmp r3, #0x2 93 cmp r7, #1 @ if increasing SDRC clk rate,
51 blne configure_sdrc 94 bleq configure_sdrc @ program the SDRC regs early (for RFR)
52 cmp r4, #0x1 95 cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
53 bleq unlock_dll 96 bleq unlock_dll
54 blne lock_dll 97 blne lock_dll
55 bl sdram_in_selfrefresh @ put the SDRAM in self refresh 98 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
56 bl configure_core_dpll 99 bl configure_core_dpll @ change the DPLL3 M2 divider
57 bl enable_sdrc 100 bl enable_sdrc @ take SDRC out of idle
58 cmp r4, #0x1 101 cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
59 bleq wait_dll_unlock 102 bleq wait_dll_unlock
60 blne wait_dll_lock 103 blne wait_dll_lock
61 cmp r3, #0x1 104 cmp r7, #1 @ if increasing SDRC clk rate,
62 blne configure_sdrc 105 beq return_to_sdram @ return to SDRAM code, otherwise,
106 bl configure_sdrc @ reprogram SDRC regs now
107 mov r12, r5
108 bl wait_clk_stable @ wait for SDRC to stabilize
109return_to_sdram:
63 isb @ prevent speculative exec past here 110 isb @ prevent speculative exec past here
64 mov r0, #0 @ return value 111 mov r0, #0 @ return value
65 ldmfd sp!, {r1-r12, pc} @ restore regs and return 112 ldmfd sp!, {r1-r12, pc} @ restore regs and return
66unlock_dll: 113unlock_dll:
67 ldr r11, omap3_sdrc_dlla_ctrl 114 ldr r11, omap3_sdrc_dlla_ctrl
68 ldr r12, [r11] 115 ldr r12, [r11]
69 orr r12, r12, #0x4 116 and r12, r12, #FIXEDDELAY_MASK
117 orr r12, r12, #FIXEDDELAY_DEFAULT
118 orr r12, r12, #DLLIDLE_MASK
70 str r12, [r11] @ (no OCP barrier needed) 119 str r12, [r11] @ (no OCP barrier needed)
71 bx lr 120 bx lr
72lock_dll: 121lock_dll:
73 ldr r11, omap3_sdrc_dlla_ctrl 122 ldr r11, omap3_sdrc_dlla_ctrl
74 ldr r12, [r11] 123 ldr r12, [r11]
75 bic r12, r12, #0x4 124 bic r12, r12, #DLLIDLE_MASK
76 str r12, [r11] @ (no OCP barrier needed) 125 str r12, [r11] @ (no OCP barrier needed)
77 bx lr 126 bx lr
78sdram_in_selfrefresh: 127sdram_in_selfrefresh:
79 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register 128 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
80 ldr r12, [r11] @ read the contents of SDRC_POWER 129 ldr r12, [r11] @ read the contents of SDRC_POWER
81 mov r9, r12 @ keep a copy of SDRC_POWER bits 130 mov r9, r12 @ keep a copy of SDRC_POWER bits
82 orr r12, r12, #0x40 @ enable self refresh on idle req 131 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
83 bic r12, r12, #0x4 @ clear PWDENA 132 bic r12, r12, #PWDENA_MASK @ clear PWDENA
84 str r12, [r11] @ write back to SDRC_POWER register 133 str r12, [r11] @ write back to SDRC_POWER register
85 ldr r12, [r11] @ posted-write barrier for SDRC 134 ldr r12, [r11] @ posted-write barrier for SDRC
135idle_sdrc:
86 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg 136 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
87 ldr r12, [r11] 137 ldr r12, [r11]
88 bic r12, r12, #0x2 @ disable iclk bit for SDRC 138 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
89 str r12, [r11] 139 str r12, [r11]
90wait_sdrc_idle: 140wait_sdrc_idle:
91 ldr r11, omap3_cm_idlest1_core 141 ldr r11, omap3_cm_idlest1_core
92 ldr r12, [r11] 142 ldr r12, [r11]
93 and r12, r12, #0x2 @ check for SDRC idle 143 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
94 cmp r12, #2 144 cmp r12, #ST_SDRC_MASK
95 bne wait_sdrc_idle 145 bne wait_sdrc_idle
96 bx lr 146 bx lr
97configure_core_dpll: 147configure_core_dpll:
@@ -99,36 +149,23 @@ configure_core_dpll:
99 ldr r12, [r11] 149 ldr r12, [r11]
100 ldr r10, core_m2_mask_val @ modify m2 for core dpll 150 ldr r10, core_m2_mask_val @ modify m2 for core dpll
101 and r12, r12, r10 151 and r12, r12, r10
102 orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val 152 orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
103 str r12, [r11] 153 str r12, [r11]
104 ldr r12, [r11] @ posted-write barrier for CM 154 ldr r12, [r11] @ posted-write barrier for CM
105 mov r12, #0x800 @ wait for the clock to stabilise
106 cmp r3, #2
107 bne wait_clk_stable
108 bx lr 155 bx lr
109wait_clk_stable: 156wait_clk_stable:
110 subs r12, r12, #1 157 subs r12, r12, #1
111 bne wait_clk_stable 158 bne wait_clk_stable
112 nop
113 nop
114 nop
115 nop
116 nop
117 nop
118 nop
119 nop
120 nop
121 nop
122 bx lr 159 bx lr
123enable_sdrc: 160enable_sdrc:
124 ldr r11, omap3_cm_iclken1_core 161 ldr r11, omap3_cm_iclken1_core
125 ldr r12, [r11] 162 ldr r12, [r11]
126 orr r12, r12, #0x2 @ enable iclk bit for SDRC 163 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
127 str r12, [r11] 164 str r12, [r11]
128wait_sdrc_idle1: 165wait_sdrc_idle1:
129 ldr r11, omap3_cm_idlest1_core 166 ldr r11, omap3_cm_idlest1_core
130 ldr r12, [r11] 167 ldr r12, [r11]
131 and r12, r12, #0x2 168 and r12, r12, #ST_SDRC_MASK
132 cmp r12, #0 169 cmp r12, #0
133 bne wait_sdrc_idle1 170 bne wait_sdrc_idle1
134restore_sdrc_power_val: 171restore_sdrc_power_val:
@@ -138,14 +175,14 @@ restore_sdrc_power_val:
138wait_dll_lock: 175wait_dll_lock:
139 ldr r11, omap3_sdrc_dlla_status 176 ldr r11, omap3_sdrc_dlla_status
140 ldr r12, [r11] 177 ldr r12, [r11]
141 and r12, r12, #0x4 178 and r12, r12, #LOCKSTATUS_MASK
142 cmp r12, #0x4 179 cmp r12, #LOCKSTATUS_MASK
143 bne wait_dll_lock 180 bne wait_dll_lock
144 bx lr 181 bx lr
145wait_dll_unlock: 182wait_dll_unlock:
146 ldr r11, omap3_sdrc_dlla_status 183 ldr r11, omap3_sdrc_dlla_status
147 ldr r12, [r11] 184 ldr r12, [r11]
148 and r12, r12, #0x4 185 and r12, r12, #LOCKSTATUS_MASK
149 cmp r12, #0x0 186 cmp r12, #0x0
150 bne wait_dll_unlock 187 bne wait_dll_unlock
151 bx lr 188 bx lr
@@ -156,7 +193,9 @@ configure_sdrc:
156 str r1, [r11] 193 str r1, [r11]
157 ldr r11, omap3_sdrc_actim_ctrlb 194 ldr r11, omap3_sdrc_actim_ctrlb
158 str r2, [r11] 195 str r2, [r11]
159 ldr r2, [r11] @ posted-write barrier for SDRC 196 ldr r11, omap3_sdrc_mr_0
197 str r6, [r11]
198 ldr r6, [r11] @ posted-write barrier for SDRC
160 bx lr 199 bx lr
161 200
162omap3_sdrc_power: 201omap3_sdrc_power:
@@ -173,6 +212,8 @@ omap3_sdrc_actim_ctrla:
173 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) 212 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
174omap3_sdrc_actim_ctrlb: 213omap3_sdrc_actim_ctrlb:
175 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) 214 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
215omap3_sdrc_mr_0:
216 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
176omap3_sdrc_dlla_status: 217omap3_sdrc_dlla_status:
177 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 218 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
178omap3_sdrc_dlla_ctrl: 219omap3_sdrc_dlla_ctrl:
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 21:11:16 -0500