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-rw-r--r--arch/arm/mach-omap2/sram34xx.S7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 8d524f305633..9a454151c422 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -77,7 +77,9 @@ lock_dll:
77sdram_in_selfrefresh: 77sdram_in_selfrefresh:
78 ldr r4, omap3_sdrc_power @ read the SDRC_POWER register 78 ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
79 ldr r5, [r4] @ read the contents of SDRC_POWER 79 ldr r5, [r4] @ read the contents of SDRC_POWER
80 mov r9, r5 @ keep a copy of SDRC_POWER bits
80 orr r5, r5, #0x40 @ enable self refresh on idle req 81 orr r5, r5, #0x40 @ enable self refresh on idle req
82 bic r5, r5, #0x4 @ clear PWDENA
81 str r5, [r4] @ write back to SDRC_POWER register 83 str r5, [r4] @ write back to SDRC_POWER register
82 ldr r5, [r4] @ posted-write barrier for SDRC 84 ldr r5, [r4] @ posted-write barrier for SDRC
83 ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg 85 ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
@@ -128,10 +130,9 @@ wait_sdrc_idle1:
128 and r5, r5, #0x2 130 and r5, r5, #0x2
129 cmp r5, #0 131 cmp r5, #0
130 bne wait_sdrc_idle1 132 bne wait_sdrc_idle1
133restore_sdrc_power_val:
131 ldr r4, omap3_sdrc_power 134 ldr r4, omap3_sdrc_power
132 ldr r5, [r4] 135 str r9, [r4] @ restore SDRC_POWER, no barrier needed
133 bic r5, r5, #0x40
134 str r5, [r4]
135 bx lr 136 bx lr
136wait_dll_lock: 137wait_dll_lock:
137 ldr r4, omap3_sdrc_dlla_status 138 ldr r4, omap3_sdrc_dlla_status