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-rw-r--r--arch/arm/mach-omap2/sram34xx.S2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 3aef7448b2a5..9c2d0465a83c 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -58,7 +58,6 @@
58 58
59/* SDRC_POWER bit settings */ 59/* SDRC_POWER bit settings */
60#define SRFRONIDLEREQ_MASK 0x40 60#define SRFRONIDLEREQ_MASK 0x40
61#define PWDENA_MASK 0x4
62 61
63/* CM_IDLEST1_CORE bit settings */ 62/* CM_IDLEST1_CORE bit settings */
64#define ST_SDRC_MASK 0x2 63#define ST_SDRC_MASK 0x2
@@ -160,7 +159,6 @@ sdram_in_selfrefresh:
160 ldr r12, [r11] @ read the contents of SDRC_POWER 159 ldr r12, [r11] @ read the contents of SDRC_POWER
161 mov r9, r12 @ keep a copy of SDRC_POWER bits 160 mov r9, r12 @ keep a copy of SDRC_POWER bits
162 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle 161 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
163 bic r12, r12, #PWDENA_MASK @ clear PWDENA
164 str r12, [r11] @ write back to SDRC_POWER register 162 str r12, [r11] @ write back to SDRC_POWER register
165 ldr r12, [r11] @ posted-write barrier for SDRC 163 ldr r12, [r11] @ posted-write barrier for SDRC
166idle_sdrc: 164idle_sdrc: