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-rw-r--r--arch/arm/mach-omap2/sram34xx.S13
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 35131e5bc7d1..c080c82521e1 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -40,22 +40,23 @@
40/* 40/*
41 * Change frequency of core dpll 41 * Change frequency of core dpll
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
43 * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
44 * SDRC rates < 83MHz
43 */ 45 */
44ENTRY(omap3_sram_configure_core_dpll) 46ENTRY(omap3_sram_configure_core_dpll)
45 stmfd sp!, {r1-r12, lr} @ store regs to stack 47 stmfd sp!, {r1-r12, lr} @ store regs to stack
48 ldr r4, [sp, #52] @ pull extra args off the stack
46 dsb @ flush buffered writes to interconnect 49 dsb @ flush buffered writes to interconnect
47 cmp r3, #0x2 50 cmp r3, #0x2
48 blne configure_sdrc 51 blne configure_sdrc
49 cmp r3, #0x2 52 cmp r4, #0x1
53 bleq unlock_dll
50 blne lock_dll 54 blne lock_dll
51 cmp r3, #0x1
52 blne unlock_dll
53 bl sdram_in_selfrefresh @ put the SDRAM in self refresh 55 bl sdram_in_selfrefresh @ put the SDRAM in self refresh
54 bl configure_core_dpll 56 bl configure_core_dpll
55 bl enable_sdrc 57 bl enable_sdrc
56 cmp r3, #0x1 58 cmp r4, #0x1
57 blne wait_dll_unlock 59 bleq wait_dll_unlock
58 cmp r3, #0x2
59 blne wait_dll_lock 60 blne wait_dll_lock
60 cmp r3, #0x1 61 cmp r3, #0x1
61 blne configure_sdrc 62 blne configure_sdrc