1 files changed, 51 insertions, 54 deletions

diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 4a9e49140716..4c274510f3e9 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-omap2/sram-fn.S
+ * linux/arch/arm/mach-omap2/sram242x.S
  *
  * Omap2 specific functions that need to be run in internal SRAM
  *
@@ -27,22 +27,20 @@
 #include <asm/arch/io.h>
 #include <asm/hardware.h>
 
-#include "sdrc.h"
 #include "prm.h"
 #include "cm.h"
-
-#define TIMER_32KSYNCT_CR_V     IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
+#include "sdrc.h"
 
         .text
 
-ENTRY(sram_ddr_init)
+ENTRY(omap242x_sram_ddr_init)
         stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
 
         mov     r12, r2                 @ capture CS1 vs CS0
         mov     r8, r3                  @ capture force parameter
 
         /* frequency shift down */
-        ldr     r2, cm_clksel2_pll      @ get address of dpllout reg
+        ldr     r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
         mov     r3, #0x1                @ value for 1x operation
         str     r3, [r2]                @ go to L1-freq operation
 
@@ -51,7 +49,7 @@ ENTRY(sram_ddr_init)
         bl voltage_shift                @ go drop voltage
 
         /* dll lock mode */
-        ldr     r11, sdrc_dlla_ctrl     @ addr of dlla ctrl
+        ldr     r11, omap242x_sdi_sdrc_dlla_ctrl        @ addr of dlla ctrl
         ldr     r10, [r11]              @ get current val
         cmp     r12, #0x1               @ cs1 base (2422 es2.05/1)
         addeq   r11, r11, #0x8          @ if cs1 base, move to DLLB
@@ -102,7 +100,7 @@ i_dll_delay:
          * wait for it to finish, use 32k sync counter, 1tick=31uS.
          */
 voltage_shift:
-        ldr     r4, prcm_voltctrl       @ get addr of volt ctrl.
+        ldr     r4, omap242x_sdi_prcm_voltctrl  @ get addr of volt ctrl.
         ldr     r5, [r4]                @ get value.
         ldr     r6, prcm_mask_val       @ get value of mask
         and     r5, r5, r6              @ apply mask to clear bits
@@ -112,7 +110,7 @@ voltage_shift:
         orr     r5, r5, r3              @ build value for force
         str     r5, [r4]                @ Force transition to L1
 
-        ldr     r3, timer_32ksynct_cr   @ get addr of counter
+        ldr     r3, omap242x_sdi_timer_32ksynct_cr      @ get addr of counter
         ldr     r5, [r3]                @ get value
         add     r5, r5, #0x3            @ give it at most 93uS
 volt_delay:
@@ -121,32 +119,31 @@ volt_delay:
         bhi     volt_delay              @ not yet->branch
         mov     pc, lr                  @ back to caller.
 
-/* relative load constants */
-cm_clksel2_pll:
+omap242x_sdi_cm_clksel2_pll:
         .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-sdrc_dlla_ctrl:
+omap242x_sdi_sdrc_dlla_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-prcm_voltctrl:
-        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
+omap242x_sdi_prcm_voltctrl:
+        .word OMAP242X_PRCM_VOLTCTRL
 prcm_mask_val:
         .word 0xFFFF3FFC
-timer_32ksynct_cr:
-        .word TIMER_32KSYNCT_CR_V
-ENTRY(sram_ddr_init_sz)
-        .word   . - sram_ddr_init
+omap242x_sdi_timer_32ksynct_cr:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+ENTRY(omap242x_sram_ddr_init_sz)
+        .word   . - omap242x_sram_ddr_init
 
 /*
  * Reprograms memory timings.
  * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
  * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
  */
-ENTRY(sram_reprogram_sdrc)
+ENTRY(omap242x_sram_reprogram_sdrc)
         stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
         mov     r3, #0x0                @ clear for mrc call
         mcr     p15, 0, r3, c7, c10, 4  @ memory barrier, finish ARM SDR/DDR
         nop
         nop
-        ldr     r6, ddr_sdrc_rfr_ctrl   @ get addr of refresh reg
+        ldr     r6, omap242x_srs_sdrc_rfr_ctrl  @ get addr of refresh reg
         ldr     r5, [r6]                @ get value
         mov     r5, r5, lsr #8          @ isolate rfr field and drop burst
 
@@ -160,7 +157,7 @@ ENTRY(sram_reprogram_sdrc)
         movne   r5, r5, lsl #1          @ mult by 2 if to full
         mov     r5, r5, lsl #8          @ put rfr field back into place
         add     r5, r5, #0x1            @ turn on burst of 1
-        ldr     r4, ddr_cm_clksel2_pll  @ get address of out reg
+        ldr     r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
         ldr     r3, [r4]                @ get curr value
         orr     r3, r3, #0x3
         bic     r3, r3, #0x3            @ clear lower bits
@@ -181,7 +178,7 @@ ENTRY(sram_reprogram_sdrc)
         bne     freq_out                @ leave if SDR, no DLL function
 
         /* With DDR, we need to take care of the DLL for the frequency change */
-        ldr     r2, ddr_sdrc_dlla_ctrl  @ addr of dlla ctrl
+        ldr     r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
         str     r1, [r2]                @ write out new SDRC_DLLA_CTRL
         add     r2, r2, #0x8            @ addr to SDRC_DLLB_CTRL
         str     r1, [r2]                @ commit to SDRC_DLLB_CTRL
@@ -197,7 +194,7 @@ freq_out:
      *  wait for it to finish, use 32k sync counter, 1tick=31uS.
      */
 voltage_shift_c:
-        ldr     r10, ddr_prcm_voltctrl  @ get addr of volt ctrl
+        ldr     r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
         ldr     r8, [r10]               @ get value
         ldr     r7, ddr_prcm_mask_val   @ get value of mask
         and     r8, r8, r7              @ apply mask to clear bits
@@ -207,7 +204,7 @@ voltage_shift_c:
         orr     r8, r8, r7              @ build value for force
         str     r8, [r10]               @ Force transition to L1
 
-        ldr     r10, ddr_timer_32ksynct @ get addr of counter
+        ldr     r10, omap242x_srs_timer_32ksynct        @ get addr of counter
         ldr     r8, [r10]               @ get value
         add     r8, r8, #0x2            @ give it at most 62uS (min 31+)
 volt_delay_c:
@@ -216,39 +213,39 @@ volt_delay_c:
         bhi     volt_delay_c            @ not yet->branch
         mov     pc, lr                  @ back to caller
 
-ddr_cm_clksel2_pll:
+omap242x_srs_cm_clksel2_pll:
         .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-ddr_sdrc_dlla_ctrl:
+omap242x_srs_sdrc_dlla_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-ddr_sdrc_rfr_ctrl:
+omap242x_srs_sdrc_rfr_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-ddr_prcm_voltctrl:
-        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
+omap242x_srs_prcm_voltctrl:
+        .word OMAP242X_PRCM_VOLTCTRL
 ddr_prcm_mask_val:
         .word 0xFFFF3FFC
-ddr_timer_32ksynct:
-        .word TIMER_32KSYNCT_CR_V
+omap242x_srs_timer_32ksynct:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
 
-ENTRY(sram_reprogram_sdrc_sz)
-        .word   . - sram_reprogram_sdrc
+ENTRY(omap242x_sram_reprogram_sdrc_sz)
+        .word   . - omap242x_sram_reprogram_sdrc
 
 /*
  * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
  */
-ENTRY(sram_set_prcm)
+ENTRY(omap242x_sram_set_prcm)
         stmfd   sp!, {r0-r12, lr}       @ regs to stack
         adr     r4, pbegin              @ addr of preload start
         adr     r8, pend                @ addr of preload end
         mcrr    p15, 1, r8, r4, c12     @ preload into icache
 pbegin:
         /* move into fast relock bypass */
-        ldr     r8, pll_ctl             @ get addr
+        ldr     r8, omap242x_ssp_pll_ctl        @ get addr
         ldr     r5, [r8]                @ get val
         mvn     r6, #0x3                @ clear mask
         and     r5, r5, r6              @ clear field
         orr     r7, r5, #0x2            @ fast relock val
         str     r7, [r8]                @ go to fast relock
-        ldr     r4, pll_stat            @ addr of stat
+        ldr     r4, omap242x_ssp_pll_stat       @ addr of stat
 block:
         /* wait for bypass */
         ldr     r8, [r4]                @ stat value
@@ -257,10 +254,10 @@ block:
         bne     block                   @ loop if not
 
         /* set new dpll dividers _after_ in bypass */
-        ldr     r4, pll_div             @ get addr
+        ldr     r4, omap242x_ssp_pll_div        @ get addr
         str     r0, [r4]                @ set dpll ctrl val
 
-        ldr     r4, set_config          @ get addr
+        ldr     r4, omap242x_ssp_set_config     @ get addr
         mov     r8, #1                  @ valid cfg msk
         str     r8, [r4]                @ make dividers take
 
@@ -274,8 +271,8 @@ wait_a_bit:
         beq     pend                    @ jump over dpll relock
 
         /* relock DPLL with new vals */
-        ldr     r5, pll_stat            @ get addr
-        ldr     r4, pll_ctl             @ get addr
+        ldr     r5, omap242x_ssp_pll_stat       @ get addr
+        ldr     r4, omap242x_ssp_pll_ctl        @ get addr
         orr     r8, r7, #0x3            @ val for lock dpll
         str     r8, [r4]                @ set val
         mov     r0, #1000               @ dead spin a bit
@@ -289,9 +286,9 @@ wait_lock:
         bne     wait_lock               @ wait if not
 pend:
         /* update memory timings & briefly lock dll */
-        ldr     r4, sdrc_rfr            @ get addr
+        ldr     r4, omap242x_ssp_sdrc_rfr       @ get addr
         str     r1, [r4]                @ update refresh timing
-        ldr     r11, dlla_ctrl          @ get addr of DLLA ctrl
+        ldr     r11, omap242x_ssp_dlla_ctrl     @ get addr of DLLA ctrl
         ldr     r10, [r11]              @ get current val
         mvn     r9, #0x4                @ mask to get clear bit2
         and     r10, r10, r9            @ clear bit2 for lock mode
@@ -307,18 +304,18 @@ wait_dll_lock:
         nop
         ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 
-set_config:
-        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80)
-pll_ctl:
-        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1)
-pll_stat:
-        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1)
-pll_div:
-        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL)
-sdrc_rfr:
+omap242x_ssp_set_config:
+        .word OMAP242X_PRCM_CLKCFG_CTRL
+omap242x_ssp_pll_ctl:
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
+omap242x_ssp_pll_stat:
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
+omap242x_ssp_pll_div:
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
+omap242x_ssp_sdrc_rfr:
         .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-dlla_ctrl:
+omap242x_ssp_dlla_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
-ENTRY(sram_set_prcm_sz)
-        .word   . - sram_set_prcm
+ENTRY(omap242x_sram_set_prcm_sz)
+        .word   . - omap242x_sram_set_prcm