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-rw-r--r--arch/arm/mach-omap2/sleep34xx.S15
1 files changed, 3 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index a31845a201e9..f75a166f0a21 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -188,12 +188,12 @@ ENTRY(omap34xx_cpu_suspend)
188 stmfd sp!, {r0-r12, lr} @ save registers on stack 188 stmfd sp!, {r0-r12, lr} @ save registers on stack
189 189
190 /* 190 /*
191 * r0 contains restore pointer in sdram 191 * r0 contains CPU context save/restore pointer in sdram
192 * r1 contains information about saving context: 192 * r1 contains information about saving context:
193 * 0 - No context lost 193 * 0 - No context lost
194 * 1 - Only L1 and logic lost 194 * 1 - Only L1 and logic lost
195 * 2 - Only L2 lost 195 * 2 - Only L2 lost (Even L1 is retained we clean it along with L2)
196 * 3 - Both L1 and L2 lost 196 * 3 - Both L1 and L2 lost and logic lost
197 */ 197 */
198 198
199 /* Directly jump to WFI is the context save is not required */ 199 /* Directly jump to WFI is the context save is not required */
@@ -278,15 +278,6 @@ l1_logic_lost:
278 278
279clean_caches: 279clean_caches:
280 /* 280 /*
281 * Clean Data or unified cache to POU
282 * How to invalidate only L1 cache???? - #FIX_ME#
283 * mcr p15, 0, r11, c7, c11, 1
284 */
285 cmp r1, #0x1 @ Check whether L2 inval is required
286 beq omap3_do_wfi
287
288clean_l2:
289 /*
290 * jump out to kernel flush routine 281 * jump out to kernel flush routine
291 * - reuse that code is better 282 * - reuse that code is better
292 * - it executes in a cached space so is faster than refetch per-block 283 * - it executes in a cached space so is faster than refetch per-block