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-rw-r--r--arch/arm/mach-omap2/serial.c907
1 files changed, 242 insertions, 665 deletions
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 42c326732a29..247d89478f24 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -19,26 +19,21 @@
19 */ 19 */
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/serial_reg.h>
23#include <linux/clk.h> 22#include <linux/clk.h>
24#include <linux/io.h> 23#include <linux/io.h>
25#include <linux/delay.h> 24#include <linux/delay.h>
26#include <linux/platform_device.h> 25#include <linux/platform_device.h>
27#include <linux/slab.h> 26#include <linux/slab.h>
28#include <linux/serial_8250.h>
29#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
30#include <linux/console.h> 28#include <linux/console.h>
31 29
32#ifdef CONFIG_SERIAL_OMAP
33#include <plat/omap-serial.h> 30#include <plat/omap-serial.h>
34#endif
35
36#include "common.h" 31#include "common.h"
37#include <plat/board.h> 32#include <plat/board.h>
38#include <plat/clock.h>
39#include <plat/dma.h> 33#include <plat/dma.h>
40#include <plat/omap_hwmod.h> 34#include <plat/omap_hwmod.h>
41#include <plat/omap_device.h> 35#include <plat/omap_device.h>
36#include <plat/omap-pm.h>
42 37
43#include "prm2xxx_3xxx.h" 38#include "prm2xxx_3xxx.h"
44#include "pm.h" 39#include "pm.h"
@@ -47,603 +42,226 @@
47#include "control.h" 42#include "control.h"
48#include "mux.h" 43#include "mux.h"
49 44
50#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
51#define UART_OMAP_WER 0x17 /* Wake-up enable register */
52
53#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
54#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
55
56/* 45/*
57 * NOTE: By default the serial timeout is disabled as it causes lost characters 46 * NOTE: By default the serial auto_suspend timeout is disabled as it causes
58 * over the serial ports. This means that the UART clocks will stay on until 47 * lost characters over the serial ports. This means that the UART clocks will
59 * disabled via sysfs. This also causes that any deeper omap sleep states are 48 * stay on until power/autosuspend_delay is set for the uart from sysfs.
60 * blocked. 49 * This also causes that any deeper omap sleep states are blocked.
61 */ 50 */
62#define DEFAULT_TIMEOUT 0 51#define DEFAULT_AUTOSUSPEND_DELAY -1
63 52
64#define MAX_UART_HWMOD_NAME_LEN 16 53#define MAX_UART_HWMOD_NAME_LEN 16
65 54
66struct omap_uart_state { 55struct omap_uart_state {
67 int num; 56 int num;
68 int can_sleep; 57 int can_sleep;
69 struct timer_list timer;
70 u32 timeout;
71
72 void __iomem *wk_st;
73 void __iomem *wk_en;
74 u32 wk_mask;
75 u32 padconf;
76 u32 dma_enabled;
77
78 struct clk *ick;
79 struct clk *fck;
80 int clocked;
81
82 int irq;
83 int regshift;
84 int irqflags;
85 void __iomem *membase;
86 resource_size_t mapbase;
87 58
88 struct list_head node; 59 struct list_head node;
89 struct omap_hwmod *oh; 60 struct omap_hwmod *oh;
90 struct platform_device *pdev; 61 struct platform_device *pdev;
91
92 u32 errata;
93#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
94 int context_valid;
95
96 /* Registers to be saved/restored for OFF-mode */
97 u16 dll;
98 u16 dlh;
99 u16 ier;
100 u16 sysc;
101 u16 scr;
102 u16 wer;
103 u16 mcr;
104#endif
105}; 62};
106 63
107static LIST_HEAD(uart_list); 64static LIST_HEAD(uart_list);
108static u8 num_uarts; 65static u8 num_uarts;
66static u8 console_uart_id = -1;
67static u8 no_console_suspend;
68static u8 uart_debug;
69
70#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */
71#define DEFAULT_RXDMA_BUFSIZE 4096 /* RX DMA buffer size */
72#define DEFAULT_RXDMA_TIMEOUT (3 * HZ)/* RX DMA timeout (jiffies) */
73
74static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
75 {
76 .dma_enabled = false,
77 .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
78 .dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
79 .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
80 .autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
81 },
82};
109 83
110static inline unsigned int __serial_read_reg(struct uart_port *up, 84#ifdef CONFIG_PM
111 int offset) 85static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
112{
113 offset <<= up->regshift;
114 return (unsigned int)__raw_readb(up->membase + offset);
115}
116
117static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
118 int offset)
119{ 86{
120 offset <<= uart->regshift; 87 struct omap_device *od = to_omap_device(pdev);
121 return (unsigned int)__raw_readb(uart->membase + offset);
122}
123 88
124static inline void __serial_write_reg(struct uart_port *up, int offset, 89 if (!od)
125 int value) 90 return;
126{
127 offset <<= up->regshift;
128 __raw_writeb(value, up->membase + offset);
129}
130 91
131static inline void serial_write_reg(struct omap_uart_state *uart, int offset, 92 if (enable)
132 int value) 93 omap_hwmod_enable_wakeup(od->hwmods[0]);
133{ 94 else
134 offset <<= uart->regshift; 95 omap_hwmod_disable_wakeup(od->hwmods[0]);
135 __raw_writeb(value, uart->membase + offset);
136} 96}
137 97
138/* 98/*
139 * Internal UARTs need to be initialized for the 8250 autoconfig to work 99 * Errata i291: [UART]:Cannot Acknowledge Idle Requests
140 * properly. Note that the TX watermark initialization may not be needed 100 * in Smartidle Mode When Configured for DMA Operations.
141 * once the 8250.c watermark handling code is merged. 101 * WA: configure uart in force idle mode.
142 */ 102 */
143 103static void omap_uart_set_noidle(struct platform_device *pdev)
144static inline void __init omap_uart_reset(struct omap_uart_state *uart)
145{ 104{
146 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 105 struct omap_device *od = to_omap_device(pdev);
147 serial_write_reg(uart, UART_OMAP_SCR, 0x08);
148 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
149}
150
151#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
152 106
153/* 107 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
154 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
155 * The access to uart register after MDR1 Access
156 * causes UART to corrupt data.
157 *
158 * Need a delay =
159 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
160 * give 10 times as much
161 */
162static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
163 u8 fcr_val)
164{
165 u8 timeout = 255;
166
167 serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
168 udelay(2);
169 serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
170 UART_FCR_CLEAR_RCVR);
171 /*
172 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
173 * TX_FIFO_E bit is 1.
174 */
175 while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
176 (UART_LSR_THRE | UART_LSR_DR))) {
177 timeout--;
178 if (!timeout) {
179 /* Should *never* happen. we warn and carry on */
180 dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
181 serial_read_reg(uart, UART_LSR));
182 break;
183 }
184 udelay(1);
185 }
186} 108}
187 109
188static void omap_uart_save_context(struct omap_uart_state *uart) 110static void omap_uart_set_forceidle(struct platform_device *pdev)
189{ 111{
190 u16 lcr = 0; 112 struct omap_device *od = to_omap_device(pdev);
191 113
192 if (!enable_off_mode) 114 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
193 return;
194
195 lcr = serial_read_reg(uart, UART_LCR);
196 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
197 uart->dll = serial_read_reg(uart, UART_DLL);
198 uart->dlh = serial_read_reg(uart, UART_DLM);
199 serial_write_reg(uart, UART_LCR, lcr);
200 uart->ier = serial_read_reg(uart, UART_IER);
201 uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
202 uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
203 uart->wer = serial_read_reg(uart, UART_OMAP_WER);
204 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
205 uart->mcr = serial_read_reg(uart, UART_MCR);
206 serial_write_reg(uart, UART_LCR, lcr);
207
208 uart->context_valid = 1;
209} 115}
210 116
211static void omap_uart_restore_context(struct omap_uart_state *uart)
212{
213 u16 efr = 0;
214
215 if (!enable_off_mode)
216 return;
217
218 if (!uart->context_valid)
219 return;
220
221 uart->context_valid = 0;
222
223 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
224 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
225 else
226 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
227
228 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
229 efr = serial_read_reg(uart, UART_EFR);
230 serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
231 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
232 serial_write_reg(uart, UART_IER, 0x0);
233 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
234 serial_write_reg(uart, UART_DLL, uart->dll);
235 serial_write_reg(uart, UART_DLM, uart->dlh);
236 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
237 serial_write_reg(uart, UART_IER, uart->ier);
238 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
239 serial_write_reg(uart, UART_MCR, uart->mcr);
240 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
241 serial_write_reg(uart, UART_EFR, efr);
242 serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
243 serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
244 serial_write_reg(uart, UART_OMAP_WER, uart->wer);
245 serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
246
247 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
248 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
249 else
250 /* UART 16x mode */
251 serial_write_reg(uart, UART_OMAP_MDR1,
252 UART_OMAP_MDR1_16X_MODE);
253}
254#else 117#else
255static inline void omap_uart_save_context(struct omap_uart_state *uart) {} 118static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
256static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} 119{}
257#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ 120static void omap_uart_set_noidle(struct platform_device *pdev) {}
258 121static void omap_uart_set_forceidle(struct platform_device *pdev) {}
259static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) 122#endif /* CONFIG_PM */
260{
261 if (uart->clocked)
262 return;
263
264 omap_device_enable(uart->pdev);
265 uart->clocked = 1;
266 omap_uart_restore_context(uart);
267}
268
269#ifdef CONFIG_PM
270
271static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
272{
273 if (!uart->clocked)
274 return;
275
276 omap_uart_save_context(uart);
277 uart->clocked = 0;
278 omap_device_idle(uart->pdev);
279}
280
281static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
282{
283 /* Set wake-enable bit */
284 if (uart->wk_en && uart->wk_mask) {
285 u32 v = __raw_readl(uart->wk_en);
286 v |= uart->wk_mask;
287 __raw_writel(v, uart->wk_en);
288 }
289
290 /* Ensure IOPAD wake-enables are set */
291 if (cpu_is_omap34xx() && uart->padconf) {
292 u16 v = omap_ctrl_readw(uart->padconf);
293 v |= OMAP3_PADCONF_WAKEUPENABLE0;
294 omap_ctrl_writew(v, uart->padconf);
295 }
296}
297
298static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
299{
300 /* Clear wake-enable bit */
301 if (uart->wk_en && uart->wk_mask) {
302 u32 v = __raw_readl(uart->wk_en);
303 v &= ~uart->wk_mask;
304 __raw_writel(v, uart->wk_en);
305 }
306
307 /* Ensure IOPAD wake-enables are cleared */
308 if (cpu_is_omap34xx() && uart->padconf) {
309 u16 v = omap_ctrl_readw(uart->padconf);
310 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
311 omap_ctrl_writew(v, uart->padconf);
312 }
313}
314
315static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
316 int enable)
317{
318 u8 idlemode;
319
320 if (enable) {
321 /**
322 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
323 * in Smartidle Mode When Configured for DMA Operations.
324 */
325 if (uart->dma_enabled)
326 idlemode = HWMOD_IDLEMODE_FORCE;
327 else
328 idlemode = HWMOD_IDLEMODE_SMART;
329 } else {
330 idlemode = HWMOD_IDLEMODE_NO;
331 }
332
333 omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
334}
335
336static void omap_uart_block_sleep(struct omap_uart_state *uart)
337{
338 omap_uart_enable_clocks(uart);
339
340 omap_uart_smart_idle_enable(uart, 0);
341 uart->can_sleep = 0;
342 if (uart->timeout)
343 mod_timer(&uart->timer, jiffies + uart->timeout);
344 else
345 del_timer(&uart->timer);
346}
347
348static void omap_uart_allow_sleep(struct omap_uart_state *uart)
349{
350 if (device_may_wakeup(&uart->pdev->dev))
351 omap_uart_enable_wakeup(uart);
352 else
353 omap_uart_disable_wakeup(uart);
354
355 if (!uart->clocked)
356 return;
357
358 omap_uart_smart_idle_enable(uart, 1);
359 uart->can_sleep = 1;
360 del_timer(&uart->timer);
361}
362
363static void omap_uart_idle_timer(unsigned long data)
364{
365 struct omap_uart_state *uart = (struct omap_uart_state *)data;
366
367 omap_uart_allow_sleep(uart);
368}
369
370void omap_uart_prepare_idle(int num)
371{
372 struct omap_uart_state *uart;
373
374 list_for_each_entry(uart, &uart_list, node) {
375 if (num == uart->num && uart->can_sleep) {
376 omap_uart_disable_clocks(uart);
377 return;
378 }
379 }
380}
381
382void omap_uart_resume_idle(int num)
383{
384 struct omap_uart_state *uart;
385
386 list_for_each_entry(uart, &uart_list, node) {
387 if (num == uart->num && uart->can_sleep) {
388 omap_uart_enable_clocks(uart);
389
390 /* Check for IO pad wakeup */
391 if (cpu_is_omap34xx() && uart->padconf) {
392 u16 p = omap_ctrl_readw(uart->padconf);
393
394 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
395 omap_uart_block_sleep(uart);
396 }
397
398 /* Check for normal UART wakeup */
399 if (__raw_readl(uart->wk_st) & uart->wk_mask)
400 omap_uart_block_sleep(uart);
401 return;
402 }
403 }
404}
405
406void omap_uart_prepare_suspend(void)
407{
408 struct omap_uart_state *uart;
409
410 list_for_each_entry(uart, &uart_list, node) {
411 omap_uart_allow_sleep(uart);
412 }
413}
414
415int omap_uart_can_sleep(void)
416{
417 struct omap_uart_state *uart;
418 int can_sleep = 1;
419
420 list_for_each_entry(uart, &uart_list, node) {
421 if (!uart->clocked)
422 continue;
423
424 if (!uart->can_sleep) {
425 can_sleep = 0;
426 continue;
427 }
428
429 /* This UART can now safely sleep. */
430 omap_uart_allow_sleep(uart);
431 }
432
433 return can_sleep;
434}
435 123
436/** 124#ifdef CONFIG_OMAP_MUX
437 * omap_uart_interrupt() 125static struct omap_device_pad default_uart1_pads[] __initdata = {
438 * 126 {
439 * This handler is used only to detect that *any* UART interrupt has 127 .name = "uart1_cts.uart1_cts",
440 * occurred. It does _nothing_ to handle the interrupt. Rather, 128 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
441 * any UART interrupt will trigger the inactivity timer so the 129 },
442 * UART will not idle or sleep for its timeout period. 130 {
443 * 131 .name = "uart1_rts.uart1_rts",
444 **/ 132 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
445/* static int first_interrupt; */ 133 },
446static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) 134 {
447{ 135 .name = "uart1_tx.uart1_tx",
448 struct omap_uart_state *uart = dev_id; 136 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
137 },
138 {
139 .name = "uart1_rx.uart1_rx",
140 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
141 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
142 .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
143 },
144};
449 145
450 omap_uart_block_sleep(uart); 146static struct omap_device_pad default_uart2_pads[] __initdata = {
147 {
148 .name = "uart2_cts.uart2_cts",
149 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
150 },
151 {
152 .name = "uart2_rts.uart2_rts",
153 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
154 },
155 {
156 .name = "uart2_tx.uart2_tx",
157 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
158 },
159 {
160 .name = "uart2_rx.uart2_rx",
161 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
162 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
163 .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
164 },
165};
451 166
452 return IRQ_NONE; 167static struct omap_device_pad default_uart3_pads[] __initdata = {
453} 168 {
169 .name = "uart3_cts_rctx.uart3_cts_rctx",
170 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
171 },
172 {
173 .name = "uart3_rts_sd.uart3_rts_sd",
174 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
175 },
176 {
177 .name = "uart3_tx_irtx.uart3_tx_irtx",
178 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
179 },
180 {
181 .name = "uart3_rx_irrx.uart3_rx_irrx",
182 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
183 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
184 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
185 },
186};
454 187
455static void omap_uart_idle_init(struct omap_uart_state *uart) 188static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
456{ 189 {
457 int ret; 190 .name = "gpmc_wait2.uart4_tx",
458 191 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
459 uart->can_sleep = 0; 192 },
460 uart->timeout = DEFAULT_TIMEOUT; 193 {
461 setup_timer(&uart->timer, omap_uart_idle_timer, 194 .name = "gpmc_wait3.uart4_rx",
462 (unsigned long) uart); 195 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
463 if (uart->timeout) 196 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
464 mod_timer(&uart->timer, jiffies + uart->timeout); 197 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
465 omap_uart_smart_idle_enable(uart, 0); 198 },
466 199};
467 if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
468 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
469 u32 wk_mask = 0;
470 u32 padconf = 0;
471
472 /* XXX These PRM accesses do not belong here */
473 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
474 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
475 switch (uart->num) {
476 case 0:
477 wk_mask = OMAP3430_ST_UART1_MASK;
478 padconf = 0x182;
479 break;
480 case 1:
481 wk_mask = OMAP3430_ST_UART2_MASK;
482 padconf = 0x17a;
483 break;
484 case 2:
485 wk_mask = OMAP3430_ST_UART3_MASK;
486 padconf = 0x19e;
487 break;
488 case 3:
489 wk_mask = OMAP3630_ST_UART4_MASK;
490 padconf = 0x0d2;
491 break;
492 }
493 uart->wk_mask = wk_mask;
494 uart->padconf = padconf;
495 } else if (cpu_is_omap24xx()) {
496 u32 wk_mask = 0;
497 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
498
499 switch (uart->num) {
500 case 0:
501 wk_mask = OMAP24XX_ST_UART1_MASK;
502 break;
503 case 1:
504 wk_mask = OMAP24XX_ST_UART2_MASK;
505 break;
506 case 2:
507 wk_en = OMAP24XX_PM_WKEN2;
508 wk_st = OMAP24XX_PM_WKST2;
509 wk_mask = OMAP24XX_ST_UART3_MASK;
510 break;
511 }
512 uart->wk_mask = wk_mask;
513 if (cpu_is_omap2430()) {
514 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
515 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
516 } else if (cpu_is_omap2420()) {
517 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
518 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
519 }
520 } else {
521 uart->wk_en = NULL;
522 uart->wk_st = NULL;
523 uart->wk_mask = 0;
524 uart->padconf = 0;
525 }
526 200
527 uart->irqflags |= IRQF_SHARED; 201static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
528 ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, 202 {
529 IRQF_SHARED, "serial idle", (void *)uart); 203 .name = "uart4_tx.uart4_tx",
530 WARN_ON(ret); 204 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
531} 205 },
206 {
207 .name = "uart4_rx.uart4_rx",
208 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
209 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
210 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
211 },
212};
532 213
533void omap_uart_enable_irqs(int enable) 214static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
534{ 215{
535 int ret; 216 switch (bdata->id) {
536 struct omap_uart_state *uart; 217 case 0:
537 218 bdata->pads = default_uart1_pads;
538 list_for_each_entry(uart, &uart_list, node) { 219 bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
539 if (enable) { 220 break;
540 pm_runtime_put_sync(&uart->pdev->dev); 221 case 1:
541 ret = request_threaded_irq(uart->irq, NULL, 222 bdata->pads = default_uart2_pads;
542 omap_uart_interrupt, 223 bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
543 IRQF_SHARED, 224 break;
544 "serial idle", 225 case 2:
545 (void *)uart); 226 bdata->pads = default_uart3_pads;
546 } else { 227 bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
547 pm_runtime_get_noresume(&uart->pdev->dev); 228 break;
548 free_irq(uart->irq, (void *)uart); 229 case 3:
230 if (cpu_is_omap44xx()) {
231 bdata->pads = default_omap4_uart4_pads;
232 bdata->pads_cnt =
233 ARRAY_SIZE(default_omap4_uart4_pads);
234 } else if (cpu_is_omap3630()) {
235 bdata->pads = default_omap36xx_uart4_pads;
236 bdata->pads_cnt =
237 ARRAY_SIZE(default_omap36xx_uart4_pads);
549 } 238 }
239 break;
240 default:
241 break;
550 } 242 }
551} 243}
552
553static ssize_t sleep_timeout_show(struct device *dev,
554 struct device_attribute *attr,
555 char *buf)
556{
557 struct platform_device *pdev = to_platform_device(dev);
558 struct omap_device *odev = to_omap_device(pdev);
559 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
560
561 return sprintf(buf, "%u\n", uart->timeout / HZ);
562}
563
564static ssize_t sleep_timeout_store(struct device *dev,
565 struct device_attribute *attr,
566 const char *buf, size_t n)
567{
568 struct platform_device *pdev = to_platform_device(dev);
569 struct omap_device *odev = to_omap_device(pdev);
570 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
571 unsigned int value;
572
573 if (sscanf(buf, "%u", &value) != 1) {
574 dev_err(dev, "sleep_timeout_store: Invalid value\n");
575 return -EINVAL;
576 }
577
578 uart->timeout = value * HZ;
579 if (uart->timeout)
580 mod_timer(&uart->timer, jiffies + uart->timeout);
581 else
582 /* A zero value means disable timeout feature */
583 omap_uart_block_sleep(uart);
584
585 return n;
586}
587
588static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
589 sleep_timeout_store);
590#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
591#else 244#else
592static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} 245static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
593static void omap_uart_block_sleep(struct omap_uart_state *uart) 246#endif
594{
595 /* Needed to enable UART clocks when built without CONFIG_PM */
596 omap_uart_enable_clocks(uart);
597}
598#define DEV_CREATE_FILE(dev, attr)
599#endif /* CONFIG_PM */
600
601#ifndef CONFIG_SERIAL_OMAP
602/*
603 * Override the default 8250 read handler: mem_serial_in()
604 * Empty RX fifo read causes an abort on omap3630 and omap4
605 * This function makes sure that an empty rx fifo is not read on these silicons
606 * (OMAP1/2/3430 are not affected)
607 */
608static unsigned int serial_in_override(struct uart_port *up, int offset)
609{
610 if (UART_RX == offset) {
611 unsigned int lsr;
612 lsr = __serial_read_reg(up, UART_LSR);
613 if (!(lsr & UART_LSR_DR))
614 return -EPERM;
615 }
616
617 return __serial_read_reg(up, offset);
618}
619 247
620static void serial_out_override(struct uart_port *up, int offset, int value) 248char *cmdline_find_option(char *str)
621{ 249{
622 unsigned int status, tmout = 10000; 250 extern char *saved_command_line;
623 251
624 status = __serial_read_reg(up, UART_LSR); 252 return strstr(saved_command_line, str);
625 while (!(status & UART_LSR_THRE)) {
626 /* Wait up to 10ms for the character(s) to be sent. */
627 if (--tmout == 0)
628 break;
629 udelay(1);
630 status = __serial_read_reg(up, UART_LSR);
631 }
632 __serial_write_reg(up, offset, value);
633} 253}
634#endif
635 254
636static int __init omap_serial_early_init(void) 255static int __init omap_serial_early_init(void)
637{ 256{
638 int i = 0;
639
640 do { 257 do {
641 char oh_name[MAX_UART_HWMOD_NAME_LEN]; 258 char oh_name[MAX_UART_HWMOD_NAME_LEN];
642 struct omap_hwmod *oh; 259 struct omap_hwmod *oh;
643 struct omap_uart_state *uart; 260 struct omap_uart_state *uart;
261 char uart_name[MAX_UART_HWMOD_NAME_LEN];
644 262
645 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, 263 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
646 "uart%d", i + 1); 264 "uart%d", num_uarts + 1);
647 oh = omap_hwmod_lookup(oh_name); 265 oh = omap_hwmod_lookup(oh_name);
648 if (!oh) 266 if (!oh)
649 break; 267 break;
@@ -653,21 +271,35 @@ static int __init omap_serial_early_init(void)
653 return -ENODEV; 271 return -ENODEV;
654 272
655 uart->oh = oh; 273 uart->oh = oh;
656 uart->num = i++; 274 uart->num = num_uarts++;
657 list_add_tail(&uart->node, &uart_list); 275 list_add_tail(&uart->node, &uart_list);
658 num_uarts++; 276 snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
659 277 "%s%d", OMAP_SERIAL_NAME, uart->num);
660 /* 278
661 * NOTE: omap_hwmod_setup*() has not yet been called, 279 if (cmdline_find_option(uart_name)) {
662 * so no hwmod functions will work yet. 280 console_uart_id = uart->num;
663 */ 281
664 282 if (console_loglevel >= 10) {
665 /* 283 uart_debug = true;
666 * During UART early init, device need to be probed 284 pr_info("%s used as console in debug mode"
667 * to determine SoC specific init before omap_device 285 " uart%d clocks will not be"
668 * is ready. Therefore, don't allow idle here 286 " gated", uart_name, uart->num);
669 */ 287 }
670 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; 288
289 if (cmdline_find_option("no_console_suspend"))
290 no_console_suspend = true;
291
292 /*
293 * omap-uart can be used for earlyprintk logs
294 * So if omap-uart is used as console then prevent
295 * uart reset and idle to get logs from omap-uart
296 * until uart console driver is available to take
297 * care for console messages.
298 * Idling or resetting omap-uart while printing logs
299 * early boot logs can stall the boot-up.
300 */
301 oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
302 }
671 } while (1); 303 } while (1);
672 304
673 return 0; 305 return 0;
@@ -677,6 +309,7 @@ core_initcall(omap_serial_early_init);
677/** 309/**
678 * omap_serial_init_port() - initialize single serial port 310 * omap_serial_init_port() - initialize single serial port
679 * @bdata: port specific board data pointer 311 * @bdata: port specific board data pointer
312 * @info: platform specific data pointer
680 * 313 *
681 * This function initialies serial driver for given port only. 314 * This function initialies serial driver for given port only.
682 * Platforms can call this function instead of omap_serial_init() 315 * Platforms can call this function instead of omap_serial_init()
@@ -685,7 +318,8 @@ core_initcall(omap_serial_early_init);
685 * Don't mix calls to omap_serial_init_port() and omap_serial_init(), 318 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
686 * use only one of the two. 319 * use only one of the two.
687 */ 320 */
688void __init omap_serial_init_port(struct omap_board_data *bdata) 321void __init omap_serial_init_port(struct omap_board_data *bdata,
322 struct omap_uart_port_info *info)
689{ 323{
690 struct omap_uart_state *uart; 324 struct omap_uart_state *uart;
691 struct omap_hwmod *oh; 325 struct omap_hwmod *oh;
@@ -693,15 +327,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
693 void *pdata = NULL; 327 void *pdata = NULL;
694 u32 pdata_size = 0; 328 u32 pdata_size = 0;
695 char *name; 329 char *name;
696#ifndef CONFIG_SERIAL_OMAP
697 struct plat_serial8250_port ports[2] = {
698 {},
699 {.flags = 0},
700 };
701 struct plat_serial8250_port *p = &ports[0];
702#else
703 struct omap_uart_port_info omap_up; 330 struct omap_uart_port_info omap_up;
704#endif
705 331
706 if (WARN_ON(!bdata)) 332 if (WARN_ON(!bdata))
707 return; 333 return;
@@ -713,66 +339,34 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
713 list_for_each_entry(uart, &uart_list, node) 339 list_for_each_entry(uart, &uart_list, node)
714 if (bdata->id == uart->num) 340 if (bdata->id == uart->num)
715 break; 341 break;
342 if (!info)
343 info = omap_serial_default_info;
716 344
717 oh = uart->oh; 345 oh = uart->oh;
718 uart->dma_enabled = 0;
719#ifndef CONFIG_SERIAL_OMAP
720 name = "serial8250";
721
722 /*
723 * !! 8250 driver does not use standard IORESOURCE* It
724 * has it's own custom pdata that can be taken from
725 * the hwmod resource data. But, this needs to be
726 * done after the build.
727 *
728 * ?? does it have to be done before the register ??
729 * YES, because platform_device_data_add() copies
730 * pdata, it does not use a pointer.
731 */
732 p->flags = UPF_BOOT_AUTOCONF;
733 p->iotype = UPIO_MEM;
734 p->regshift = 2;
735 p->uartclk = OMAP24XX_BASE_BAUD * 16;
736 p->irq = oh->mpu_irqs[0].irq;
737 p->mapbase = oh->slaves[0]->addr->pa_start;
738 p->membase = omap_hwmod_get_mpu_rt_va(oh);
739 p->irqflags = IRQF_SHARED;
740 p->private_data = uart;
741
742 /*
743 * omap44xx, ti816x: Never read empty UART fifo
744 * omap3xxx: Never read empty UART fifo on UARTs
745 * with IP rev >=0x52
746 */
747 uart->regshift = p->regshift;
748 uart->membase = p->membase;
749 if (cpu_is_omap44xx() || cpu_is_ti816x())
750 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
751 else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
752 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
753 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
754
755 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
756 p->serial_in = serial_in_override;
757 p->serial_out = serial_out_override;
758 }
759
760 pdata = &ports[0];
761 pdata_size = 2 * sizeof(struct plat_serial8250_port);
762#else
763
764 name = DRIVER_NAME; 346 name = DRIVER_NAME;
765 347
766 omap_up.dma_enabled = uart->dma_enabled; 348 omap_up.dma_enabled = info->dma_enabled;
767 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; 349 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
768 omap_up.mapbase = oh->slaves[0]->addr->pa_start; 350 omap_up.flags = UPF_BOOT_AUTOCONF;
769 omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); 351 omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
770 omap_up.irqflags = IRQF_SHARED; 352 omap_up.set_forceidle = omap_uart_set_forceidle;
771 omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 353 omap_up.set_noidle = omap_uart_set_noidle;
354 omap_up.enable_wakeup = omap_uart_enable_wakeup;
355 omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
356 omap_up.dma_rx_timeout = info->dma_rx_timeout;
357 omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
358 omap_up.autosuspend_timeout = info->autosuspend_timeout;
359
360 /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
361 if (!cpu_is_omap2420() && !cpu_is_ti816x())
362 omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
363
364 /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
365 if (cpu_is_omap34xx() || cpu_is_omap3630())
366 omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
772 367
773 pdata = &omap_up; 368 pdata = &omap_up;
774 pdata_size = sizeof(struct omap_uart_port_info); 369 pdata_size = sizeof(struct omap_uart_port_info);
775#endif
776 370
777 if (WARN_ON(!oh)) 371 if (WARN_ON(!oh))
778 return; 372 return;
@@ -782,64 +376,29 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
782 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", 376 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
783 name, oh->name); 377 name, oh->name);
784 378
785 omap_device_disable_idle_on_suspend(pdev); 379 if ((console_uart_id == bdata->id) && no_console_suspend)
380 omap_device_disable_idle_on_suspend(pdev);
381
786 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); 382 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
787 383
788 uart->irq = oh->mpu_irqs[0].irq;
789 uart->regshift = 2;
790 uart->mapbase = oh->slaves[0]->addr->pa_start;
791 uart->membase = omap_hwmod_get_mpu_rt_va(oh);
792 uart->pdev = pdev; 384 uart->pdev = pdev;
793 385
794 oh->dev_attr = uart; 386 oh->dev_attr = uart;
795 387
796 console_lock(); /* in case the earlycon is on the UART */ 388 if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
797 389 && !uart_debug)
798 /*
799 * Because of early UART probing, UART did not get idled
800 * on init. Now that omap_device is ready, ensure full idle
801 * before doing omap_device_enable().
802 */
803 omap_hwmod_idle(uart->oh);
804
805 omap_device_enable(uart->pdev);
806 omap_uart_idle_init(uart);
807 omap_uart_reset(uart);
808 omap_hwmod_enable_wakeup(uart->oh);
809 omap_device_idle(uart->pdev);
810
811 /*
812 * Need to block sleep long enough for interrupt driven
813 * driver to start. Console driver is in polling mode
814 * so device needs to be kept enabled while polling driver
815 * is in use.
816 */
817 if (uart->timeout)
818 uart->timeout = (30 * HZ);
819 omap_uart_block_sleep(uart);
820 uart->timeout = DEFAULT_TIMEOUT;
821
822 console_unlock();
823
824 if ((cpu_is_omap34xx() && uart->padconf) ||
825 (uart->wk_en && uart->wk_mask)) {
826 device_init_wakeup(&pdev->dev, true); 390 device_init_wakeup(&pdev->dev, true);
827 DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
828 }
829
830 /* Enable the MDR1 errata for OMAP3 */
831 if (cpu_is_omap34xx() && !cpu_is_ti816x())
832 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
833} 391}
834 392
835/** 393/**
836 * omap_serial_init() - initialize all supported serial ports 394 * omap_serial_board_init() - initialize all supported serial ports
395 * @info: platform specific data pointer
837 * 396 *
838 * Initializes all available UARTs as serial ports. Platforms 397 * Initializes all available UARTs as serial ports. Platforms
839 * can call this function when they want to have default behaviour 398 * can call this function when they want to have default behaviour
840 * for serial ports (e.g initialize them all as serial ports). 399 * for serial ports (e.g initialize them all as serial ports).
841 */ 400 */
842void __init omap_serial_init(void) 401void __init omap_serial_board_init(struct omap_uart_port_info *info)
843{ 402{
844 struct omap_uart_state *uart; 403 struct omap_uart_state *uart;
845 struct omap_board_data bdata; 404 struct omap_board_data bdata;
@@ -849,7 +408,25 @@ void __init omap_serial_init(void)
849 bdata.flags = 0; 408 bdata.flags = 0;
850 bdata.pads = NULL; 409 bdata.pads = NULL;
851 bdata.pads_cnt = 0; 410 bdata.pads_cnt = 0;
852 omap_serial_init_port(&bdata);
853 411
412 if (cpu_is_omap44xx() || cpu_is_omap34xx())
413 omap_serial_fill_default_pads(&bdata);
414
415 if (!info)
416 omap_serial_init_port(&bdata, NULL);
417 else
418 omap_serial_init_port(&bdata, &info[uart->num]);
854 } 419 }
855} 420}
421
422/**
423 * omap_serial_init() - initialize all supported serial ports
424 *
425 * Initializes all available UARTs.
426 * Platforms can call this function when they want to have default behaviour
427 * for serial ports (e.g initialize them all as serial ports).
428 */
429void __init omap_serial_init(void)
430{
431 omap_serial_board_init(NULL);
432}
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