diff options
Diffstat (limited to 'arch/arm/mach-omap2/serial.c')
| -rw-r--r-- | arch/arm/mach-omap2/serial.c | 197 |
1 files changed, 134 insertions, 63 deletions
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index b094c15bfe47..a7421a50410b 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
| @@ -54,6 +54,7 @@ struct omap_uart_state { | |||
| 54 | 54 | ||
| 55 | struct plat_serial8250_port *p; | 55 | struct plat_serial8250_port *p; |
| 56 | struct list_head node; | 56 | struct list_head node; |
| 57 | struct platform_device pdev; | ||
| 57 | 58 | ||
| 58 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | 59 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
| 59 | int context_valid; | 60 | int context_valid; |
| @@ -68,10 +69,9 @@ struct omap_uart_state { | |||
| 68 | #endif | 69 | #endif |
| 69 | }; | 70 | }; |
| 70 | 71 | ||
| 71 | static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS]; | ||
| 72 | static LIST_HEAD(uart_list); | 72 | static LIST_HEAD(uart_list); |
| 73 | 73 | ||
| 74 | static struct plat_serial8250_port serial_platform_data[] = { | 74 | static struct plat_serial8250_port serial_platform_data0[] = { |
| 75 | { | 75 | { |
| 76 | .membase = IO_ADDRESS(OMAP_UART1_BASE), | 76 | .membase = IO_ADDRESS(OMAP_UART1_BASE), |
| 77 | .mapbase = OMAP_UART1_BASE, | 77 | .mapbase = OMAP_UART1_BASE, |
| @@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
| 81 | .regshift = 2, | 81 | .regshift = 2, |
| 82 | .uartclk = OMAP24XX_BASE_BAUD * 16, | 82 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
| 83 | }, { | 83 | }, { |
| 84 | .flags = 0 | ||
| 85 | } | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct plat_serial8250_port serial_platform_data1[] = { | ||
| 89 | { | ||
| 84 | .membase = IO_ADDRESS(OMAP_UART2_BASE), | 90 | .membase = IO_ADDRESS(OMAP_UART2_BASE), |
| 85 | .mapbase = OMAP_UART2_BASE, | 91 | .mapbase = OMAP_UART2_BASE, |
| 86 | .irq = 73, | 92 | .irq = 73, |
| @@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
| 89 | .regshift = 2, | 95 | .regshift = 2, |
| 90 | .uartclk = OMAP24XX_BASE_BAUD * 16, | 96 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
| 91 | }, { | 97 | }, { |
| 98 | .flags = 0 | ||
| 99 | } | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct plat_serial8250_port serial_platform_data2[] = { | ||
| 103 | { | ||
| 92 | .membase = IO_ADDRESS(OMAP_UART3_BASE), | 104 | .membase = IO_ADDRESS(OMAP_UART3_BASE), |
| 93 | .mapbase = OMAP_UART3_BASE, | 105 | .mapbase = OMAP_UART3_BASE, |
| 94 | .irq = 74, | 106 | .irq = 74, |
| @@ -217,6 +229,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) | |||
| 217 | clk_disable(uart->fck); | 229 | clk_disable(uart->fck); |
| 218 | } | 230 | } |
| 219 | 231 | ||
| 232 | static void omap_uart_enable_wakeup(struct omap_uart_state *uart) | ||
| 233 | { | ||
| 234 | /* Set wake-enable bit */ | ||
| 235 | if (uart->wk_en && uart->wk_mask) { | ||
| 236 | u32 v = __raw_readl(uart->wk_en); | ||
| 237 | v |= uart->wk_mask; | ||
| 238 | __raw_writel(v, uart->wk_en); | ||
| 239 | } | ||
| 240 | |||
| 241 | /* Ensure IOPAD wake-enables are set */ | ||
| 242 | if (cpu_is_omap34xx() && uart->padconf) { | ||
| 243 | u16 v = omap_ctrl_readw(uart->padconf); | ||
| 244 | v |= OMAP3_PADCONF_WAKEUPENABLE0; | ||
| 245 | omap_ctrl_writew(v, uart->padconf); | ||
| 246 | } | ||
| 247 | } | ||
| 248 | |||
| 249 | static void omap_uart_disable_wakeup(struct omap_uart_state *uart) | ||
| 250 | { | ||
| 251 | /* Clear wake-enable bit */ | ||
| 252 | if (uart->wk_en && uart->wk_mask) { | ||
| 253 | u32 v = __raw_readl(uart->wk_en); | ||
| 254 | v &= ~uart->wk_mask; | ||
| 255 | __raw_writel(v, uart->wk_en); | ||
| 256 | } | ||
| 257 | |||
| 258 | /* Ensure IOPAD wake-enables are cleared */ | ||
| 259 | if (cpu_is_omap34xx() && uart->padconf) { | ||
| 260 | u16 v = omap_ctrl_readw(uart->padconf); | ||
| 261 | v &= ~OMAP3_PADCONF_WAKEUPENABLE0; | ||
| 262 | omap_ctrl_writew(v, uart->padconf); | ||
| 263 | } | ||
| 264 | } | ||
| 265 | |||
| 220 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, | 266 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, |
| 221 | int enable) | 267 | int enable) |
| 222 | { | 268 | { |
| @@ -246,6 +292,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart) | |||
| 246 | 292 | ||
| 247 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) | 293 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) |
| 248 | { | 294 | { |
| 295 | if (device_may_wakeup(&uart->pdev.dev)) | ||
| 296 | omap_uart_enable_wakeup(uart); | ||
| 297 | else | ||
| 298 | omap_uart_disable_wakeup(uart); | ||
| 299 | |||
| 249 | if (!uart->clocked) | 300 | if (!uart->clocked) |
| 250 | return; | 301 | return; |
| 251 | 302 | ||
| @@ -292,7 +343,6 @@ void omap_uart_resume_idle(int num) | |||
| 292 | /* Check for normal UART wakeup */ | 343 | /* Check for normal UART wakeup */ |
| 293 | if (__raw_readl(uart->wk_st) & uart->wk_mask) | 344 | if (__raw_readl(uart->wk_st) & uart->wk_mask) |
| 294 | omap_uart_block_sleep(uart); | 345 | omap_uart_block_sleep(uart); |
| 295 | |||
| 296 | return; | 346 | return; |
| 297 | } | 347 | } |
| 298 | } | 348 | } |
| @@ -346,16 +396,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) | |||
| 346 | return IRQ_NONE; | 396 | return IRQ_NONE; |
| 347 | } | 397 | } |
| 348 | 398 | ||
| 349 | static u32 sleep_timeout = DEFAULT_TIMEOUT; | ||
| 350 | |||
| 351 | static void omap_uart_idle_init(struct omap_uart_state *uart) | 399 | static void omap_uart_idle_init(struct omap_uart_state *uart) |
| 352 | { | 400 | { |
| 353 | u32 v; | ||
| 354 | struct plat_serial8250_port *p = uart->p; | 401 | struct plat_serial8250_port *p = uart->p; |
| 355 | int ret; | 402 | int ret; |
| 356 | 403 | ||
| 357 | uart->can_sleep = 0; | 404 | uart->can_sleep = 0; |
| 358 | uart->timeout = sleep_timeout; | 405 | uart->timeout = DEFAULT_TIMEOUT; |
| 359 | setup_timer(&uart->timer, omap_uart_idle_timer, | 406 | setup_timer(&uart->timer, omap_uart_idle_timer, |
| 360 | (unsigned long) uart); | 407 | (unsigned long) uart); |
| 361 | mod_timer(&uart->timer, jiffies + uart->timeout); | 408 | mod_timer(&uart->timer, jiffies + uart->timeout); |
| @@ -413,76 +460,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) | |||
| 413 | uart->padconf = 0; | 460 | uart->padconf = 0; |
| 414 | } | 461 | } |
| 415 | 462 | ||
| 416 | /* Set wake-enable bit */ | ||
| 417 | if (uart->wk_en && uart->wk_mask) { | ||
| 418 | v = __raw_readl(uart->wk_en); | ||
| 419 | v |= uart->wk_mask; | ||
| 420 | __raw_writel(v, uart->wk_en); | ||
| 421 | } | ||
| 422 | |||
| 423 | /* Ensure IOPAD wake-enables are set */ | ||
| 424 | if (cpu_is_omap34xx() && uart->padconf) { | ||
| 425 | u16 v; | ||
| 426 | |||
| 427 | v = omap_ctrl_readw(uart->padconf); | ||
| 428 | v |= OMAP3_PADCONF_WAKEUPENABLE0; | ||
| 429 | omap_ctrl_writew(v, uart->padconf); | ||
| 430 | } | ||
| 431 | |||
| 432 | p->flags |= UPF_SHARE_IRQ; | 463 | p->flags |= UPF_SHARE_IRQ; |
| 433 | ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, | 464 | ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, |
| 434 | "serial idle", (void *)uart); | 465 | "serial idle", (void *)uart); |
| 435 | WARN_ON(ret); | 466 | WARN_ON(ret); |
| 436 | } | 467 | } |
| 437 | 468 | ||
| 438 | static ssize_t sleep_timeout_show(struct kobject *kobj, | 469 | void omap_uart_enable_irqs(int enable) |
| 439 | struct kobj_attribute *attr, | 470 | { |
| 471 | int ret; | ||
| 472 | struct omap_uart_state *uart; | ||
| 473 | |||
| 474 | list_for_each_entry(uart, &uart_list, node) { | ||
| 475 | if (enable) | ||
| 476 | ret = request_irq(uart->p->irq, omap_uart_interrupt, | ||
| 477 | IRQF_SHARED, "serial idle", (void *)uart); | ||
| 478 | else | ||
| 479 | free_irq(uart->p->irq, (void *)uart); | ||
| 480 | } | ||
| 481 | } | ||
| 482 | |||
| 483 | static ssize_t sleep_timeout_show(struct device *dev, | ||
| 484 | struct device_attribute *attr, | ||
| 440 | char *buf) | 485 | char *buf) |
| 441 | { | 486 | { |
| 442 | return sprintf(buf, "%u\n", sleep_timeout / HZ); | 487 | struct platform_device *pdev = container_of(dev, |
| 488 | struct platform_device, dev); | ||
| 489 | struct omap_uart_state *uart = container_of(pdev, | ||
| 490 | struct omap_uart_state, pdev); | ||
| 491 | |||
| 492 | return sprintf(buf, "%u\n", uart->timeout / HZ); | ||
| 443 | } | 493 | } |
| 444 | 494 | ||
| 445 | static ssize_t sleep_timeout_store(struct kobject *kobj, | 495 | static ssize_t sleep_timeout_store(struct device *dev, |
| 446 | struct kobj_attribute *attr, | 496 | struct device_attribute *attr, |
| 447 | const char *buf, size_t n) | 497 | const char *buf, size_t n) |
| 448 | { | 498 | { |
| 449 | struct omap_uart_state *uart; | 499 | struct platform_device *pdev = container_of(dev, |
| 500 | struct platform_device, dev); | ||
| 501 | struct omap_uart_state *uart = container_of(pdev, | ||
| 502 | struct omap_uart_state, pdev); | ||
| 450 | unsigned int value; | 503 | unsigned int value; |
| 451 | 504 | ||
| 452 | if (sscanf(buf, "%u", &value) != 1) { | 505 | if (sscanf(buf, "%u", &value) != 1) { |
| 453 | printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); | 506 | printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); |
| 454 | return -EINVAL; | 507 | return -EINVAL; |
| 455 | } | 508 | } |
| 456 | sleep_timeout = value * HZ; | 509 | |
| 457 | list_for_each_entry(uart, &uart_list, node) { | 510 | uart->timeout = value * HZ; |
| 458 | uart->timeout = sleep_timeout; | 511 | if (uart->timeout) |
| 459 | if (uart->timeout) | 512 | mod_timer(&uart->timer, jiffies + uart->timeout); |
| 460 | mod_timer(&uart->timer, jiffies + uart->timeout); | 513 | else |
| 461 | else | 514 | /* A zero value means disable timeout feature */ |
| 462 | /* A zero value means disable timeout feature */ | 515 | omap_uart_block_sleep(uart); |
| 463 | omap_uart_block_sleep(uart); | 516 | |
| 464 | } | ||
| 465 | return n; | 517 | return n; |
| 466 | } | 518 | } |
| 467 | 519 | ||
| 468 | static struct kobj_attribute sleep_timeout_attr = | 520 | DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); |
| 469 | __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); | 521 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) |
| 470 | |||
| 471 | #else | 522 | #else |
| 472 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} | 523 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} |
| 524 | #define DEV_CREATE_FILE(dev, attr) | ||
| 473 | #endif /* CONFIG_PM */ | 525 | #endif /* CONFIG_PM */ |
| 474 | 526 | ||
| 475 | static struct platform_device serial_device = { | 527 | static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = { |
| 476 | .name = "serial8250", | 528 | { |
| 477 | .id = PLAT8250_DEV_PLATFORM, | 529 | .pdev = { |
| 478 | .dev = { | 530 | .name = "serial8250", |
| 479 | .platform_data = serial_platform_data, | 531 | .id = PLAT8250_DEV_PLATFORM, |
| 532 | .dev = { | ||
| 533 | .platform_data = serial_platform_data0, | ||
| 534 | }, | ||
| 535 | }, | ||
| 536 | }, { | ||
| 537 | .pdev = { | ||
| 538 | .name = "serial8250", | ||
| 539 | .id = PLAT8250_DEV_PLATFORM1, | ||
| 540 | .dev = { | ||
| 541 | .platform_data = serial_platform_data1, | ||
| 542 | }, | ||
| 543 | }, | ||
| 544 | }, { | ||
| 545 | .pdev = { | ||
| 546 | .name = "serial8250", | ||
| 547 | .id = PLAT8250_DEV_PLATFORM2, | ||
| 548 | .dev = { | ||
| 549 | .platform_data = serial_platform_data2, | ||
| 550 | }, | ||
| 551 | }, | ||
| 480 | }, | 552 | }, |
| 481 | }; | 553 | }; |
| 482 | 554 | ||
| 483 | void __init omap_serial_init(void) | 555 | void __init omap_serial_init(void) |
| 484 | { | 556 | { |
| 485 | int i, err; | 557 | int i; |
| 486 | const struct omap_uart_config *info; | 558 | const struct omap_uart_config *info; |
| 487 | char name[16]; | 559 | char name[16]; |
| 488 | 560 | ||
| @@ -496,14 +568,12 @@ void __init omap_serial_init(void) | |||
| 496 | 568 | ||
| 497 | if (info == NULL) | 569 | if (info == NULL) |
| 498 | return; | 570 | return; |
| 499 | if (cpu_is_omap44xx()) { | ||
| 500 | for (i = 0; i < OMAP_MAX_NR_PORTS; i++) | ||
| 501 | serial_platform_data[i].irq += 32; | ||
| 502 | } | ||
| 503 | 571 | ||
| 504 | for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { | 572 | for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { |
| 505 | struct plat_serial8250_port *p = serial_platform_data + i; | ||
| 506 | struct omap_uart_state *uart = &omap_uart[i]; | 573 | struct omap_uart_state *uart = &omap_uart[i]; |
| 574 | struct platform_device *pdev = &uart->pdev; | ||
| 575 | struct device *dev = &pdev->dev; | ||
| 576 | struct plat_serial8250_port *p = dev->platform_data; | ||
| 507 | 577 | ||
| 508 | if (!(info->enabled_uarts & (1 << i))) { | 578 | if (!(info->enabled_uarts & (1 << i))) { |
| 509 | p->membase = NULL; | 579 | p->membase = NULL; |
| @@ -531,20 +601,21 @@ void __init omap_serial_init(void) | |||
| 531 | uart->num = i; | 601 | uart->num = i; |
| 532 | p->private_data = uart; | 602 | p->private_data = uart; |
| 533 | uart->p = p; | 603 | uart->p = p; |
| 534 | list_add(&uart->node, &uart_list); | 604 | list_add_tail(&uart->node, &uart_list); |
| 605 | |||
| 606 | if (cpu_is_omap44xx()) | ||
| 607 | p->irq += 32; | ||
| 535 | 608 | ||
| 536 | omap_uart_enable_clocks(uart); | 609 | omap_uart_enable_clocks(uart); |
| 537 | omap_uart_reset(uart); | 610 | omap_uart_reset(uart); |
| 538 | omap_uart_idle_init(uart); | 611 | omap_uart_idle_init(uart); |
| 539 | } | ||
| 540 | |||
| 541 | err = platform_device_register(&serial_device); | ||
| 542 | |||
| 543 | #ifdef CONFIG_PM | ||
| 544 | if (!err) | ||
| 545 | err = sysfs_create_file(&serial_device.dev.kobj, | ||
| 546 | &sleep_timeout_attr.attr); | ||
| 547 | #endif | ||
| 548 | 612 | ||
| 613 | if (WARN_ON(platform_device_register(pdev))) | ||
| 614 | continue; | ||
| 615 | if ((cpu_is_omap34xx() && uart->padconf) || | ||
| 616 | (uart->wk_en && uart->wk_mask)) { | ||
| 617 | device_init_wakeup(dev, true); | ||
| 618 | DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); | ||
| 619 | } | ||
| 620 | } | ||
| 549 | } | 621 | } |
| 550 | |||
