diff options
Diffstat (limited to 'arch/arm/mach-omap2/prm44xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/prm44xx.h | 44 |
1 files changed, 11 insertions, 33 deletions
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 67a0d3feb3f6..7dfa379b625d 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #define OMAP4430_PRM_BASE 0x4a306000 | 31 | #define OMAP4430_PRM_BASE 0x4a306000 |
| 32 | 32 | ||
| 33 | #define OMAP44XX_PRM_REGADDR(inst, reg) \ | 33 | #define OMAP44XX_PRM_REGADDR(inst, reg) \ |
| 34 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) | 34 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) |
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | /* PRM instances */ | 37 | /* PRM instances */ |
| @@ -46,30 +46,18 @@ | |||
| 46 | #define OMAP4430_PRM_CAM_INST 0x1000 | 46 | #define OMAP4430_PRM_CAM_INST 0x1000 |
| 47 | #define OMAP4430_PRM_DSS_INST 0x1100 | 47 | #define OMAP4430_PRM_DSS_INST 0x1100 |
| 48 | #define OMAP4430_PRM_GFX_INST 0x1200 | 48 | #define OMAP4430_PRM_GFX_INST 0x1200 |
| 49 | #define OMAP4430_PRM_L3INIT_INST 0x1300 | 49 | #define OMAP4430_PRM_L3INIT_INST 0x1300 |
| 50 | #define OMAP4430_PRM_L4PER_INST 0x1400 | 50 | #define OMAP4430_PRM_L4PER_INST 0x1400 |
| 51 | #define OMAP4430_PRM_CEFUSE_INST 0x1600 | 51 | #define OMAP4430_PRM_CEFUSE_INST 0x1600 |
| 52 | #define OMAP4430_PRM_WKUP_INST 0x1700 | 52 | #define OMAP4430_PRM_WKUP_INST 0x1700 |
| 53 | #define OMAP4430_PRM_WKUP_CM_INST 0x1800 | 53 | #define OMAP4430_PRM_WKUP_CM_INST 0x1800 |
| 54 | #define OMAP4430_PRM_EMU_INST 0x1900 | 54 | #define OMAP4430_PRM_EMU_INST 0x1900 |
| 55 | #define OMAP4430_PRM_EMU_CM_INST 0x1a00 | 55 | #define OMAP4430_PRM_EMU_CM_INST 0x1a00 |
| 56 | #define OMAP4430_PRM_DEVICE_INST 0x1b00 | 56 | #define OMAP4430_PRM_DEVICE_INST 0x1b00 |
| 57 | #define OMAP4430_PRM_INSTR_INST 0x1f00 | 57 | #define OMAP4430_PRM_INSTR_INST 0x1f00 |
| 58 | 58 | ||
| 59 | /* PRM clockdomain register offsets (from instance start) */ | 59 | /* PRM clockdomain register offsets (from instance start) */ |
| 60 | #define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000 | ||
| 61 | #define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000 | ||
| 62 | #define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000 | ||
| 63 | #define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000 | ||
| 64 | #define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000 | ||
| 65 | #define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000 | ||
| 66 | #define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000 | ||
| 67 | #define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000 | ||
| 68 | #define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000 | ||
| 69 | #define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000 | ||
| 70 | #define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000 | ||
| 71 | #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 | 60 | #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 |
| 72 | #define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000 | ||
| 73 | #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 | 61 | #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 |
| 74 | 62 | ||
| 75 | /* OMAP4 specific register offsets */ | 63 | /* OMAP4 specific register offsets */ |
| @@ -247,8 +235,8 @@ | |||
| 247 | #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) | 235 | #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) |
| 248 | #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 | 236 | #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 |
| 249 | #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) | 237 | #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) |
| 250 | #define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c | 238 | #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c |
| 251 | #define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) | 239 | #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) |
| 252 | #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 | 240 | #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 |
| 253 | #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) | 241 | #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) |
| 254 | #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 | 242 | #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 |
| @@ -713,8 +701,8 @@ | |||
| 713 | #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) | 701 | #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) |
| 714 | #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 | 702 | #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 |
| 715 | #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) | 703 | #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) |
| 716 | #define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8 | 704 | #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 |
| 717 | #define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) | 705 | #define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) |
| 718 | #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac | 706 | #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac |
| 719 | #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) | 707 | #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) |
| 720 | #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 | 708 | #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 |
| @@ -751,8 +739,8 @@ | |||
| 751 | #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) | 739 | #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) |
| 752 | #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 | 740 | #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 |
| 753 | #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) | 741 | #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) |
| 754 | #define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4 | 742 | #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 |
| 755 | #define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) | 743 | #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) |
| 756 | #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 | 744 | #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 |
| 757 | #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) | 745 | #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) |
| 758 | 746 | ||
| @@ -762,16 +750,6 @@ | |||
| 762 | extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); | 750 | extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); |
| 763 | extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); | 751 | extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); |
| 764 | extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); | 752 | extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); |
| 765 | extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); | ||
| 766 | extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx); | ||
| 767 | extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx); | ||
| 768 | extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); | ||
| 769 | |||
| 770 | extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); | ||
| 771 | extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); | ||
| 772 | extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); | ||
| 773 | |||
| 774 | extern void omap4_prm_global_warm_sw_reset(void); | ||
| 775 | 753 | ||
| 776 | # endif | 754 | # endif |
| 777 | 755 | ||
