1 files changed, 71 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 00165558fc4d..495a31a7e8a7 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -21,8 +21,11 @@
 #include <plat/cpu.h>
 #include <plat/prcm.h>
 
+#include "vp.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
+#include "prcm44xx.h"
+#include "prminst44xx.h"
 
 /* PRM low-level functions */
 
@@ -50,3 +53,71 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
 
         return v;
 }
+
+/* PRM VP */
+
+/*
+ * struct omap4_vp - OMAP4 VP register access description.
+ * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
+ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ */
+struct omap4_vp {
+        u32 irqstatus_mpu;
+        u32 tranxdone_status;
+};
+
+static struct omap4_vp omap4_vp[] = {
+        [OMAP4_VP_VDD_MPU_ID] = {
+                .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
+                .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
+        },
+        [OMAP4_VP_VDD_IVA_ID] = {
+                .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+                .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
+        },
+        [OMAP4_VP_VDD_CORE_ID] = {
+                .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+                .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
+        },
+};
+
+u32 omap4_prm_vp_check_txdone(u8 vp_id)
+{
+        struct omap4_vp *vp = &omap4_vp[vp_id];
+        u32 irqstatus;
+
+        irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                                                OMAP4430_PRM_OCP_SOCKET_INST,
+                                                vp->irqstatus_mpu);
+        return irqstatus & vp->tranxdone_status;
+}
+
+void omap4_prm_vp_clear_txdone(u8 vp_id)
+{
+        struct omap4_vp *vp = &omap4_vp[vp_id];
+
+        omap4_prminst_write_inst_reg(vp->tranxdone_status,
+                                     OMAP4430_PRM_PARTITION,
+                                     OMAP4430_PRM_OCP_SOCKET_INST,
+                                     vp->irqstatus_mpu);
+};
+
+u32 omap4_prm_vcvp_read(u8 offset)
+{
+        return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                                           OMAP4430_PRM_DEVICE_INST, offset);
+}
+
+void omap4_prm_vcvp_write(u32 val, u8 offset)
+{
+        omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
+                                     OMAP4430_PRM_DEVICE_INST, offset);
+}
+
+u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
+{
+        return omap4_prminst_rmw_inst_reg_bits(mask, bits,
+                                               OMAP4430_PRM_PARTITION,
+                                               OMAP4430_PRM_DEVICE_INST,
+                                               offset);
+}