diff options
Diffstat (limited to 'arch/arm/mach-omap2/prm44xx.c')
-rw-r--r-- | arch/arm/mach-omap2/prm44xx.c | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 0958d070d3db..cc170fb81ff7 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c | |||
@@ -32,6 +32,12 @@ | |||
32 | 32 | ||
33 | /* Static data */ | 33 | /* Static data */ |
34 | 34 | ||
35 | static void omap44xx_prm_read_pending_irqs(unsigned long *events); | ||
36 | static void omap44xx_prm_ocp_barrier(void); | ||
37 | static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask); | ||
38 | static void omap44xx_prm_restore_irqen(u32 *saved_mask); | ||
39 | static void omap44xx_prm_reconfigure_io_chain(void); | ||
40 | |||
35 | static const struct omap_prcm_irq omap4_prcm_irqs[] = { | 41 | static const struct omap_prcm_irq omap4_prcm_irqs[] = { |
36 | OMAP_PRCM_IRQ("io", 9, 1), | 42 | OMAP_PRCM_IRQ("io", 9, 1), |
37 | }; | 43 | }; |
@@ -80,19 +86,19 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { | |||
80 | /* PRM low-level functions */ | 86 | /* PRM low-level functions */ |
81 | 87 | ||
82 | /* Read a register in a CM/PRM instance in the PRM module */ | 88 | /* Read a register in a CM/PRM instance in the PRM module */ |
83 | u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) | 89 | static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) |
84 | { | 90 | { |
85 | return readl_relaxed(prm_base + inst + reg); | 91 | return readl_relaxed(prm_base + inst + reg); |
86 | } | 92 | } |
87 | 93 | ||
88 | /* Write into a register in a CM/PRM instance in the PRM module */ | 94 | /* Write into a register in a CM/PRM instance in the PRM module */ |
89 | void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) | 95 | static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) |
90 | { | 96 | { |
91 | writel_relaxed(val, prm_base + inst + reg); | 97 | writel_relaxed(val, prm_base + inst + reg); |
92 | } | 98 | } |
93 | 99 | ||
94 | /* Read-modify-write a register in a PRM module. Caller must lock */ | 100 | /* Read-modify-write a register in a PRM module. Caller must lock */ |
95 | u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) | 101 | static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) |
96 | { | 102 | { |
97 | u32 v; | 103 | u32 v; |
98 | 104 | ||
@@ -207,7 +213,7 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs) | |||
207 | * MPU IRQs, and store the result into the two u32s pointed to by @events. | 213 | * MPU IRQs, and store the result into the two u32s pointed to by @events. |
208 | * No return value. | 214 | * No return value. |
209 | */ | 215 | */ |
210 | void omap44xx_prm_read_pending_irqs(unsigned long *events) | 216 | static void omap44xx_prm_read_pending_irqs(unsigned long *events) |
211 | { | 217 | { |
212 | events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, | 218 | events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, |
213 | OMAP4_PRM_IRQSTATUS_MPU_OFFSET); | 219 | OMAP4_PRM_IRQSTATUS_MPU_OFFSET); |
@@ -224,7 +230,7 @@ void omap44xx_prm_read_pending_irqs(unsigned long *events) | |||
224 | * block, to avoid race conditions after acknowledging or clearing IRQ | 230 | * block, to avoid race conditions after acknowledging or clearing IRQ |
225 | * bits. No return value. | 231 | * bits. No return value. |
226 | */ | 232 | */ |
227 | void omap44xx_prm_ocp_barrier(void) | 233 | static void omap44xx_prm_ocp_barrier(void) |
228 | { | 234 | { |
229 | omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, | 235 | omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, |
230 | OMAP4_REVISION_PRM_OFFSET); | 236 | OMAP4_REVISION_PRM_OFFSET); |
@@ -241,7 +247,7 @@ void omap44xx_prm_ocp_barrier(void) | |||
241 | * interrupts reaches the PRM before returning; otherwise, spurious | 247 | * interrupts reaches the PRM before returning; otherwise, spurious |
242 | * interrupts might occur. No return value. | 248 | * interrupts might occur. No return value. |
243 | */ | 249 | */ |
244 | void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) | 250 | static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) |
245 | { | 251 | { |
246 | saved_mask[0] = | 252 | saved_mask[0] = |
247 | omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, | 253 | omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, |
@@ -270,7 +276,7 @@ void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) | |||
270 | * No OCP barrier should be needed here; any pending PRM interrupts will fire | 276 | * No OCP barrier should be needed here; any pending PRM interrupts will fire |
271 | * once the writes reach the PRM. No return value. | 277 | * once the writes reach the PRM. No return value. |
272 | */ | 278 | */ |
273 | void omap44xx_prm_restore_irqen(u32 *saved_mask) | 279 | static void omap44xx_prm_restore_irqen(u32 *saved_mask) |
274 | { | 280 | { |
275 | omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST, | 281 | omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST, |
276 | OMAP4_PRM_IRQENABLE_MPU_OFFSET); | 282 | OMAP4_PRM_IRQENABLE_MPU_OFFSET); |
@@ -287,7 +293,7 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask) | |||
287 | * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted. | 293 | * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted. |
288 | * No return value. XXX Are the final two steps necessary? | 294 | * No return value. XXX Are the final two steps necessary? |
289 | */ | 295 | */ |
290 | void omap44xx_prm_reconfigure_io_chain(void) | 296 | static void omap44xx_prm_reconfigure_io_chain(void) |
291 | { | 297 | { |
292 | int i = 0; | 298 | int i = 0; |
293 | s32 inst = omap4_prmst_get_prm_dev_inst(); | 299 | s32 inst = omap4_prmst_get_prm_dev_inst(); |
@@ -652,11 +658,10 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) | |||
652 | 658 | ||
653 | static int omap4_check_vcvp(void) | 659 | static int omap4_check_vcvp(void) |
654 | { | 660 | { |
655 | /* No VC/VP on dra7xx devices */ | 661 | if (prm_features & PRM_HAS_VOLTAGE) |
656 | if (soc_is_dra7xx()) | 662 | return 1; |
657 | return 0; | ||
658 | 663 | ||
659 | return 1; | 664 | return 0; |
660 | } | 665 | } |
661 | 666 | ||
662 | struct pwrdm_ops omap4_pwrdm_operations = { | 667 | struct pwrdm_ops omap4_pwrdm_operations = { |
@@ -689,6 +694,10 @@ static struct prm_ll_data omap44xx_prm_ll_data = { | |||
689 | .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old, | 694 | .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old, |
690 | .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old, | 695 | .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old, |
691 | .late_init = &omap44xx_prm_late_init, | 696 | .late_init = &omap44xx_prm_late_init, |
697 | .assert_hardreset = omap4_prminst_assert_hardreset, | ||
698 | .deassert_hardreset = omap4_prminst_deassert_hardreset, | ||
699 | .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted, | ||
700 | .reset_system = omap4_prminst_global_warm_sw_reset, | ||
692 | }; | 701 | }; |
693 | 702 | ||
694 | int __init omap44xx_prm_init(void) | 703 | int __init omap44xx_prm_init(void) |
@@ -696,6 +705,9 @@ int __init omap44xx_prm_init(void) | |||
696 | if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) | 705 | if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) |
697 | prm_features |= PRM_HAS_IO_WAKEUP; | 706 | prm_features |= PRM_HAS_IO_WAKEUP; |
698 | 707 | ||
708 | if (!soc_is_dra7xx()) | ||
709 | prm_features |= PRM_HAS_VOLTAGE; | ||
710 | |||
699 | return prm_register(&omap44xx_prm_ll_data); | 711 | return prm_register(&omap44xx_prm_ll_data); |
700 | } | 712 | } |
701 | 713 | ||