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-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.h277
1 files changed, 71 insertions, 206 deletions
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index c19d249b4816..3330b1bf789d 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP2/3 Power/Reset Management (PRM) register definitions 2 * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
3 * 3 *
4 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. 4 * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation 5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Paul Walmsley 6 * Paul Walmsley
7 * 7 *
@@ -19,160 +19,6 @@
19#include "prcm-common.h" 19#include "prcm-common.h"
20#include "prm.h" 20#include "prm.h"
21 21
22#define OMAP2420_PRM_REGADDR(module, reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
24#define OMAP2430_PRM_REGADDR(module, reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
26#define OMAP34XX_PRM_REGADDR(module, reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
28
29
30/*
31 * OMAP2-specific global PRM registers
32 * Use __raw_{read,write}l() with these registers.
33 *
34 * With a few exceptions, these are the register names beginning with
35 * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
36 * bits.)
37 *
38 */
39
40#define OMAP2_PRCM_REVISION_OFFSET 0x0000
41#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
42#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
43#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
44
45#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
46#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
47#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
48#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
49
50#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
51#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
52#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
53#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
54#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
55#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
56#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
57#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
58#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
59#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
60#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
61#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
62#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
63#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
64#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
65#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
66#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
67#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
68#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
69#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
70
71#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
72#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
73
74#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
75#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
76
77#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
78#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
79#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
80#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
81#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
82#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
83#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
84#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
85#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
86#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
87
88/*
89 * OMAP3-specific global PRM registers
90 * Use __raw_{read,write}l() with these registers.
91 *
92 * With a few exceptions, these are the register names beginning with
93 * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
94 * bits.)
95 */
96
97#define OMAP3_PRM_REVISION_OFFSET 0x0004
98#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
99#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
100#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
101
102#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
103#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
104#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
105#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
106
107
108#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
109#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
110#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
111#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
112#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
113#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
114#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
115#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
116#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
117#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
118#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
119#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
120#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
121#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
122#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
123#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
124#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
125#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
126#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
127#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
128#define OMAP3_PRM_RSTST_OFFSET 0x0058
129#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
130#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
131#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
132#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
133#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
134#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
135#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
136#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
137#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
138#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
139#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
140#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
141#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
142#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
143#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
144#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
145#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
146#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
147#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
148#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
149#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
150#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
151#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
152#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
153#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
154#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
155#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
156#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
157#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
158#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
159#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
160#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
161#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
162#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
163#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
164#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
165#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
166#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
167#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
168#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
169#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
170
171#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
172#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
173#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
174#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
175
176/* 22/*
177 * Module specific PRM register offsets from PRM_BASE + domain offset 23 * Module specific PRM register offsets from PRM_BASE + domain offset
178 * 24 *
@@ -200,66 +46,83 @@
200#define PM_EVGENONTIM 0x00d8 46#define PM_EVGENONTIM 0x00d8
201#define PM_EVGENOFFTIM 0x00dc 47#define PM_EVGENOFFTIM 0x00dc
202 48
203/* OMAP2xxx specific register offsets */
204#define OMAP24XX_PM_WKEN2 0x00a4
205#define OMAP24XX_PM_WKST2 0x00b4
206
207#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
208#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
209#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
210#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
211
212/* OMAP3 specific register offsets */
213#define OMAP3430ES2_PM_WKEN3 0x00f0
214#define OMAP3430ES2_PM_WKST3 0x00b8
215
216#define OMAP3430_PM_MPUGRPSEL 0x00a4
217#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
218#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
219 49
220#define OMAP3430_PM_IVAGRPSEL 0x00a8 50#ifndef __ASSEMBLER__
221#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
222#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
223
224#define OMAP3430_PM_PREPWSTST 0x00e8
225
226#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
227#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
228 51
52#include <linux/io.h>
53#include "powerdomain.h"
229 54
230#ifndef __ASSEMBLER__
231/* Power/reset management domain register get/set */ 55/* Power/reset management domain register get/set */
232extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx); 56static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
233extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx); 57{
234extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 58 return __raw_readl(prm_base + module + idx);
235extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); 59}
236extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); 60
237extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); 61static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
62{
63 __raw_writel(val, prm_base + module + idx);
64}
65
66/* Read-modify-write a register in a PRM module. Caller must lock */
67static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
68 s16 idx)
69{
70 u32 v;
71
72 v = omap2_prm_read_mod_reg(module, idx);
73 v &= ~mask;
74 v |= bits;
75 omap2_prm_write_mod_reg(v, module, idx);
76
77 return v;
78}
79
80/* Read a PRM register, AND it, and shift the result down to bit 0 */
81static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
82{
83 u32 v;
84
85 v = omap2_prm_read_mod_reg(domain, idx);
86 v &= mask;
87 v >>= __ffs(mask);
88
89 return v;
90}
91
92static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
93{
94 return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
95}
96
97static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
98{
99 return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
100}
238 101
239/* These omap2_ PRM functions apply to both OMAP2 and 3 */ 102/* These omap2_ PRM functions apply to both OMAP2 and 3 */
240extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); 103extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
241extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); 104extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
242extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift); 105extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
243 106
244/* OMAP3-specific VP functions */ 107extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
245u32 omap3_prm_vp_check_txdone(u8 vp_id); 108extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
246void omap3_prm_vp_clear_txdone(u8 vp_id); 109extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
247 110extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
248/* 111 u8 pwrst);
249 * OMAP3 access functions for voltage controller (VC) and 112extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
250 * voltage proccessor (VP) in the PRM. 113 u8 pwrst);
251 */ 114extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
252extern u32 omap3_prm_vcvp_read(u8 offset); 115extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
253extern void omap3_prm_vcvp_write(u32 val, u8 offset); 116extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
254extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 117extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
255 118
256extern void omap3xxx_prm_reconfigure_io_chain(void); 119extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
257 120 struct clockdomain *clkdm2);
258/* PRM interrupt-related functions */ 121extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
259extern void omap3xxx_prm_read_pending_irqs(unsigned long *events); 122 struct clockdomain *clkdm2);
260extern void omap3xxx_prm_ocp_barrier(void); 123extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
261extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask); 124 struct clockdomain *clkdm2);
262extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); 125extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
263 126
264#endif /* __ASSEMBLER */ 127#endif /* __ASSEMBLER */
265 128
@@ -348,7 +211,9 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
348 * 211 *
349 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 212 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
350 */ 213 */
214#define OMAP_GLOBALWARM_RST_SHIFT 1
351#define OMAP_GLOBALWARM_RST_MASK (1 << 1) 215#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
216#define OMAP_GLOBALCOLD_RST_SHIFT 0
352#define OMAP_GLOBALCOLD_RST_MASK (1 << 0) 217#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
353 218
354/* 219/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 16:23:24 -0500