diff options
Diffstat (limited to 'arch/arm/mach-omap2/prm-regbits-44xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-44xx.h | 1314 |
1 files changed, 715 insertions, 599 deletions
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 597be4a2b9ff..25b19b610177 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP44xx Power Management register bits | 2 | * OMAP44xx Power Management register bits |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009 Nokia Corporation | 5 | * Copyright (C) 2009-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) | 7 | * Paul Walmsley (paul@pwsan.com) |
| 8 | * Rajendra Nayak (rnayak@ti.com) | 8 | * Rajendra Nayak (rnayak@ti.com) |
| @@ -30,587 +30,611 @@ | |||
| 30 | * PRM_LDO_SRAM_MPU_SETUP | 30 | * PRM_LDO_SRAM_MPU_SETUP |
| 31 | */ | 31 | */ |
| 32 | #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 | 32 | #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 |
| 33 | #define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) | 33 | #define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) |
| 34 | 34 | ||
| 35 | /* | 35 | /* |
| 36 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 36 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 37 | * PRM_LDO_SRAM_MPU_SETUP | 37 | * PRM_LDO_SRAM_MPU_SETUP |
| 38 | */ | 38 | */ |
| 39 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 | 39 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 |
| 40 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) | 40 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) |
| 41 | 41 | ||
| 42 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 42 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 43 | #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 | 43 | #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 |
| 44 | #define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) | 44 | #define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) |
| 45 | 45 | ||
| 46 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 46 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 47 | #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 | 47 | #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 |
| 48 | #define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) | 48 | #define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) |
| 49 | 49 | ||
| 50 | /* Used by PRM_IRQENABLE_MPU_2 */ | 50 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 51 | #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 | 51 | #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 |
| 52 | #define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) | 52 | #define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) |
| 53 | 53 | ||
| 54 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 54 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 55 | #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 | 55 | #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 |
| 56 | #define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) | 56 | #define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) |
| 57 | 57 | ||
| 58 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 58 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 59 | #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 | 59 | #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 |
| 60 | #define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) | 60 | #define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) |
| 61 | 61 | ||
| 62 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 62 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 63 | #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 | 63 | #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 |
| 64 | #define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) | 64 | #define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) |
| 65 | 65 | ||
| 66 | /* Used by PM_ABE_PWRSTCTRL */ | 66 | /* Used by PM_ABE_PWRSTCTRL */ |
| 67 | #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 | 67 | #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 |
| 68 | #define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) | 68 | #define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) |
| 69 | 69 | ||
| 70 | /* Used by PM_ABE_PWRSTCTRL */ | 70 | /* Used by PM_ABE_PWRSTCTRL */ |
| 71 | #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 | 71 | #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 |
| 72 | #define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) | 72 | #define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) |
| 73 | 73 | ||
| 74 | /* Used by PM_ABE_PWRSTST */ | 74 | /* Used by PM_ABE_PWRSTST */ |
| 75 | #define OMAP4430_AESSMEM_STATEST_SHIFT 4 | 75 | #define OMAP4430_AESSMEM_STATEST_SHIFT 4 |
| 76 | #define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) | 76 | #define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) |
| 77 | 77 | ||
| 78 | /* | 78 | /* |
| 79 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 79 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 80 | * PRM_LDO_SRAM_MPU_SETUP | 80 | * PRM_LDO_SRAM_MPU_SETUP |
| 81 | */ | 81 | */ |
| 82 | #define OMAP4430_AIPOFF_SHIFT 8 | 82 | #define OMAP4430_AIPOFF_SHIFT 8 |
| 83 | #define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) | 83 | #define OMAP4430_AIPOFF_MASK (1 << 8) |
| 84 | 84 | ||
| 85 | /* Used by PRM_VOLTCTRL */ | 85 | /* Used by PRM_VOLTCTRL */ |
| 86 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 | 86 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 |
| 87 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) | 87 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) |
| 88 | 88 | ||
| 89 | /* Used by PRM_VOLTCTRL */ | 89 | /* Used by PRM_VOLTCTRL */ |
| 90 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 | 90 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 |
| 91 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) | 91 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) |
| 92 | 92 | ||
| 93 | /* Used by PRM_VOLTCTRL */ | 93 | /* Used by PRM_VOLTCTRL */ |
| 94 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 | 94 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 |
| 95 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) | 95 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) |
| 96 | |||
| 97 | /* Used by PRM_VC_ERRST */ | ||
| 98 | #define OMAP4430_BYPS_RA_ERR_SHIFT 25 | ||
| 99 | #define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) | ||
| 100 | |||
| 101 | /* Used by PRM_VC_ERRST */ | ||
| 102 | #define OMAP4430_BYPS_SA_ERR_SHIFT 24 | ||
| 103 | #define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) | ||
| 104 | |||
| 105 | /* Used by PRM_VC_ERRST */ | ||
| 106 | #define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 | ||
| 107 | #define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) | ||
| 108 | |||
| 109 | /* Used by PRM_RSTST */ | ||
| 110 | #define OMAP4430_C2C_RST_SHIFT 10 | ||
| 111 | #define OMAP4430_C2C_RST_MASK (1 << 10) | ||
| 96 | 112 | ||
| 97 | /* Used by PM_CAM_PWRSTCTRL */ | 113 | /* Used by PM_CAM_PWRSTCTRL */ |
| 98 | #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 | 114 | #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 |
| 99 | #define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) | 115 | #define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) |
| 100 | 116 | ||
| 101 | /* Used by PM_CAM_PWRSTST */ | 117 | /* Used by PM_CAM_PWRSTST */ |
| 102 | #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 | 118 | #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 |
| 103 | #define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) | 119 | #define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) |
| 104 | 120 | ||
| 105 | /* Used by PRM_CLKREQCTRL */ | 121 | /* Used by PRM_CLKREQCTRL */ |
| 106 | #define OMAP4430_CLKREQ_COND_SHIFT 0 | 122 | #define OMAP4430_CLKREQ_COND_SHIFT 0 |
| 107 | #define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) | 123 | #define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) |
| 108 | 124 | ||
| 109 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | 125 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ |
| 110 | #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 | 126 | #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 |
| 111 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) | 127 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) |
| 112 | 128 | ||
| 113 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | 129 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ |
| 114 | #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 | 130 | #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 |
| 115 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) | 131 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) |
| 116 | 132 | ||
| 117 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | 133 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ |
| 118 | #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 | 134 | #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 |
| 119 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) | 135 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) |
| 120 | 136 | ||
| 121 | /* Used by PRM_VC_CFG_CHANNEL */ | 137 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 122 | #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 | 138 | #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 |
| 123 | #define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) | 139 | #define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) |
| 124 | 140 | ||
| 125 | /* Used by PRM_VC_CFG_CHANNEL */ | 141 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 126 | #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 | 142 | #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 |
| 127 | #define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) | 143 | #define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) |
| 128 | 144 | ||
| 129 | /* Used by PRM_VC_CFG_CHANNEL */ | 145 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 130 | #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 | 146 | #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 |
| 131 | #define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) | 147 | #define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) |
| 132 | 148 | ||
| 133 | /* Used by PM_CORE_PWRSTCTRL */ | 149 | /* Used by PM_CORE_PWRSTCTRL */ |
| 134 | #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 | 150 | #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 |
| 135 | #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) | 151 | #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) |
| 136 | 152 | ||
| 137 | /* Used by PM_CORE_PWRSTCTRL */ | 153 | /* Used by PM_CORE_PWRSTCTRL */ |
| 138 | #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 | 154 | #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 |
| 139 | #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) | 155 | #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) |
| 140 | 156 | ||
| 141 | /* Used by PM_CORE_PWRSTST */ | 157 | /* Used by PM_CORE_PWRSTST */ |
| 142 | #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 | 158 | #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 |
| 143 | #define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) | 159 | #define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) |
| 144 | 160 | ||
| 145 | /* Used by PM_CORE_PWRSTCTRL */ | 161 | /* Used by PM_CORE_PWRSTCTRL */ |
| 146 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 | 162 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 |
| 147 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) | 163 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) |
| 148 | 164 | ||
| 149 | /* Used by PM_CORE_PWRSTCTRL */ | 165 | /* Used by PM_CORE_PWRSTCTRL */ |
| 150 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 | 166 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 |
| 151 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) | 167 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) |
| 152 | 168 | ||
| 153 | /* Used by PM_CORE_PWRSTST */ | 169 | /* Used by PM_CORE_PWRSTST */ |
| 154 | #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 | 170 | #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 |
| 155 | #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) | 171 | #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) |
| 172 | |||
| 173 | /* Used by REVISION_PRM */ | ||
| 174 | #define OMAP4430_CUSTOM_SHIFT 6 | ||
| 175 | #define OMAP4430_CUSTOM_MASK (0x3 << 6) | ||
| 156 | 176 | ||
| 157 | /* Used by PRM_VC_VAL_BYPASS */ | 177 | /* Used by PRM_VC_VAL_BYPASS */ |
| 158 | #define OMAP4430_DATA_SHIFT 16 | 178 | #define OMAP4430_DATA_SHIFT 16 |
| 159 | #define OMAP4430_DATA_MASK BITFIELD(16, 23) | 179 | #define OMAP4430_DATA_MASK (0xff << 16) |
| 160 | 180 | ||
| 161 | /* Used by PRM_DEVICE_OFF_CTRL */ | 181 | /* Used by PRM_DEVICE_OFF_CTRL */ |
| 162 | #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 | 182 | #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 |
| 163 | #define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) | 183 | #define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) |
| 164 | 184 | ||
| 165 | /* Used by PRM_VC_CFG_I2C_MODE */ | 185 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 166 | #define OMAP4430_DFILTEREN_SHIFT 6 | 186 | #define OMAP4430_DFILTEREN_SHIFT 6 |
| 167 | #define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) | 187 | #define OMAP4430_DFILTEREN_MASK (1 << 6) |
| 168 | 188 | ||
| 169 | /* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | 189 | /* |
| 190 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 191 | * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP | ||
| 192 | */ | ||
| 193 | #define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 | ||
| 194 | #define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) | ||
| 195 | |||
| 196 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | ||
| 170 | #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 | 197 | #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 |
| 171 | #define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) | 198 | #define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) |
| 172 | 199 | ||
| 173 | /* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | 200 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ |
| 174 | #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 | 201 | #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 |
| 175 | #define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) | 202 | #define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) |
| 176 | 203 | ||
| 177 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 204 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 178 | #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 | 205 | #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 |
| 179 | #define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) | 206 | #define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) |
| 180 | 207 | ||
| 181 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 208 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 182 | #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 | 209 | #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 |
| 183 | #define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) | 210 | #define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) |
| 184 | 211 | ||
| 185 | /* Used by PRM_IRQENABLE_MPU */ | 212 | /* Used by PRM_IRQENABLE_MPU */ |
| 186 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 | 213 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 |
| 187 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) | 214 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) |
| 188 | 215 | ||
| 189 | /* Used by PRM_IRQSTATUS_MPU */ | 216 | /* Used by PRM_IRQSTATUS_MPU */ |
| 190 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 | 217 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 |
| 191 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) | 218 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) |
| 192 | 219 | ||
| 193 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | 220 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ |
| 194 | #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 | 221 | #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 |
| 195 | #define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) | 222 | #define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) |
| 196 | 223 | ||
| 197 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | 224 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ |
| 198 | #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 | 225 | #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 |
| 199 | #define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) | 226 | #define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) |
| 200 | 227 | ||
| 201 | /* Used by PRM_IRQENABLE_MPU */ | 228 | /* Used by PRM_IRQENABLE_MPU */ |
| 202 | #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 | 229 | #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 |
| 203 | #define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) | 230 | #define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) |
| 204 | 231 | ||
| 205 | /* Used by PRM_IRQSTATUS_MPU */ | 232 | /* Used by PRM_IRQSTATUS_MPU */ |
| 206 | #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 | 233 | #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 |
| 207 | #define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) | 234 | #define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) |
| 208 | 235 | ||
| 209 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 236 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 210 | #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 | 237 | #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 |
| 211 | #define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) | 238 | #define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) |
| 212 | 239 | ||
| 213 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 240 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 214 | #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 | 241 | #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 |
| 215 | #define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) | 242 | #define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) |
| 216 | 243 | ||
| 217 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 244 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 218 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 | 245 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 |
| 219 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) | 246 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) |
| 220 | 247 | ||
| 221 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 248 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 222 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 | 249 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 |
| 223 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) | 250 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) |
| 224 | |||
| 225 | /* Used by PRM_IRQENABLE_MPU */ | ||
| 226 | #define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5 | ||
| 227 | #define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) | ||
| 228 | |||
| 229 | /* Used by PRM_IRQSTATUS_MPU */ | ||
| 230 | #define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5 | ||
| 231 | #define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) | ||
| 232 | 251 | ||
| 233 | /* Used by PM_DSS_PWRSTCTRL */ | 252 | /* Used by PM_DSS_PWRSTCTRL */ |
| 234 | #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 | 253 | #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 |
| 235 | #define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) | 254 | #define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) |
| 236 | 255 | ||
| 237 | /* Used by PM_DSS_PWRSTCTRL */ | 256 | /* Used by PM_DSS_PWRSTCTRL */ |
| 238 | #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 | 257 | #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 |
| 239 | #define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) | 258 | #define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) |
| 240 | 259 | ||
| 241 | /* Used by PM_DSS_PWRSTST */ | 260 | /* Used by PM_DSS_PWRSTST */ |
| 242 | #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 | 261 | #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 |
| 243 | #define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) | 262 | #define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) |
| 244 | 263 | ||
| 245 | /* Used by PM_CORE_PWRSTCTRL */ | 264 | /* Used by PM_CORE_PWRSTCTRL */ |
| 246 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 | 265 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 |
| 247 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) | 266 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) |
| 248 | 267 | ||
| 249 | /* Used by PM_CORE_PWRSTCTRL */ | 268 | /* Used by PM_CORE_PWRSTCTRL */ |
| 250 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 | 269 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 |
| 251 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) | 270 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) |
| 252 | 271 | ||
| 253 | /* Used by PM_CORE_PWRSTST */ | 272 | /* Used by PM_CORE_PWRSTST */ |
| 254 | #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 | 273 | #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 |
| 255 | #define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) | 274 | #define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) |
| 256 | 275 | ||
| 257 | /* Used by PM_CORE_PWRSTCTRL */ | 276 | /* Used by PM_CORE_PWRSTCTRL */ |
| 258 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 | 277 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 |
| 259 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) | 278 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) |
| 260 | 279 | ||
| 261 | /* Used by PM_CORE_PWRSTCTRL */ | 280 | /* Used by PM_CORE_PWRSTCTRL */ |
| 262 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 | 281 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 |
| 263 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) | 282 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) |
| 264 | 283 | ||
| 265 | /* Used by PM_CORE_PWRSTST */ | 284 | /* Used by PM_CORE_PWRSTST */ |
| 266 | #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 | 285 | #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 |
| 267 | #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) | 286 | #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) |
| 268 | 287 | ||
| 269 | /* Used by RM_MPU_RSTST */ | 288 | /* Used by RM_MPU_RSTST */ |
| 270 | #define OMAP4430_EMULATION_RST_SHIFT 0 | 289 | #define OMAP4430_EMULATION_RST_SHIFT 0 |
| 271 | #define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) | 290 | #define OMAP4430_EMULATION_RST_MASK (1 << 0) |
| 272 | 291 | ||
| 273 | /* Used by RM_DUCATI_RSTST */ | 292 | /* Used by RM_DUCATI_RSTST */ |
| 274 | #define OMAP4430_EMULATION_RST1ST_SHIFT 3 | 293 | #define OMAP4430_EMULATION_RST1ST_SHIFT 3 |
| 275 | #define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) | 294 | #define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) |
| 276 | 295 | ||
| 277 | /* Used by RM_DUCATI_RSTST */ | 296 | /* Used by RM_DUCATI_RSTST */ |
| 278 | #define OMAP4430_EMULATION_RST2ST_SHIFT 4 | 297 | #define OMAP4430_EMULATION_RST2ST_SHIFT 4 |
| 279 | #define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) | 298 | #define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) |
| 280 | 299 | ||
| 281 | /* Used by RM_IVAHD_RSTST */ | 300 | /* Used by RM_IVAHD_RSTST */ |
| 282 | #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 | 301 | #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 |
| 283 | #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) | 302 | #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) |
| 284 | 303 | ||
| 285 | /* Used by RM_IVAHD_RSTST */ | 304 | /* Used by RM_IVAHD_RSTST */ |
| 286 | #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 | 305 | #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 |
| 287 | #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) | 306 | #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) |
| 288 | 307 | ||
| 289 | /* Used by PM_EMU_PWRSTCTRL */ | 308 | /* Used by PM_EMU_PWRSTCTRL */ |
| 290 | #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 | 309 | #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 |
| 291 | #define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) | 310 | #define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) |
| 292 | 311 | ||
| 293 | /* Used by PM_EMU_PWRSTST */ | 312 | /* Used by PM_EMU_PWRSTST */ |
| 294 | #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 | 313 | #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 |
| 295 | #define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) | 314 | #define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) |
| 296 | |||
| 297 | /* | ||
| 298 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 299 | * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP | ||
| 300 | */ | ||
| 301 | #define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0 | ||
| 302 | #define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) | ||
| 303 | 315 | ||
| 304 | /* | 316 | /* |
| 305 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 317 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 306 | * PRM_LDO_SRAM_MPU_SETUP | 318 | * PRM_LDO_SRAM_MPU_SETUP |
| 307 | */ | 319 | */ |
| 308 | #define OMAP4430_ENFUNC1_SHIFT 3 | 320 | #define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 |
| 309 | #define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) | 321 | #define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) |
| 310 | 322 | ||
| 311 | /* | 323 | /* |
| 312 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 324 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 313 | * PRM_LDO_SRAM_MPU_SETUP | 325 | * PRM_LDO_SRAM_MPU_SETUP |
| 314 | */ | 326 | */ |
| 315 | #define OMAP4430_ENFUNC3_SHIFT 5 | 327 | #define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 |
| 316 | #define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) | 328 | #define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) |
| 317 | 329 | ||
| 318 | /* | 330 | /* |
| 319 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 331 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 320 | * PRM_LDO_SRAM_MPU_SETUP | 332 | * PRM_LDO_SRAM_MPU_SETUP |
| 321 | */ | 333 | */ |
| 322 | #define OMAP4430_ENFUNC4_SHIFT 6 | 334 | #define OMAP4430_ENFUNC4_SHIFT 6 |
| 323 | #define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) | 335 | #define OMAP4430_ENFUNC4_MASK (1 << 6) |
| 324 | 336 | ||
| 325 | /* | 337 | /* |
| 326 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 338 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
| 327 | * PRM_LDO_SRAM_MPU_SETUP | 339 | * PRM_LDO_SRAM_MPU_SETUP |
| 328 | */ | 340 | */ |
| 329 | #define OMAP4430_ENFUNC5_SHIFT 7 | 341 | #define OMAP4430_ENFUNC5_SHIFT 7 |
| 330 | #define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) | 342 | #define OMAP4430_ENFUNC5_MASK (1 << 7) |
| 331 | 343 | ||
| 332 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 344 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 333 | #define OMAP4430_ERRORGAIN_SHIFT 16 | 345 | #define OMAP4430_ERRORGAIN_SHIFT 16 |
| 334 | #define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) | 346 | #define OMAP4430_ERRORGAIN_MASK (0xff << 16) |
| 335 | 347 | ||
| 336 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 348 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 337 | #define OMAP4430_ERROROFFSET_SHIFT 24 | 349 | #define OMAP4430_ERROROFFSET_SHIFT 24 |
| 338 | #define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) | 350 | #define OMAP4430_ERROROFFSET_MASK (0xff << 24) |
| 339 | 351 | ||
| 340 | /* Used by PRM_RSTST */ | 352 | /* Used by PRM_RSTST */ |
| 341 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 | 353 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 |
| 342 | #define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) | 354 | #define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) |
| 343 | 355 | ||
| 344 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 356 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 345 | #define OMAP4430_FORCEUPDATE_SHIFT 1 | 357 | #define OMAP4430_FORCEUPDATE_SHIFT 1 |
| 346 | #define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) | 358 | #define OMAP4430_FORCEUPDATE_MASK (1 << 1) |
| 347 | 359 | ||
| 348 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | 360 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ |
| 349 | #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 | 361 | #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 |
| 350 | #define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) | 362 | #define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) |
| 351 | 363 | ||
| 352 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ | 364 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ |
| 353 | #define OMAP4430_FORCEWKUP_EN_SHIFT 10 | 365 | #define OMAP4430_FORCEWKUP_EN_SHIFT 10 |
| 354 | #define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) | 366 | #define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) |
| 355 | 367 | ||
| 356 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ | 368 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ |
| 357 | #define OMAP4430_FORCEWKUP_ST_SHIFT 10 | 369 | #define OMAP4430_FORCEWKUP_ST_SHIFT 10 |
| 358 | #define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) | 370 | #define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) |
| 371 | |||
| 372 | /* Used by REVISION_PRM */ | ||
| 373 | #define OMAP4430_FUNC_SHIFT 16 | ||
| 374 | #define OMAP4430_FUNC_MASK (0xfff << 16) | ||
| 359 | 375 | ||
| 360 | /* Used by PM_GFX_PWRSTCTRL */ | 376 | /* Used by PM_GFX_PWRSTCTRL */ |
| 361 | #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 | 377 | #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 |
| 362 | #define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) | 378 | #define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) |
| 363 | 379 | ||
| 364 | /* Used by PM_GFX_PWRSTST */ | 380 | /* Used by PM_GFX_PWRSTST */ |
| 365 | #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 | 381 | #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 |
| 366 | #define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) | 382 | #define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) |
| 367 | 383 | ||
| 368 | /* Used by PRM_RSTST */ | 384 | /* Used by PRM_RSTST */ |
| 369 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 | 385 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 |
| 370 | #define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) | 386 | #define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) |
| 371 | 387 | ||
| 372 | /* Used by PRM_RSTST */ | 388 | /* Used by PRM_RSTST */ |
| 373 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 | 389 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 |
| 374 | #define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) | 390 | #define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) |
| 375 | 391 | ||
| 376 | /* Used by PRM_IO_PMCTRL */ | 392 | /* Used by PRM_IO_PMCTRL */ |
| 377 | #define OMAP4430_GLOBAL_WUEN_SHIFT 16 | 393 | #define OMAP4430_GLOBAL_WUEN_SHIFT 16 |
| 378 | #define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) | 394 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) |
| 379 | 395 | ||
| 380 | /* Used by PRM_VC_CFG_I2C_MODE */ | 396 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 381 | #define OMAP4430_HSMCODE_SHIFT 0 | 397 | #define OMAP4430_HSMCODE_SHIFT 0 |
| 382 | #define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) | 398 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) |
| 383 | 399 | ||
| 384 | /* Used by PRM_VC_CFG_I2C_MODE */ | 400 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 385 | #define OMAP4430_HSMODEEN_SHIFT 3 | 401 | #define OMAP4430_HSMODEEN_SHIFT 3 |
| 386 | #define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) | 402 | #define OMAP4430_HSMODEEN_MASK (1 << 3) |
| 387 | 403 | ||
| 388 | /* Used by PRM_VC_CFG_I2C_CLK */ | 404 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 389 | #define OMAP4430_HSSCLH_SHIFT 16 | 405 | #define OMAP4430_HSSCLH_SHIFT 16 |
| 390 | #define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) | 406 | #define OMAP4430_HSSCLH_MASK (0xff << 16) |
| 391 | 407 | ||
| 392 | /* Used by PRM_VC_CFG_I2C_CLK */ | 408 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 393 | #define OMAP4430_HSSCLL_SHIFT 24 | 409 | #define OMAP4430_HSSCLL_SHIFT 24 |
| 394 | #define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) | 410 | #define OMAP4430_HSSCLL_MASK (0xff << 24) |
| 395 | 411 | ||
| 396 | /* Used by PM_IVAHD_PWRSTCTRL */ | 412 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 397 | #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 | 413 | #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 |
| 398 | #define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) | 414 | #define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) |
| 399 | 415 | ||
| 400 | /* Used by PM_IVAHD_PWRSTCTRL */ | 416 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 401 | #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 | 417 | #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 |
| 402 | #define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) | 418 | #define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) |
| 403 | 419 | ||
| 404 | /* Used by PM_IVAHD_PWRSTST */ | 420 | /* Used by PM_IVAHD_PWRSTST */ |
| 405 | #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 | 421 | #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 |
| 406 | #define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) | 422 | #define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) |
| 407 | 423 | ||
| 408 | /* Used by RM_MPU_RSTST */ | 424 | /* Used by RM_MPU_RSTST */ |
| 409 | #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 | 425 | #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 |
| 410 | #define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) | 426 | #define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) |
| 411 | 427 | ||
| 412 | /* Used by RM_DUCATI_RSTST */ | 428 | /* Used by RM_DUCATI_RSTST */ |
| 413 | #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 | 429 | #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 |
| 414 | #define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) | 430 | #define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) |
| 415 | 431 | ||
| 416 | /* Used by RM_DUCATI_RSTST */ | 432 | /* Used by RM_DUCATI_RSTST */ |
| 417 | #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 | 433 | #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 |
| 418 | #define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) | 434 | #define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) |
| 419 | 435 | ||
| 420 | /* Used by RM_IVAHD_RSTST */ | 436 | /* Used by RM_IVAHD_RSTST */ |
| 421 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 | 437 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 |
| 422 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) | 438 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) |
| 423 | 439 | ||
| 424 | /* Used by RM_IVAHD_RSTST */ | 440 | /* Used by RM_IVAHD_RSTST */ |
| 425 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 | 441 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 |
| 426 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) | 442 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) |
| 427 | 443 | ||
| 428 | /* Used by PRM_RSTST */ | 444 | /* Used by PRM_RSTST */ |
| 429 | #define OMAP4430_ICEPICK_RST_SHIFT 9 | 445 | #define OMAP4430_ICEPICK_RST_SHIFT 9 |
| 430 | #define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) | 446 | #define OMAP4430_ICEPICK_RST_MASK (1 << 9) |
| 431 | 447 | ||
| 432 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 448 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 433 | #define OMAP4430_INITVDD_SHIFT 2 | 449 | #define OMAP4430_INITVDD_SHIFT 2 |
| 434 | #define OMAP4430_INITVDD_MASK BITFIELD(2, 2) | 450 | #define OMAP4430_INITVDD_MASK (1 << 2) |
| 435 | 451 | ||
| 436 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 452 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 437 | #define OMAP4430_INITVOLTAGE_SHIFT 8 | 453 | #define OMAP4430_INITVOLTAGE_SHIFT 8 |
| 438 | #define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) | 454 | #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) |
| 439 | 455 | ||
| 440 | /* | 456 | /* |
| 441 | * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, | 457 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, |
| 442 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, | 458 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, |
| 443 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST | 459 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST |
| 444 | */ | 460 | */ |
| 445 | #define OMAP4430_INTRANSITION_SHIFT 20 | 461 | #define OMAP4430_INTRANSITION_SHIFT 20 |
| 446 | #define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) | 462 | #define OMAP4430_INTRANSITION_MASK (1 << 20) |
| 447 | 463 | ||
| 448 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 464 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 449 | #define OMAP4430_IO_EN_SHIFT 9 | 465 | #define OMAP4430_IO_EN_SHIFT 9 |
| 450 | #define OMAP4430_IO_EN_MASK BITFIELD(9, 9) | 466 | #define OMAP4430_IO_EN_MASK (1 << 9) |
| 451 | 467 | ||
| 452 | /* Used by PRM_IO_PMCTRL */ | 468 | /* Used by PRM_IO_PMCTRL */ |
| 453 | #define OMAP4430_IO_ON_STATUS_SHIFT 5 | 469 | #define OMAP4430_IO_ON_STATUS_SHIFT 5 |
| 454 | #define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) | 470 | #define OMAP4430_IO_ON_STATUS_MASK (1 << 5) |
| 455 | 471 | ||
| 456 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 472 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 457 | #define OMAP4430_IO_ST_SHIFT 9 | 473 | #define OMAP4430_IO_ST_SHIFT 9 |
| 458 | #define OMAP4430_IO_ST_MASK BITFIELD(9, 9) | 474 | #define OMAP4430_IO_ST_MASK (1 << 9) |
| 459 | 475 | ||
| 460 | /* Used by PRM_IO_PMCTRL */ | 476 | /* Used by PRM_IO_PMCTRL */ |
| 461 | #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 | 477 | #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 |
| 462 | #define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) | 478 | #define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) |
| 463 | 479 | ||
| 464 | /* Used by PRM_IO_PMCTRL */ | 480 | /* Used by PRM_IO_PMCTRL */ |
| 465 | #define OMAP4430_ISOCLK_STATUS_SHIFT 1 | 481 | #define OMAP4430_ISOCLK_STATUS_SHIFT 1 |
| 466 | #define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) | 482 | #define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) |
| 467 | 483 | ||
| 468 | /* Used by PRM_IO_PMCTRL */ | 484 | /* Used by PRM_IO_PMCTRL */ |
| 469 | #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 | 485 | #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 |
| 470 | #define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) | 486 | #define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) |
| 471 | 487 | ||
| 472 | /* Used by PRM_IO_COUNT */ | 488 | /* Used by PRM_IO_COUNT */ |
| 473 | #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 | 489 | #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 |
| 474 | #define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) | 490 | #define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) |
| 475 | 491 | ||
| 476 | /* Used by PM_L3INIT_PWRSTCTRL */ | 492 | /* Used by PM_L3INIT_PWRSTCTRL */ |
| 477 | #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 | 493 | #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 |
| 478 | #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) | 494 | #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) |
| 479 | 495 | ||
| 480 | /* Used by PM_L3INIT_PWRSTCTRL */ | 496 | /* Used by PM_L3INIT_PWRSTCTRL */ |
| 481 | #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 | 497 | #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 |
| 482 | #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) | 498 | #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) |
| 483 | 499 | ||
| 484 | /* Used by PM_L3INIT_PWRSTST */ | 500 | /* Used by PM_L3INIT_PWRSTST */ |
| 485 | #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 | 501 | #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 |
| 486 | #define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) | 502 | #define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) |
| 503 | |||
| 504 | /* | ||
| 505 | * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, | ||
| 506 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | ||
| 507 | */ | ||
| 508 | #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 | ||
| 509 | #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | ||
| 487 | 510 | ||
| 488 | /* | 511 | /* |
| 489 | * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, | 512 | * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, |
| 490 | * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, | 513 | * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, |
| 491 | * PM_IVAHD_PWRSTCTRL | 514 | * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL |
| 492 | */ | 515 | */ |
| 493 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 | 516 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 |
| 494 | #define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) | 517 | #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) |
| 495 | 518 | ||
| 496 | /* | 519 | /* |
| 497 | * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, | 520 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, |
| 498 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, | 521 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, |
| 499 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST | 522 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST |
| 500 | */ | 523 | */ |
| 501 | #define OMAP4430_LOGICSTATEST_SHIFT 2 | 524 | #define OMAP4430_LOGICSTATEST_SHIFT 2 |
| 502 | #define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) | 525 | #define OMAP4430_LOGICSTATEST_MASK (1 << 2) |
| 503 | 526 | ||
| 504 | /* | 527 | /* |
| 505 | * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, | 528 | * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, |
| 506 | * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, | ||
| 507 | * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, | ||
| 508 | * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT, | ||
| 509 | * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT, | ||
| 510 | * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, | ||
| 511 | * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT, | ||
| 512 | * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT, | ||
| 513 | * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT, | ||
| 514 | * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, | ||
| 515 | * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, | ||
| 516 | * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, | ||
| 517 | * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | ||
| 518 | * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, | ||
| 519 | * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, | ||
| 520 | * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, | 529 | * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, |
| 521 | * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, | 530 | * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, |
| 522 | * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, | 531 | * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, |
| 523 | * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT, | 532 | * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, |
| 524 | * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, | 533 | * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, |
| 525 | * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, | 534 | * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, |
| 526 | * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT, | 535 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, |
| 527 | * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT, | 536 | * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, |
| 528 | * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT, | 537 | * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, |
| 529 | * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, | 538 | * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, |
| 530 | * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, | 539 | * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, |
| 531 | * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, | 540 | * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, |
| 532 | * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, | 541 | * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, |
| 533 | * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, | 542 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, |
| 534 | * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, | 543 | * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, |
| 535 | * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, | 544 | * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, |
| 536 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT, | 545 | * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, |
| 537 | * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, | 546 | * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, |
| 538 | * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT | 547 | * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, |
| 548 | * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, | ||
| 549 | * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, | ||
| 550 | * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, | ||
| 551 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, | ||
| 552 | * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, | ||
| 553 | * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, | ||
| 554 | * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, | ||
| 555 | * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, | ||
| 556 | * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, | ||
| 557 | * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, | ||
| 558 | * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, | ||
| 559 | * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, | ||
| 560 | * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, | ||
| 561 | * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT | ||
| 539 | */ | 562 | */ |
| 540 | #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 | 563 | #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 |
| 541 | #define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) | 564 | #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) |
| 542 | 565 | ||
| 543 | /* | 566 | /* |
| 544 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, | 567 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, |
| 545 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, | 568 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, |
| 569 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, | ||
| 570 | * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, | ||
| 571 | * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, | ||
| 572 | * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, | ||
| 546 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, | 573 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, |
| 547 | * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, | 574 | * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, |
| 548 | * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, | 575 | * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, |
| 549 | * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, | 576 | * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, |
| 550 | * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT, | 577 | * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, |
| 551 | * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT, | 578 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, |
| 552 | * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT, | 579 | * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, |
| 553 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT, | 580 | * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, |
| 554 | * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, | 581 | * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, |
| 555 | * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT, | 582 | * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, |
| 556 | * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, | 583 | * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT |
| 557 | * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT, | ||
| 558 | * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, | ||
| 559 | * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT | ||
| 560 | */ | 584 | */ |
| 561 | #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 | 585 | #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 |
| 562 | #define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) | 586 | #define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) |
| 563 | 587 | ||
| 564 | /* Used by RM_ABE_AESS_CONTEXT */ | 588 | /* Used by RM_ABE_AESS_CONTEXT */ |
| 565 | #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 | 589 | #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 |
| 566 | #define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) | 590 | #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) |
| 567 | 591 | ||
| 568 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ | 592 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ |
| 569 | #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 | 593 | #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 |
| 570 | #define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) | 594 | #define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) |
| 571 | 595 | ||
| 572 | /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ | 596 | /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ |
| 573 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 | 597 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 |
| 574 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) | 598 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) |
| 575 | 599 | ||
| 576 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ | 600 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ |
| 577 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 | 601 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 |
| 578 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) | 602 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) |
| 579 | 603 | ||
| 580 | /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ | 604 | /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ |
| 581 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 | 605 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 |
| 582 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) | 606 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) |
| 583 | 607 | ||
| 584 | /* | 608 | /* |
| 585 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, | 609 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, |
| 586 | * RM_SDMA_SDMA_CONTEXT | 610 | * RM_SDMA_SDMA_CONTEXT |
| 587 | */ | 611 | */ |
| 588 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 | 612 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 |
| 589 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) | 613 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) |
| 590 | 614 | ||
| 591 | /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ | 615 | /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ |
| 592 | #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 | 616 | #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 |
| 593 | #define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) | 617 | #define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) |
| 594 | 618 | ||
| 595 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | 619 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ |
| 596 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 | 620 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 |
| 597 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) | 621 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) |
| 598 | 622 | ||
| 599 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | 623 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ |
| 600 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 | 624 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 |
| 601 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) | 625 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) |
| 602 | 626 | ||
| 603 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ | 627 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ |
| 604 | #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 | 628 | #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 |
| 605 | #define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) | 629 | #define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) |
| 606 | 630 | ||
| 607 | /* Used by RM_GFX_GFX_CONTEXT */ | 631 | /* Used by RM_GFX_GFX_CONTEXT */ |
| 608 | #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 | 632 | #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 |
| 609 | #define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) | 633 | #define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) |
| 610 | 634 | ||
| 611 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | 635 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ |
| 612 | #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 | 636 | #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 |
| 613 | #define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) | 637 | #define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) |
| 614 | 638 | ||
| 615 | /* | 639 | /* |
| 616 | * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, | 640 | * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, |
| @@ -620,19 +644,19 @@ | |||
| 620 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT | 644 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT |
| 621 | */ | 645 | */ |
| 622 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 | 646 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 |
| 623 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) | 647 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) |
| 624 | 648 | ||
| 625 | /* Used by RM_MPU_MPU_CONTEXT */ | 649 | /* Used by RM_MPU_MPU_CONTEXT */ |
| 626 | #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 | 650 | #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 |
| 627 | #define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) | 651 | #define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) |
| 628 | 652 | ||
| 629 | /* Used by RM_MPU_MPU_CONTEXT */ | 653 | /* Used by RM_MPU_MPU_CONTEXT */ |
| 630 | #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 | 654 | #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 |
| 631 | #define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) | 655 | #define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) |
| 632 | 656 | ||
| 633 | /* Used by RM_MPU_MPU_CONTEXT */ | 657 | /* Used by RM_MPU_MPU_CONTEXT */ |
| 634 | #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 | 658 | #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 |
| 635 | #define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) | 659 | #define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) |
| 636 | 660 | ||
| 637 | /* | 661 | /* |
| 638 | * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, | 662 | * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, |
| @@ -640,14 +664,14 @@ | |||
| 640 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT | 664 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT |
| 641 | */ | 665 | */ |
| 642 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 | 666 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 |
| 643 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) | 667 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) |
| 644 | 668 | ||
| 645 | /* | 669 | /* |
| 646 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, | 670 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, |
| 647 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT | 671 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT |
| 648 | */ | 672 | */ |
| 649 | #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 | 673 | #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 |
| 650 | #define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) | 674 | #define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) |
| 651 | 675 | ||
| 652 | /* | 676 | /* |
| 653 | * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, | 677 | * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, |
| @@ -655,245 +679,237 @@ | |||
| 655 | * RM_L4SEC_CRYPTODMA_CONTEXT | 679 | * RM_L4SEC_CRYPTODMA_CONTEXT |
| 656 | */ | 680 | */ |
| 657 | #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 | 681 | #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 |
| 658 | #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) | 682 | #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) |
| 659 | 683 | ||
| 660 | /* Used by RM_IVAHD_SL2_CONTEXT */ | 684 | /* Used by RM_IVAHD_SL2_CONTEXT */ |
| 661 | #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 | 685 | #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 |
| 662 | #define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) | 686 | #define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) |
| 663 | 687 | ||
| 664 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | 688 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ |
| 665 | #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 | 689 | #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 |
| 666 | #define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) | 690 | #define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) |
| 667 | 691 | ||
| 668 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | 692 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ |
| 669 | #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 | 693 | #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 |
| 670 | #define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) | 694 | #define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) |
| 671 | 695 | ||
| 672 | /* Used by RM_TESLA_TESLA_CONTEXT */ | 696 | /* Used by RM_TESLA_TESLA_CONTEXT */ |
| 673 | #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 | 697 | #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 |
| 674 | #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) | 698 | #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) |
| 675 | 699 | ||
| 676 | /* Used by RM_TESLA_TESLA_CONTEXT */ | 700 | /* Used by RM_TESLA_TESLA_CONTEXT */ |
| 677 | #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 | 701 | #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 |
| 678 | #define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) | 702 | #define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) |
| 679 | 703 | ||
| 680 | /* Used by RM_TESLA_TESLA_CONTEXT */ | 704 | /* Used by RM_TESLA_TESLA_CONTEXT */ |
| 681 | #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 | 705 | #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 |
| 682 | #define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) | 706 | #define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) |
| 683 | 707 | ||
| 684 | /* Used by RM_WKUP_SARRAM_CONTEXT */ | 708 | /* Used by RM_WKUP_SARRAM_CONTEXT */ |
| 685 | #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 | 709 | #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 |
| 686 | #define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) | 710 | #define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) |
| 687 | 711 | ||
| 688 | /* | 712 | /* |
| 689 | * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, | 713 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, |
| 690 | * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, | 714 | * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, |
| 691 | * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL | 715 | * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL |
| 692 | */ | 716 | */ |
| 693 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 | 717 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 |
| 694 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) | 718 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) |
| 695 | |||
| 696 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 697 | #define OMAP4430_MEMORYCHANGE_SHIFT 3 | ||
| 698 | #define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) | ||
| 699 | 719 | ||
| 700 | /* Used by PRM_MODEM_IF_CTRL */ | 720 | /* Used by PRM_MODEM_IF_CTRL */ |
| 701 | #define OMAP4430_MODEM_READY_SHIFT 1 | 721 | #define OMAP4430_MODEM_READY_SHIFT 1 |
| 702 | #define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) | 722 | #define OMAP4430_MODEM_READY_MASK (1 << 1) |
| 703 | 723 | ||
| 704 | /* Used by PRM_MODEM_IF_CTRL */ | 724 | /* Used by PRM_MODEM_IF_CTRL */ |
| 705 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 | 725 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 |
| 706 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) | 726 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) |
| 707 | 727 | ||
| 708 | /* Used by PRM_MODEM_IF_CTRL */ | 728 | /* Used by PRM_MODEM_IF_CTRL */ |
| 709 | #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 | 729 | #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 |
| 710 | #define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) | 730 | #define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) |
| 711 | 731 | ||
| 712 | /* Used by PRM_MODEM_IF_CTRL */ | 732 | /* Used by PRM_MODEM_IF_CTRL */ |
| 713 | #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 | 733 | #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 |
| 714 | #define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) | 734 | #define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) |
| 715 | 735 | ||
| 716 | /* Used by PM_MPU_PWRSTCTRL */ | 736 | /* Used by PM_MPU_PWRSTCTRL */ |
| 717 | #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 | 737 | #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 |
| 718 | #define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) | 738 | #define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) |
| 719 | 739 | ||
| 720 | /* Used by PM_MPU_PWRSTCTRL */ | 740 | /* Used by PM_MPU_PWRSTCTRL */ |
| 721 | #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 | 741 | #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 |
| 722 | #define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) | 742 | #define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) |
| 723 | 743 | ||
| 724 | /* Used by PM_MPU_PWRSTST */ | 744 | /* Used by PM_MPU_PWRSTST */ |
| 725 | #define OMAP4430_MPU_L1_STATEST_SHIFT 4 | 745 | #define OMAP4430_MPU_L1_STATEST_SHIFT 4 |
| 726 | #define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) | 746 | #define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) |
| 727 | 747 | ||
| 728 | /* Used by PM_MPU_PWRSTCTRL */ | 748 | /* Used by PM_MPU_PWRSTCTRL */ |
| 729 | #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 | 749 | #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 |
| 730 | #define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) | 750 | #define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) |
| 731 | 751 | ||
| 732 | /* Used by PM_MPU_PWRSTCTRL */ | 752 | /* Used by PM_MPU_PWRSTCTRL */ |
| 733 | #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 | 753 | #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 |
| 734 | #define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) | 754 | #define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) |
| 735 | 755 | ||
| 736 | /* Used by PM_MPU_PWRSTST */ | 756 | /* Used by PM_MPU_PWRSTST */ |
| 737 | #define OMAP4430_MPU_L2_STATEST_SHIFT 6 | 757 | #define OMAP4430_MPU_L2_STATEST_SHIFT 6 |
| 738 | #define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) | 758 | #define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) |
| 739 | 759 | ||
| 740 | /* Used by PM_MPU_PWRSTCTRL */ | 760 | /* Used by PM_MPU_PWRSTCTRL */ |
| 741 | #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 | 761 | #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 |
| 742 | #define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) | 762 | #define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) |
| 743 | 763 | ||
| 744 | /* Used by PM_MPU_PWRSTCTRL */ | 764 | /* Used by PM_MPU_PWRSTCTRL */ |
| 745 | #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 | 765 | #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 |
| 746 | #define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) | 766 | #define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) |
| 747 | 767 | ||
| 748 | /* Used by PM_MPU_PWRSTST */ | 768 | /* Used by PM_MPU_PWRSTST */ |
| 749 | #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 | 769 | #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 |
| 750 | #define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) | 770 | #define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) |
| 751 | 771 | ||
| 752 | /* Used by PRM_RSTST */ | 772 | /* Used by PRM_RSTST */ |
| 753 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 | 773 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 |
| 754 | #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) | 774 | #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) |
| 755 | 775 | ||
| 756 | /* Used by PRM_RSTST */ | 776 | /* Used by PRM_RSTST */ |
| 757 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 | 777 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 |
| 758 | #define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) | 778 | #define OMAP4430_MPU_WDT_RST_MASK (1 << 3) |
| 759 | 779 | ||
| 760 | /* Used by PM_L4PER_PWRSTCTRL */ | 780 | /* Used by PM_L4PER_PWRSTCTRL */ |
| 761 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 | 781 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 |
| 762 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) | 782 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) |
| 763 | 783 | ||
| 764 | /* Used by PM_L4PER_PWRSTCTRL */ | 784 | /* Used by PM_L4PER_PWRSTCTRL */ |
| 765 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 | 785 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 |
| 766 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) | 786 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) |
| 767 | 787 | ||
| 768 | /* Used by PM_L4PER_PWRSTST */ | 788 | /* Used by PM_L4PER_PWRSTST */ |
| 769 | #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 | 789 | #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 |
| 770 | #define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) | 790 | #define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) |
| 771 | 791 | ||
| 772 | /* Used by PM_CORE_PWRSTCTRL */ | 792 | /* Used by PM_CORE_PWRSTCTRL */ |
| 773 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 | 793 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 |
| 774 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) | 794 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) |
| 775 | 795 | ||
| 776 | /* Used by PM_CORE_PWRSTCTRL */ | 796 | /* Used by PM_CORE_PWRSTCTRL */ |
| 777 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 | 797 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 |
| 778 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) | 798 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) |
| 779 | 799 | ||
| 780 | /* Used by PM_CORE_PWRSTST */ | 800 | /* Used by PM_CORE_PWRSTST */ |
| 781 | #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 | 801 | #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 |
| 782 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) | 802 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) |
| 783 | 803 | ||
| 784 | /* | 804 | /* |
| 785 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | 805 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, |
| 786 | * PRM_VC_VAL_CMD_VDD_MPU_L | 806 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 787 | */ | 807 | */ |
| 788 | #define OMAP4430_OFF_SHIFT 0 | 808 | #define OMAP4430_OFF_SHIFT 0 |
| 789 | #define OMAP4430_OFF_MASK BITFIELD(0, 7) | 809 | #define OMAP4430_OFF_MASK (0xff << 0) |
| 790 | |||
| 791 | /* Used by PRM_LDO_BANDGAP_CTRL */ | ||
| 792 | #define OMAP4430_OFF_ENABLE_SHIFT 0 | ||
| 793 | #define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) | ||
| 794 | 810 | ||
| 795 | /* | 811 | /* |
| 796 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | 812 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, |
| 797 | * PRM_VC_VAL_CMD_VDD_MPU_L | 813 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 798 | */ | 814 | */ |
| 799 | #define OMAP4430_ON_SHIFT 24 | 815 | #define OMAP4430_ON_SHIFT 24 |
| 800 | #define OMAP4430_ON_MASK BITFIELD(24, 31) | 816 | #define OMAP4430_ON_MASK (0xff << 24) |
| 801 | 817 | ||
| 802 | /* | 818 | /* |
| 803 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | 819 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, |
| 804 | * PRM_VC_VAL_CMD_VDD_MPU_L | 820 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 805 | */ | 821 | */ |
| 806 | #define OMAP4430_ONLP_SHIFT 16 | 822 | #define OMAP4430_ONLP_SHIFT 16 |
| 807 | #define OMAP4430_ONLP_MASK BITFIELD(16, 23) | 823 | #define OMAP4430_ONLP_MASK (0xff << 16) |
| 808 | 824 | ||
| 809 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | 825 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ |
| 810 | #define OMAP4430_OPP_CHANGE_SHIFT 2 | 826 | #define OMAP4430_OPP_CHANGE_SHIFT 2 |
| 811 | #define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) | 827 | #define OMAP4430_OPP_CHANGE_MASK (1 << 2) |
| 812 | 828 | ||
| 813 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | 829 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ |
| 814 | #define OMAP4430_OPP_SEL_SHIFT 0 | 830 | #define OMAP4430_OPP_SEL_SHIFT 0 |
| 815 | #define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) | 831 | #define OMAP4430_OPP_SEL_MASK (0x3 << 0) |
| 816 | 832 | ||
| 817 | /* Used by PRM_SRAM_COUNT */ | 833 | /* Used by PRM_SRAM_COUNT */ |
| 818 | #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 | 834 | #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 |
| 819 | #define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) | 835 | #define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) |
| 820 | 836 | ||
| 821 | /* Used by PRM_PSCON_COUNT */ | 837 | /* Used by PRM_PSCON_COUNT */ |
| 822 | #define OMAP4430_PCHARGE_TIME_SHIFT 0 | 838 | #define OMAP4430_PCHARGE_TIME_SHIFT 0 |
| 823 | #define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) | 839 | #define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) |
| 824 | 840 | ||
| 825 | /* Used by PM_ABE_PWRSTCTRL */ | 841 | /* Used by PM_ABE_PWRSTCTRL */ |
| 826 | #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 | 842 | #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 |
| 827 | #define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) | 843 | #define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) |
| 828 | 844 | ||
| 829 | /* Used by PM_ABE_PWRSTCTRL */ | 845 | /* Used by PM_ABE_PWRSTCTRL */ |
| 830 | #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 | 846 | #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 |
| 831 | #define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) | 847 | #define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) |
| 832 | 848 | ||
| 833 | /* Used by PM_ABE_PWRSTST */ | 849 | /* Used by PM_ABE_PWRSTST */ |
| 834 | #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 | 850 | #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 |
| 835 | #define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) | 851 | #define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) |
| 836 | 852 | ||
| 837 | /* Used by PRM_PHASE1_CNDP */ | 853 | /* Used by PRM_PHASE1_CNDP */ |
| 838 | #define OMAP4430_PHASE1_CNDP_SHIFT 0 | 854 | #define OMAP4430_PHASE1_CNDP_SHIFT 0 |
| 839 | #define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) | 855 | #define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) |
| 840 | 856 | ||
| 841 | /* Used by PRM_PHASE2A_CNDP */ | 857 | /* Used by PRM_PHASE2A_CNDP */ |
| 842 | #define OMAP4430_PHASE2A_CNDP_SHIFT 0 | 858 | #define OMAP4430_PHASE2A_CNDP_SHIFT 0 |
| 843 | #define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) | 859 | #define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) |
| 844 | 860 | ||
| 845 | /* Used by PRM_PHASE2B_CNDP */ | 861 | /* Used by PRM_PHASE2B_CNDP */ |
| 846 | #define OMAP4430_PHASE2B_CNDP_SHIFT 0 | 862 | #define OMAP4430_PHASE2B_CNDP_SHIFT 0 |
| 847 | #define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) | 863 | #define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) |
| 848 | 864 | ||
| 849 | /* Used by PRM_PSCON_COUNT */ | 865 | /* Used by PRM_PSCON_COUNT */ |
| 850 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 | 866 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 |
| 851 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) | 867 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) |
| 852 | 868 | ||
| 853 | /* | 869 | /* |
| 854 | * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, | 870 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, |
| 855 | * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, | 871 | * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, |
| 856 | * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, | 872 | * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, |
| 857 | * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL | 873 | * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL |
| 858 | */ | 874 | */ |
| 859 | #define OMAP4430_POWERSTATE_SHIFT 0 | 875 | #define OMAP4430_POWERSTATE_SHIFT 0 |
| 860 | #define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) | 876 | #define OMAP4430_POWERSTATE_MASK (0x3 << 0) |
| 861 | 877 | ||
| 862 | /* | 878 | /* |
| 863 | * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, | 879 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, |
| 864 | * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, | 880 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, |
| 865 | * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST | 881 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST |
| 866 | */ | 882 | */ |
| 867 | #define OMAP4430_POWERSTATEST_SHIFT 0 | 883 | #define OMAP4430_POWERSTATEST_SHIFT 0 |
| 868 | #define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) | 884 | #define OMAP4430_POWERSTATEST_MASK (0x3 << 0) |
| 869 | 885 | ||
| 870 | /* Used by PRM_PWRREQCTRL */ | 886 | /* Used by PRM_PWRREQCTRL */ |
| 871 | #define OMAP4430_PWRREQ_COND_SHIFT 0 | 887 | #define OMAP4430_PWRREQ_COND_SHIFT 0 |
| 872 | #define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) | 888 | #define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) |
| 873 | 889 | ||
| 874 | /* Used by PRM_VC_CFG_CHANNEL */ | 890 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 875 | #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 | 891 | #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 |
| 876 | #define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) | 892 | #define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) |
| 877 | 893 | ||
| 878 | /* Used by PRM_VC_CFG_CHANNEL */ | 894 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 879 | #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 | 895 | #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 |
| 880 | #define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) | 896 | #define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) |
| 881 | 897 | ||
| 882 | /* Used by PRM_VC_CFG_CHANNEL */ | 898 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 883 | #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 | 899 | #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 |
| 884 | #define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) | 900 | #define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) |
| 885 | 901 | ||
| 886 | /* Used by PRM_VC_CFG_CHANNEL */ | 902 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 887 | #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 | 903 | #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 |
| 888 | #define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) | 904 | #define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) |
| 889 | 905 | ||
| 890 | /* Used by PRM_VC_CFG_CHANNEL */ | 906 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 891 | #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 | 907 | #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 |
| 892 | #define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) | 908 | #define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) |
| 893 | 909 | ||
| 894 | /* Used by PRM_VC_CFG_CHANNEL */ | 910 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 895 | #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 | 911 | #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 |
| 896 | #define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) | 912 | #define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) |
| 897 | 913 | ||
| 898 | /* | 914 | /* |
| 899 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | 915 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, |
| @@ -901,7 +917,7 @@ | |||
| 901 | * PRM_VOLTSETUP_MPU_RET_SLEEP | 917 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 902 | */ | 918 | */ |
| 903 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 | 919 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 |
| 904 | #define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) | 920 | #define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) |
| 905 | 921 | ||
| 906 | /* | 922 | /* |
| 907 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | 923 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, |
| @@ -909,7 +925,7 @@ | |||
| 909 | * PRM_VOLTSETUP_MPU_RET_SLEEP | 925 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 910 | */ | 926 | */ |
| 911 | #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 | 927 | #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 |
| 912 | #define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) | 928 | #define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) |
| 913 | 929 | ||
| 914 | /* | 930 | /* |
| 915 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | 931 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, |
| @@ -917,7 +933,7 @@ | |||
| 917 | * PRM_VOLTSETUP_MPU_RET_SLEEP | 933 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 918 | */ | 934 | */ |
| 919 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 | 935 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 |
| 920 | #define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) | 936 | #define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) |
| 921 | 937 | ||
| 922 | /* | 938 | /* |
| 923 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | 939 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, |
| @@ -925,1281 +941,1381 @@ | |||
| 925 | * PRM_VOLTSETUP_MPU_RET_SLEEP | 941 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 926 | */ | 942 | */ |
| 927 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 | 943 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 |
| 928 | #define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) | 944 | #define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) |
| 929 | 945 | ||
| 930 | /* Used by PRM_VC_CFG_CHANNEL */ | 946 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 931 | #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 | 947 | #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 |
| 932 | #define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) | 948 | #define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) |
| 933 | 949 | ||
| 934 | /* Used by PRM_VC_CFG_CHANNEL */ | 950 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 935 | #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 | 951 | #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 |
| 936 | #define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) | 952 | #define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) |
| 937 | 953 | ||
| 938 | /* Used by PRM_VC_CFG_CHANNEL */ | 954 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 939 | #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 | 955 | #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 |
| 940 | #define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) | 956 | #define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) |
| 941 | 957 | ||
| 942 | /* Used by PRM_VC_VAL_BYPASS */ | 958 | /* Used by PRM_VC_VAL_BYPASS */ |
| 943 | #define OMAP4430_REGADDR_SHIFT 8 | 959 | #define OMAP4430_REGADDR_SHIFT 8 |
| 944 | #define OMAP4430_REGADDR_MASK BITFIELD(8, 15) | 960 | #define OMAP4430_REGADDR_MASK (0xff << 8) |
| 945 | 961 | ||
| 946 | /* | 962 | /* |
| 947 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | 963 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, |
| 948 | * PRM_VC_VAL_CMD_VDD_MPU_L | 964 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 949 | */ | 965 | */ |
| 950 | #define OMAP4430_RET_SHIFT 8 | 966 | #define OMAP4430_RET_SHIFT 8 |
| 951 | #define OMAP4430_RET_MASK BITFIELD(8, 15) | 967 | #define OMAP4430_RET_MASK (0xff << 8) |
| 952 | 968 | ||
| 953 | /* Used by PM_L4PER_PWRSTCTRL */ | 969 | /* Used by PM_L4PER_PWRSTCTRL */ |
| 954 | #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 | 970 | #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 |
| 955 | #define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) | 971 | #define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) |
| 956 | 972 | ||
| 957 | /* Used by PM_L4PER_PWRSTCTRL */ | 973 | /* Used by PM_L4PER_PWRSTCTRL */ |
| 958 | #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 | 974 | #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 |
| 959 | #define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) | 975 | #define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) |
| 960 | 976 | ||
| 961 | /* Used by PM_L4PER_PWRSTST */ | 977 | /* Used by PM_L4PER_PWRSTST */ |
| 962 | #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 | 978 | #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 |
| 963 | #define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) | 979 | #define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) |
| 964 | 980 | ||
| 965 | /* | 981 | /* |
| 966 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | 982 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, |
| 967 | * PRM_LDO_SRAM_MPU_CTRL | 983 | * PRM_LDO_SRAM_MPU_CTRL |
| 968 | */ | 984 | */ |
| 969 | #define OMAP4430_RETMODE_ENABLE_SHIFT 0 | 985 | #define OMAP4430_RETMODE_ENABLE_SHIFT 0 |
| 970 | #define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) | 986 | #define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) |
| 971 | 987 | ||
| 972 | /* Used by REVISION_PRM */ | 988 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ |
| 973 | #define OMAP4430_REV_SHIFT 0 | ||
| 974 | #define OMAP4430_REV_MASK BITFIELD(0, 7) | ||
| 975 | |||
| 976 | /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ | ||
| 977 | #define OMAP4430_RST1_SHIFT 0 | 989 | #define OMAP4430_RST1_SHIFT 0 |
| 978 | #define OMAP4430_RST1_MASK BITFIELD(0, 0) | 990 | #define OMAP4430_RST1_MASK (1 << 0) |
| 979 | 991 | ||
| 980 | /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ | 992 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ |
| 981 | #define OMAP4430_RST1ST_SHIFT 0 | 993 | #define OMAP4430_RST1ST_SHIFT 0 |
| 982 | #define OMAP4430_RST1ST_MASK BITFIELD(0, 0) | 994 | #define OMAP4430_RST1ST_MASK (1 << 0) |
| 983 | 995 | ||
| 984 | /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ | 996 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ |
| 985 | #define OMAP4430_RST2_SHIFT 1 | 997 | #define OMAP4430_RST2_SHIFT 1 |
| 986 | #define OMAP4430_RST2_MASK BITFIELD(1, 1) | 998 | #define OMAP4430_RST2_MASK (1 << 1) |
| 987 | 999 | ||
| 988 | /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ | 1000 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ |
| 989 | #define OMAP4430_RST2ST_SHIFT 1 | 1001 | #define OMAP4430_RST2ST_SHIFT 1 |
| 990 | #define OMAP4430_RST2ST_MASK BITFIELD(1, 1) | 1002 | #define OMAP4430_RST2ST_MASK (1 << 1) |
| 991 | 1003 | ||
| 992 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ | 1004 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ |
| 993 | #define OMAP4430_RST3_SHIFT 2 | 1005 | #define OMAP4430_RST3_SHIFT 2 |
| 994 | #define OMAP4430_RST3_MASK BITFIELD(2, 2) | 1006 | #define OMAP4430_RST3_MASK (1 << 2) |
| 995 | 1007 | ||
| 996 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ | 1008 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ |
| 997 | #define OMAP4430_RST3ST_SHIFT 2 | 1009 | #define OMAP4430_RST3ST_SHIFT 2 |
| 998 | #define OMAP4430_RST3ST_MASK BITFIELD(2, 2) | 1010 | #define OMAP4430_RST3ST_MASK (1 << 2) |
| 999 | 1011 | ||
| 1000 | /* Used by PRM_RSTTIME */ | 1012 | /* Used by PRM_RSTTIME */ |
| 1001 | #define OMAP4430_RSTTIME1_SHIFT 0 | 1013 | #define OMAP4430_RSTTIME1_SHIFT 0 |
| 1002 | #define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) | 1014 | #define OMAP4430_RSTTIME1_MASK (0x3ff << 0) |
| 1003 | 1015 | ||
| 1004 | /* Used by PRM_RSTTIME */ | 1016 | /* Used by PRM_RSTTIME */ |
| 1005 | #define OMAP4430_RSTTIME2_SHIFT 10 | 1017 | #define OMAP4430_RSTTIME2_SHIFT 10 |
| 1006 | #define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) | 1018 | #define OMAP4430_RSTTIME2_MASK (0x1f << 10) |
| 1007 | 1019 | ||
| 1008 | /* Used by PRM_RSTCTRL */ | 1020 | /* Used by PRM_RSTCTRL */ |
| 1009 | #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 | 1021 | #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 |
| 1010 | #define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) | 1022 | #define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) |
| 1011 | 1023 | ||
| 1012 | /* Used by PRM_RSTCTRL */ | 1024 | /* Used by PRM_RSTCTRL */ |
| 1013 | #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 | 1025 | #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 |
| 1014 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) | 1026 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) |
| 1027 | |||
| 1028 | /* Used by REVISION_PRM */ | ||
| 1029 | #define OMAP4430_R_RTL_SHIFT 11 | ||
| 1030 | #define OMAP4430_R_RTL_MASK (0x1f << 11) | ||
| 1015 | 1031 | ||
| 1016 | /* Used by PRM_VC_CFG_CHANNEL */ | 1032 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 1017 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 | 1033 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 |
| 1018 | #define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) | 1034 | #define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) |
| 1019 | 1035 | ||
| 1020 | /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ | 1036 | /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ |
| 1021 | #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 | 1037 | #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 |
| 1022 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) | 1038 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) |
| 1023 | 1039 | ||
| 1024 | /* Used by PRM_VC_CFG_CHANNEL */ | 1040 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 1025 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 | 1041 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 |
| 1026 | #define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) | 1042 | #define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) |
| 1027 | 1043 | ||
| 1028 | /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ | 1044 | /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ |
| 1029 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 | 1045 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 |
| 1030 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) | 1046 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) |
| 1031 | 1047 | ||
| 1032 | /* Used by PRM_VC_CFG_CHANNEL */ | 1048 | /* Used by PRM_VC_CFG_CHANNEL */ |
| 1033 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 | 1049 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 |
| 1034 | #define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) | 1050 | #define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) |
| 1035 | 1051 | ||
| 1036 | /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ | 1052 | /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ |
| 1037 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 | 1053 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 |
| 1038 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) | 1054 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) |
| 1055 | |||
| 1056 | /* Used by REVISION_PRM */ | ||
| 1057 | #define OMAP4430_SCHEME_SHIFT 30 | ||
| 1058 | #define OMAP4430_SCHEME_MASK (0x3 << 30) | ||
| 1039 | 1059 | ||
| 1040 | /* Used by PRM_VC_CFG_I2C_CLK */ | 1060 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 1041 | #define OMAP4430_SCLH_SHIFT 0 | 1061 | #define OMAP4430_SCLH_SHIFT 0 |
| 1042 | #define OMAP4430_SCLH_MASK BITFIELD(0, 7) | 1062 | #define OMAP4430_SCLH_MASK (0xff << 0) |
| 1043 | 1063 | ||
| 1044 | /* Used by PRM_VC_CFG_I2C_CLK */ | 1064 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 1045 | #define OMAP4430_SCLL_SHIFT 8 | 1065 | #define OMAP4430_SCLL_SHIFT 8 |
| 1046 | #define OMAP4430_SCLL_MASK BITFIELD(8, 15) | 1066 | #define OMAP4430_SCLL_MASK (0xff << 8) |
| 1047 | 1067 | ||
| 1048 | /* Used by PRM_RSTST */ | 1068 | /* Used by PRM_RSTST */ |
| 1049 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 | 1069 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 |
| 1050 | #define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) | 1070 | #define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) |
| 1051 | 1071 | ||
| 1052 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1072 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1053 | #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 | 1073 | #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 |
| 1054 | #define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) | 1074 | #define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) |
| 1055 | 1075 | ||
| 1056 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1076 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1057 | #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 | 1077 | #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 |
| 1058 | #define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) | 1078 | #define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) |
| 1059 | 1079 | ||
| 1060 | /* Used by PM_IVAHD_PWRSTST */ | 1080 | /* Used by PM_IVAHD_PWRSTST */ |
| 1061 | #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 | 1081 | #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 |
| 1062 | #define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) | 1082 | #define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) |
| 1063 | 1083 | ||
| 1064 | /* Used by PRM_VC_VAL_BYPASS */ | 1084 | /* Used by PRM_VC_VAL_BYPASS */ |
| 1065 | #define OMAP4430_SLAVEADDR_SHIFT 0 | 1085 | #define OMAP4430_SLAVEADDR_SHIFT 0 |
| 1066 | #define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) | 1086 | #define OMAP4430_SLAVEADDR_MASK (0x7f << 0) |
| 1067 | 1087 | ||
| 1068 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 1088 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 1069 | #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 | 1089 | #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 |
| 1070 | #define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) | 1090 | #define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) |
| 1071 | 1091 | ||
| 1072 | /* Used by PRM_SRAM_COUNT */ | 1092 | /* Used by PRM_SRAM_COUNT */ |
| 1073 | #define OMAP4430_SLPCNT_VALUE_SHIFT 16 | 1093 | #define OMAP4430_SLPCNT_VALUE_SHIFT 16 |
| 1074 | #define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) | 1094 | #define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) |
| 1075 | 1095 | ||
| 1076 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | 1096 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ |
| 1077 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 | 1097 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 |
| 1078 | #define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) | 1098 | #define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) |
| 1079 | 1099 | ||
| 1080 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | 1100 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ |
| 1081 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 | 1101 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 |
| 1082 | #define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) | 1102 | #define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) |
| 1103 | |||
| 1104 | /* Used by PRM_VC_ERRST */ | ||
| 1105 | #define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 | ||
| 1106 | #define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) | ||
| 1107 | |||
| 1108 | /* Used by PRM_VC_ERRST */ | ||
| 1109 | #define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 | ||
| 1110 | #define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) | ||
| 1111 | |||
| 1112 | /* Used by PRM_VC_ERRST */ | ||
| 1113 | #define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 | ||
| 1114 | #define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) | ||
| 1115 | |||
| 1116 | /* Used by PRM_VC_ERRST */ | ||
| 1117 | #define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 | ||
| 1118 | #define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) | ||
| 1119 | |||
| 1120 | /* Used by PRM_VC_ERRST */ | ||
| 1121 | #define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 | ||
| 1122 | #define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) | ||
| 1123 | |||
| 1124 | /* Used by PRM_VC_ERRST */ | ||
| 1125 | #define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 | ||
| 1126 | #define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) | ||
| 1127 | |||
| 1128 | /* Used by PRM_VC_ERRST */ | ||
| 1129 | #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 | ||
| 1130 | #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) | ||
| 1131 | |||
| 1132 | /* Used by PRM_VC_ERRST */ | ||
| 1133 | #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 | ||
| 1134 | #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) | ||
| 1135 | |||
| 1136 | /* Used by PRM_VC_ERRST */ | ||
| 1137 | #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 | ||
| 1138 | #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) | ||
| 1083 | 1139 | ||
| 1084 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 1140 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 1085 | #define OMAP4430_SR2EN_SHIFT 0 | 1141 | #define OMAP4430_SR2EN_SHIFT 0 |
| 1086 | #define OMAP4430_SR2EN_MASK BITFIELD(0, 0) | 1142 | #define OMAP4430_SR2EN_MASK (1 << 0) |
| 1087 | 1143 | ||
| 1088 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | 1144 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ |
| 1089 | #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 | 1145 | #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 |
| 1090 | #define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) | 1146 | #define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) |
| 1091 | 1147 | ||
| 1092 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | 1148 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ |
| 1093 | #define OMAP4430_SR2_STATUS_SHIFT 3 | 1149 | #define OMAP4430_SR2_STATUS_SHIFT 3 |
| 1094 | #define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) | 1150 | #define OMAP4430_SR2_STATUS_MASK (0x3 << 3) |
| 1095 | 1151 | ||
| 1096 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | 1152 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ |
| 1097 | #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 | 1153 | #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 |
| 1098 | #define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) | 1154 | #define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) |
| 1099 | 1155 | ||
| 1100 | /* | 1156 | /* |
| 1101 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | 1157 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, |
| 1102 | * PRM_LDO_SRAM_MPU_CTRL | 1158 | * PRM_LDO_SRAM_MPU_CTRL |
| 1103 | */ | 1159 | */ |
| 1104 | #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 | 1160 | #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 |
| 1105 | #define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) | 1161 | #define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) |
| 1106 | 1162 | ||
| 1107 | /* | 1163 | /* |
| 1108 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | 1164 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, |
| 1109 | * PRM_LDO_SRAM_MPU_CTRL | 1165 | * PRM_LDO_SRAM_MPU_CTRL |
| 1110 | */ | 1166 | */ |
| 1111 | #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 | 1167 | #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 |
| 1112 | #define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) | 1168 | #define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) |
| 1113 | 1169 | ||
| 1114 | /* Used by PRM_VC_CFG_I2C_MODE */ | 1170 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 1115 | #define OMAP4430_SRMODEEN_SHIFT 4 | 1171 | #define OMAP4430_SRMODEEN_SHIFT 4 |
| 1116 | #define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) | 1172 | #define OMAP4430_SRMODEEN_MASK (1 << 4) |
| 1117 | 1173 | ||
| 1118 | /* Used by PRM_VOLTSETUP_WARMRESET */ | 1174 | /* Used by PRM_VOLTSETUP_WARMRESET */ |
| 1119 | #define OMAP4430_STABLE_COUNT_SHIFT 0 | 1175 | #define OMAP4430_STABLE_COUNT_SHIFT 0 |
| 1120 | #define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) | 1176 | #define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) |
| 1121 | 1177 | ||
| 1122 | /* Used by PRM_VOLTSETUP_WARMRESET */ | 1178 | /* Used by PRM_VOLTSETUP_WARMRESET */ |
| 1123 | #define OMAP4430_STABLE_PRESCAL_SHIFT 8 | 1179 | #define OMAP4430_STABLE_PRESCAL_SHIFT 8 |
| 1124 | #define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) | 1180 | #define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) |
| 1181 | |||
| 1182 | /* Used by PRM_LDO_BANDGAP_SETUP */ | ||
| 1183 | #define OMAP4430_STARTUP_COUNT_SHIFT 0 | ||
| 1184 | #define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) | ||
| 1185 | |||
| 1186 | /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ | ||
| 1187 | #define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 | ||
| 1188 | #define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) | ||
| 1125 | 1189 | ||
| 1126 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1190 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1127 | #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 | 1191 | #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 |
| 1128 | #define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) | 1192 | #define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) |
| 1129 | 1193 | ||
| 1130 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1194 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1131 | #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 | 1195 | #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 |
| 1132 | #define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) | 1196 | #define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) |
| 1133 | 1197 | ||
| 1134 | /* Used by PM_IVAHD_PWRSTST */ | 1198 | /* Used by PM_IVAHD_PWRSTST */ |
| 1135 | #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 | 1199 | #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 |
| 1136 | #define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) | 1200 | #define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) |
| 1137 | 1201 | ||
| 1138 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1202 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1139 | #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 | 1203 | #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 |
| 1140 | #define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) | 1204 | #define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) |
| 1141 | 1205 | ||
| 1142 | /* Used by PM_IVAHD_PWRSTCTRL */ | 1206 | /* Used by PM_IVAHD_PWRSTCTRL */ |
| 1143 | #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 | 1207 | #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 |
| 1144 | #define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) | 1208 | #define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) |
| 1145 | 1209 | ||
| 1146 | /* Used by PM_IVAHD_PWRSTST */ | 1210 | /* Used by PM_IVAHD_PWRSTST */ |
| 1147 | #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 | 1211 | #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 |
| 1148 | #define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) | 1212 | #define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) |
| 1149 | 1213 | ||
| 1150 | /* Used by RM_TESLA_RSTST */ | 1214 | /* Used by RM_TESLA_RSTST */ |
| 1151 | #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 | 1215 | #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 |
| 1152 | #define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) | 1216 | #define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) |
| 1153 | 1217 | ||
| 1154 | /* Used by RM_TESLA_RSTST */ | 1218 | /* Used by RM_TESLA_RSTST */ |
| 1155 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 | 1219 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 |
| 1156 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) | 1220 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) |
| 1157 | 1221 | ||
| 1158 | /* Used by PM_TESLA_PWRSTCTRL */ | 1222 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1159 | #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 | 1223 | #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 |
| 1160 | #define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) | 1224 | #define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) |
| 1161 | 1225 | ||
| 1162 | /* Used by PM_TESLA_PWRSTCTRL */ | 1226 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1163 | #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 | 1227 | #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 |
| 1164 | #define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) | 1228 | #define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) |
| 1165 | 1229 | ||
| 1166 | /* Used by PM_TESLA_PWRSTST */ | 1230 | /* Used by PM_TESLA_PWRSTST */ |
| 1167 | #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 | 1231 | #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 |
| 1168 | #define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) | 1232 | #define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) |
| 1169 | 1233 | ||
| 1170 | /* Used by PM_TESLA_PWRSTCTRL */ | 1234 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1171 | #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 | 1235 | #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 |
| 1172 | #define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) | 1236 | #define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) |
| 1173 | 1237 | ||
| 1174 | /* Used by PM_TESLA_PWRSTCTRL */ | 1238 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1175 | #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 | 1239 | #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 |
| 1176 | #define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) | 1240 | #define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) |
| 1177 | 1241 | ||
| 1178 | /* Used by PM_TESLA_PWRSTST */ | 1242 | /* Used by PM_TESLA_PWRSTST */ |
| 1179 | #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 | 1243 | #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 |
| 1180 | #define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) | 1244 | #define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) |
| 1181 | 1245 | ||
| 1182 | /* Used by PM_TESLA_PWRSTCTRL */ | 1246 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1183 | #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 | 1247 | #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 |
| 1184 | #define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) | 1248 | #define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) |
| 1185 | 1249 | ||
| 1186 | /* Used by PM_TESLA_PWRSTCTRL */ | 1250 | /* Used by PM_TESLA_PWRSTCTRL */ |
| 1187 | #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 | 1251 | #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 |
| 1188 | #define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) | 1252 | #define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) |
| 1189 | 1253 | ||
| 1190 | /* Used by PM_TESLA_PWRSTST */ | 1254 | /* Used by PM_TESLA_PWRSTST */ |
| 1191 | #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 | 1255 | #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 |
| 1192 | #define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) | 1256 | #define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) |
| 1193 | 1257 | ||
| 1194 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | 1258 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ |
| 1195 | #define OMAP4430_TIMEOUT_SHIFT 0 | 1259 | #define OMAP4430_TIMEOUT_SHIFT 0 |
| 1196 | #define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) | 1260 | #define OMAP4430_TIMEOUT_MASK (0xffff << 0) |
| 1197 | 1261 | ||
| 1198 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 1262 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 1199 | #define OMAP4430_TIMEOUTEN_SHIFT 3 | 1263 | #define OMAP4430_TIMEOUTEN_SHIFT 3 |
| 1200 | #define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) | 1264 | #define OMAP4430_TIMEOUTEN_MASK (1 << 3) |
| 1201 | 1265 | ||
| 1202 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1266 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1203 | #define OMAP4430_TRANSITION_EN_SHIFT 8 | 1267 | #define OMAP4430_TRANSITION_EN_SHIFT 8 |
| 1204 | #define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) | 1268 | #define OMAP4430_TRANSITION_EN_MASK (1 << 8) |
| 1205 | 1269 | ||
| 1206 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1270 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1207 | #define OMAP4430_TRANSITION_ST_SHIFT 8 | 1271 | #define OMAP4430_TRANSITION_ST_SHIFT 8 |
| 1208 | #define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) | 1272 | #define OMAP4430_TRANSITION_ST_MASK (1 << 8) |
| 1209 | 1273 | ||
| 1210 | /* Used by PRM_VC_VAL_BYPASS */ | 1274 | /* Used by PRM_VC_VAL_BYPASS */ |
| 1211 | #define OMAP4430_VALID_SHIFT 24 | 1275 | #define OMAP4430_VALID_SHIFT 24 |
| 1212 | #define OMAP4430_VALID_MASK BITFIELD(24, 24) | 1276 | #define OMAP4430_VALID_MASK (1 << 24) |
| 1213 | 1277 | ||
| 1214 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1278 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1215 | #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 | 1279 | #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 |
| 1216 | #define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) | 1280 | #define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) |
| 1217 | 1281 | ||
| 1218 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1282 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1219 | #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 | 1283 | #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 |
| 1220 | #define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) | 1284 | #define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) |
| 1285 | |||
| 1286 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1287 | #define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 | ||
| 1288 | #define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) | ||
| 1289 | |||
| 1290 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1291 | #define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 | ||
| 1292 | #define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) | ||
| 1221 | 1293 | ||
| 1222 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1294 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1223 | #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 | 1295 | #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 |
| 1224 | #define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) | 1296 | #define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) |
| 1225 | 1297 | ||
| 1226 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1298 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1227 | #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 | 1299 | #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 |
| 1228 | #define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) | 1300 | #define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) |
| 1229 | 1301 | ||
| 1230 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1302 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1231 | #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 | 1303 | #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 |
| 1232 | #define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) | 1304 | #define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) |
| 1233 | 1305 | ||
| 1234 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1306 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1235 | #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 | 1307 | #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 |
| 1236 | #define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) | 1308 | #define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) |
| 1237 | 1309 | ||
| 1238 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1310 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1239 | #define OMAP4430_VC_RAERR_EN_SHIFT 12 | 1311 | #define OMAP4430_VC_RAERR_EN_SHIFT 12 |
| 1240 | #define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) | 1312 | #define OMAP4430_VC_RAERR_EN_MASK (1 << 12) |
| 1241 | 1313 | ||
| 1242 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1314 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1243 | #define OMAP4430_VC_RAERR_ST_SHIFT 12 | 1315 | #define OMAP4430_VC_RAERR_ST_SHIFT 12 |
| 1244 | #define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) | 1316 | #define OMAP4430_VC_RAERR_ST_MASK (1 << 12) |
| 1245 | 1317 | ||
| 1246 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1318 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1247 | #define OMAP4430_VC_SAERR_EN_SHIFT 11 | 1319 | #define OMAP4430_VC_SAERR_EN_SHIFT 11 |
| 1248 | #define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) | 1320 | #define OMAP4430_VC_SAERR_EN_MASK (1 << 11) |
| 1249 | 1321 | ||
| 1250 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1322 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1251 | #define OMAP4430_VC_SAERR_ST_SHIFT 11 | 1323 | #define OMAP4430_VC_SAERR_ST_SHIFT 11 |
| 1252 | #define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) | 1324 | #define OMAP4430_VC_SAERR_ST_MASK (1 << 11) |
| 1253 | 1325 | ||
| 1254 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1326 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1255 | #define OMAP4430_VC_TOERR_EN_SHIFT 13 | 1327 | #define OMAP4430_VC_TOERR_EN_SHIFT 13 |
| 1256 | #define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) | 1328 | #define OMAP4430_VC_TOERR_EN_MASK (1 << 13) |
| 1257 | 1329 | ||
| 1258 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1330 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1259 | #define OMAP4430_VC_TOERR_ST_SHIFT 13 | 1331 | #define OMAP4430_VC_TOERR_ST_SHIFT 13 |
| 1260 | #define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) | 1332 | #define OMAP4430_VC_TOERR_ST_MASK (1 << 13) |
| 1261 | 1333 | ||
| 1262 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | 1334 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ |
| 1263 | #define OMAP4430_VDDMAX_SHIFT 24 | 1335 | #define OMAP4430_VDDMAX_SHIFT 24 |
| 1264 | #define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) | 1336 | #define OMAP4430_VDDMAX_MASK (0xff << 24) |
| 1265 | 1337 | ||
| 1266 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | 1338 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ |
| 1267 | #define OMAP4430_VDDMIN_SHIFT 16 | 1339 | #define OMAP4430_VDDMIN_SHIFT 16 |
| 1268 | #define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) | 1340 | #define OMAP4430_VDDMIN_MASK (0xff << 16) |
| 1269 | 1341 | ||
| 1270 | /* Used by PRM_VOLTCTRL */ | 1342 | /* Used by PRM_VOLTCTRL */ |
| 1271 | #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 | 1343 | #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 |
| 1272 | #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) | 1344 | #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) |
| 1273 | 1345 | ||
| 1274 | /* Used by PRM_RSTST */ | 1346 | /* Used by PRM_RSTST */ |
| 1275 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 | 1347 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 |
| 1276 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) | 1348 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) |
| 1277 | 1349 | ||
| 1278 | /* Used by PRM_VOLTCTRL */ | 1350 | /* Used by PRM_VOLTCTRL */ |
| 1279 | #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 | 1351 | #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 |
| 1280 | #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) | 1352 | #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) |
| 1281 | 1353 | ||
| 1282 | /* Used by PRM_VOLTCTRL */ | 1354 | /* Used by PRM_VOLTCTRL */ |
| 1283 | #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 | 1355 | #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 |
| 1284 | #define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) | 1356 | #define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) |
| 1285 | 1357 | ||
| 1286 | /* Used by PRM_RSTST */ | 1358 | /* Used by PRM_RSTST */ |
| 1287 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 | 1359 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 |
| 1288 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) | 1360 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) |
| 1289 | 1361 | ||
| 1290 | /* Used by PRM_VOLTCTRL */ | 1362 | /* Used by PRM_VOLTCTRL */ |
| 1291 | #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 | 1363 | #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 |
| 1292 | #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) | 1364 | #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) |
| 1293 | 1365 | ||
| 1294 | /* Used by PRM_VOLTCTRL */ | 1366 | /* Used by PRM_VOLTCTRL */ |
| 1295 | #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 | 1367 | #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 |
| 1296 | #define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) | 1368 | #define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) |
| 1297 | 1369 | ||
| 1298 | /* Used by PRM_RSTST */ | 1370 | /* Used by PRM_RSTST */ |
| 1299 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 | 1371 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 |
| 1300 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) | 1372 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) |
| 1373 | |||
| 1374 | /* Used by PRM_VC_ERRST */ | ||
| 1375 | #define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 | ||
| 1376 | #define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) | ||
| 1377 | |||
| 1378 | /* Used by PRM_VC_ERRST */ | ||
| 1379 | #define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 | ||
| 1380 | #define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) | ||
| 1381 | |||
| 1382 | /* Used by PRM_VC_ERRST */ | ||
| 1383 | #define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 | ||
| 1384 | #define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) | ||
| 1385 | |||
| 1386 | /* Used by PRM_VC_ERRST */ | ||
| 1387 | #define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 | ||
| 1388 | #define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) | ||
| 1389 | |||
| 1390 | /* Used by PRM_VC_ERRST */ | ||
| 1391 | #define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 | ||
| 1392 | #define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) | ||
| 1393 | |||
| 1394 | /* Used by PRM_VC_ERRST */ | ||
| 1395 | #define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 | ||
| 1396 | #define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) | ||
| 1397 | |||
| 1398 | /* Used by PRM_VC_ERRST */ | ||
| 1399 | #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 | ||
| 1400 | #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) | ||
| 1401 | |||
| 1402 | /* Used by PRM_VC_ERRST */ | ||
| 1403 | #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 | ||
| 1404 | #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) | ||
| 1405 | |||
| 1406 | /* Used by PRM_VC_ERRST */ | ||
| 1407 | #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 | ||
| 1408 | #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) | ||
| 1301 | 1409 | ||
| 1302 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | 1410 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ |
| 1303 | #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 | 1411 | #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 |
| 1304 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) | 1412 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) |
| 1305 | 1413 | ||
| 1306 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | 1414 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ |
| 1307 | #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 | 1415 | #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 |
| 1308 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) | 1416 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) |
| 1309 | 1417 | ||
| 1310 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | 1418 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ |
| 1311 | #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 | 1419 | #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 |
| 1312 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) | 1420 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) |
| 1313 | 1421 | ||
| 1314 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | 1422 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ |
| 1315 | #define OMAP4430_VPENABLE_SHIFT 0 | 1423 | #define OMAP4430_VPENABLE_SHIFT 0 |
| 1316 | #define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) | 1424 | #define OMAP4430_VPENABLE_MASK (1 << 0) |
| 1317 | 1425 | ||
| 1318 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ | 1426 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ |
| 1319 | #define OMAP4430_VPINIDLE_SHIFT 0 | 1427 | #define OMAP4430_VPINIDLE_SHIFT 0 |
| 1320 | #define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) | 1428 | #define OMAP4430_VPINIDLE_MASK (1 << 0) |
| 1321 | 1429 | ||
| 1322 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | 1430 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ |
| 1323 | #define OMAP4430_VPVOLTAGE_SHIFT 0 | 1431 | #define OMAP4430_VPVOLTAGE_SHIFT 0 |
| 1324 | #define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) | 1432 | #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) |
| 1325 | 1433 | ||
| 1326 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1434 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1327 | #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 | 1435 | #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 |
| 1328 | #define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) | 1436 | #define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) |
| 1329 | 1437 | ||
| 1330 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1438 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1331 | #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 | 1439 | #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 |
| 1332 | #define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) | 1440 | #define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) |
| 1333 | 1441 | ||
| 1334 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1442 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1335 | #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 | 1443 | #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 |
| 1336 | #define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) | 1444 | #define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) |
| 1337 | 1445 | ||
| 1338 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1446 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1339 | #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 | 1447 | #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 |
| 1340 | #define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) | 1448 | #define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) |
| 1341 | 1449 | ||
| 1342 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1450 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1343 | #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 | 1451 | #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 |
| 1344 | #define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) | 1452 | #define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) |
| 1345 | 1453 | ||
| 1346 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1454 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1347 | #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 | 1455 | #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 |
| 1348 | #define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) | 1456 | #define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) |
| 1349 | 1457 | ||
| 1350 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1458 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1351 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 | 1459 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 |
| 1352 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) | 1460 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) |
| 1353 | 1461 | ||
| 1354 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1462 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1355 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 | 1463 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 |
| 1356 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) | 1464 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) |
| 1357 | 1465 | ||
| 1358 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1466 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1359 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 | 1467 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 |
| 1360 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) | 1468 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) |
| 1361 | 1469 | ||
| 1362 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1470 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1363 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 | 1471 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 |
| 1364 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) | 1472 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) |
| 1365 | 1473 | ||
| 1366 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1474 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1367 | #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 | 1475 | #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 |
| 1368 | #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) | 1476 | #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) |
| 1369 | 1477 | ||
| 1370 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1478 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1371 | #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 | 1479 | #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 |
| 1372 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) | 1480 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) |
| 1373 | 1481 | ||
| 1374 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1482 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1375 | #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 | 1483 | #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 |
| 1376 | #define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) | 1484 | #define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) |
| 1377 | 1485 | ||
| 1378 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1486 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1379 | #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 | 1487 | #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 |
| 1380 | #define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) | 1488 | #define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) |
| 1381 | 1489 | ||
| 1382 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1490 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1383 | #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 | 1491 | #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 |
| 1384 | #define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) | 1492 | #define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) |
| 1385 | 1493 | ||
| 1386 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1494 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1387 | #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 | 1495 | #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 |
| 1388 | #define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) | 1496 | #define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) |
| 1389 | 1497 | ||
| 1390 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1498 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1391 | #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 | 1499 | #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 |
| 1392 | #define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) | 1500 | #define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) |
| 1393 | 1501 | ||
| 1394 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1502 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1395 | #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 | 1503 | #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 |
| 1396 | #define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) | 1504 | #define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) |
| 1397 | 1505 | ||
| 1398 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1506 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1399 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 | 1507 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 |
| 1400 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) | 1508 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) |
| 1401 | 1509 | ||
| 1402 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1510 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1403 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 | 1511 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 |
| 1404 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) | 1512 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) |
| 1405 | 1513 | ||
| 1406 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1514 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1407 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 | 1515 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 |
| 1408 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) | 1516 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) |
| 1409 | 1517 | ||
| 1410 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1518 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1411 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 | 1519 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 |
| 1412 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) | 1520 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) |
| 1413 | 1521 | ||
| 1414 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | 1522 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ |
| 1415 | #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 | 1523 | #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 |
| 1416 | #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) | 1524 | #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) |
| 1417 | 1525 | ||
| 1418 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | 1526 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ |
| 1419 | #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 | 1527 | #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 |
| 1420 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) | 1528 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) |
| 1421 | 1529 | ||
| 1422 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1530 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1423 | #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 | 1531 | #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 |
| 1424 | #define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) | 1532 | #define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) |
| 1425 | 1533 | ||
| 1426 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1534 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1427 | #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 | 1535 | #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 |
| 1428 | #define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) | 1536 | #define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) |
| 1429 | 1537 | ||
| 1430 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1538 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1431 | #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 | 1539 | #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 |
| 1432 | #define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) | 1540 | #define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) |
| 1433 | 1541 | ||
| 1434 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1542 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1435 | #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 | 1543 | #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 |
| 1436 | #define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) | 1544 | #define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) |
| 1437 | 1545 | ||
| 1438 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1546 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1439 | #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 | 1547 | #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 |
| 1440 | #define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) | 1548 | #define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) |
| 1441 | 1549 | ||
| 1442 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1550 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1443 | #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 | 1551 | #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 |
| 1444 | #define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) | 1552 | #define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) |
| 1445 | 1553 | ||
| 1446 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1554 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1447 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 | 1555 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 |
| 1448 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) | 1556 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) |
| 1449 | 1557 | ||
| 1450 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1558 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1451 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 | 1559 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 |
| 1452 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) | 1560 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) |
| 1453 | 1561 | ||
| 1454 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1562 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1455 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 | 1563 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 |
| 1456 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) | 1564 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) |
| 1457 | 1565 | ||
| 1458 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1566 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1459 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 | 1567 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 |
| 1460 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) | 1568 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) |
| 1461 | 1569 | ||
| 1462 | /* Used by PRM_IRQENABLE_MPU_2 */ | 1570 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1463 | #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 | 1571 | #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 |
| 1464 | #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) | 1572 | #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) |
| 1465 | 1573 | ||
| 1466 | /* Used by PRM_IRQSTATUS_MPU_2 */ | 1574 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1467 | #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 | 1575 | #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 |
| 1468 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) | 1576 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) |
| 1469 | 1577 | ||
| 1470 | /* Used by PRM_SRAM_COUNT */ | 1578 | /* Used by PRM_SRAM_COUNT */ |
| 1471 | #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 | 1579 | #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 |
| 1472 | #define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) | 1580 | #define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) |
| 1473 | 1581 | ||
| 1474 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | 1582 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ |
| 1475 | #define OMAP4430_VSTEPMAX_SHIFT 0 | 1583 | #define OMAP4430_VSTEPMAX_SHIFT 0 |
| 1476 | #define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) | 1584 | #define OMAP4430_VSTEPMAX_MASK (0xff << 0) |
| 1477 | 1585 | ||
| 1478 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | 1586 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ |
| 1479 | #define OMAP4430_VSTEPMIN_SHIFT 0 | 1587 | #define OMAP4430_VSTEPMIN_SHIFT 0 |
| 1480 | #define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) | 1588 | #define OMAP4430_VSTEPMIN_MASK (0xff << 0) |
| 1481 | 1589 | ||
| 1482 | /* Used by PRM_MODEM_IF_CTRL */ | 1590 | /* Used by PRM_MODEM_IF_CTRL */ |
| 1483 | #define OMAP4430_WAKE_MODEM_SHIFT 0 | 1591 | #define OMAP4430_WAKE_MODEM_SHIFT 0 |
| 1484 | #define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) | 1592 | #define OMAP4430_WAKE_MODEM_MASK (1 << 0) |
| 1485 | 1593 | ||
| 1486 | /* Used by PM_DSS_DSS_WKDEP */ | 1594 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1487 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 | 1595 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 |
| 1488 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) | 1596 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) |
| 1489 | 1597 | ||
| 1490 | /* Used by PM_DSS_DSS_WKDEP */ | 1598 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1491 | #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 | 1599 | #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 |
| 1492 | #define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) | 1600 | #define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) |
| 1493 | 1601 | ||
| 1494 | /* Used by PM_DSS_DSS_WKDEP */ | 1602 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1495 | #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 | 1603 | #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 |
| 1496 | #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) | 1604 | #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) |
| 1497 | 1605 | ||
| 1498 | /* Used by PM_DSS_DSS_WKDEP */ | 1606 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1499 | #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 | 1607 | #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 |
| 1500 | #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) | 1608 | #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) |
| 1501 | 1609 | ||
| 1502 | /* Used by PM_ABE_DMIC_WKDEP */ | 1610 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1503 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 | 1611 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 |
| 1504 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) | 1612 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) |
| 1505 | 1613 | ||
| 1506 | /* Used by PM_ABE_DMIC_WKDEP */ | 1614 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1507 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 | 1615 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 |
| 1508 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) | 1616 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) |
| 1509 | 1617 | ||
| 1510 | /* Used by PM_ABE_DMIC_WKDEP */ | 1618 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1511 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 | 1619 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 |
| 1512 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) | 1620 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) |
| 1513 | 1621 | ||
| 1514 | /* Used by PM_ABE_DMIC_WKDEP */ | 1622 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1515 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 | 1623 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 |
| 1516 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) | 1624 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) |
| 1517 | 1625 | ||
| 1518 | /* Used by PM_L4PER_DMTIMER10_WKDEP */ | 1626 | /* Used by PM_L4PER_DMTIMER10_WKDEP */ |
| 1519 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 | 1627 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 |
| 1520 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) | 1628 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) |
| 1521 | 1629 | ||
| 1522 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | 1630 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ |
| 1523 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 | 1631 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 |
| 1524 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) | 1632 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) |
| 1525 | 1633 | ||
| 1526 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | 1634 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ |
| 1527 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 | 1635 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 |
| 1528 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) | 1636 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) |
| 1529 | 1637 | ||
| 1530 | /* Used by PM_L4PER_DMTIMER2_WKDEP */ | 1638 | /* Used by PM_L4PER_DMTIMER2_WKDEP */ |
| 1531 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 | 1639 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 |
| 1532 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) | 1640 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) |
| 1533 | 1641 | ||
| 1534 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | 1642 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ |
| 1535 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 | 1643 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 |
| 1536 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) | 1644 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) |
| 1537 | 1645 | ||
| 1538 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | 1646 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ |
| 1539 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 | 1647 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 |
| 1540 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) | 1648 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) |
| 1541 | 1649 | ||
| 1542 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | 1650 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ |
| 1543 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 | 1651 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 |
| 1544 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) | 1652 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) |
| 1545 | 1653 | ||
| 1546 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | 1654 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ |
| 1547 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 | 1655 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 |
| 1548 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) | 1656 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) |
| 1549 | 1657 | ||
| 1550 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | 1658 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ |
| 1551 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 | 1659 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 |
| 1552 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) | 1660 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) |
| 1553 | 1661 | ||
| 1554 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | 1662 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ |
| 1555 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 | 1663 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 |
| 1556 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) | 1664 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) |
| 1557 | 1665 | ||
| 1558 | /* Used by PM_DSS_DSS_WKDEP */ | 1666 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1559 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 | 1667 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 |
| 1560 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) | 1668 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) |
| 1561 | 1669 | ||
| 1562 | /* Used by PM_DSS_DSS_WKDEP */ | 1670 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1563 | #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 | 1671 | #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 |
| 1564 | #define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) | 1672 | #define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) |
| 1565 | 1673 | ||
| 1566 | /* Used by PM_DSS_DSS_WKDEP */ | 1674 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1567 | #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 | 1675 | #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 |
| 1568 | #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) | 1676 | #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) |
| 1569 | 1677 | ||
| 1570 | /* Used by PM_DSS_DSS_WKDEP */ | 1678 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1571 | #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 | 1679 | #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 |
| 1572 | #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) | 1680 | #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) |
| 1573 | 1681 | ||
| 1574 | /* Used by PM_DSS_DSS_WKDEP */ | 1682 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1575 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 | 1683 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 |
| 1576 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) | 1684 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) |
| 1577 | 1685 | ||
| 1578 | /* Used by PM_DSS_DSS_WKDEP */ | 1686 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1579 | #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 | 1687 | #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 |
| 1580 | #define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) | 1688 | #define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) |
| 1581 | 1689 | ||
| 1582 | /* Used by PM_DSS_DSS_WKDEP */ | 1690 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1583 | #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 | 1691 | #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 |
| 1584 | #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) | 1692 | #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) |
| 1585 | 1693 | ||
| 1586 | /* Used by PM_DSS_DSS_WKDEP */ | 1694 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1587 | #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 | 1695 | #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 |
| 1588 | #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) | 1696 | #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) |
| 1589 | 1697 | ||
| 1590 | /* Used by PM_WKUP_GPIO1_WKDEP */ | 1698 | /* Used by PM_WKUP_GPIO1_WKDEP */ |
| 1591 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 | 1699 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 |
| 1592 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) | 1700 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) |
| 1593 | 1701 | ||
| 1594 | /* Used by PM_WKUP_GPIO1_WKDEP */ | 1702 | /* Used by PM_WKUP_GPIO1_WKDEP */ |
| 1595 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 | 1703 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 |
| 1596 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) | 1704 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) |
| 1597 | 1705 | ||
| 1598 | /* Used by PM_WKUP_GPIO1_WKDEP */ | 1706 | /* Used by PM_WKUP_GPIO1_WKDEP */ |
| 1599 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 | 1707 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 |
| 1600 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1708 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) |
| 1601 | 1709 | ||
| 1602 | /* Used by PM_L4PER_GPIO2_WKDEP */ | 1710 | /* Used by PM_L4PER_GPIO2_WKDEP */ |
| 1603 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 | 1711 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 |
| 1604 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) | 1712 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) |
| 1605 | 1713 | ||
| 1606 | /* Used by PM_L4PER_GPIO2_WKDEP */ | 1714 | /* Used by PM_L4PER_GPIO2_WKDEP */ |
| 1607 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 | 1715 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 |
| 1608 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) | 1716 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) |
| 1609 | 1717 | ||
| 1610 | /* Used by PM_L4PER_GPIO2_WKDEP */ | 1718 | /* Used by PM_L4PER_GPIO2_WKDEP */ |
| 1611 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 | 1719 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 |
| 1612 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1720 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) |
| 1613 | 1721 | ||
| 1614 | /* Used by PM_L4PER_GPIO3_WKDEP */ | 1722 | /* Used by PM_L4PER_GPIO3_WKDEP */ |
| 1615 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 | 1723 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 |
| 1616 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) | 1724 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) |
| 1617 | 1725 | ||
| 1618 | /* Used by PM_L4PER_GPIO3_WKDEP */ | 1726 | /* Used by PM_L4PER_GPIO3_WKDEP */ |
| 1619 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 | 1727 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 |
| 1620 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1728 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) |
| 1621 | 1729 | ||
| 1622 | /* Used by PM_L4PER_GPIO4_WKDEP */ | 1730 | /* Used by PM_L4PER_GPIO4_WKDEP */ |
| 1623 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 | 1731 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 |
| 1624 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) | 1732 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) |
| 1625 | 1733 | ||
| 1626 | /* Used by PM_L4PER_GPIO4_WKDEP */ | 1734 | /* Used by PM_L4PER_GPIO4_WKDEP */ |
| 1627 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 | 1735 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 |
| 1628 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1736 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) |
| 1629 | 1737 | ||
| 1630 | /* Used by PM_L4PER_GPIO5_WKDEP */ | 1738 | /* Used by PM_L4PER_GPIO5_WKDEP */ |
| 1631 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 | 1739 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 |
| 1632 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) | 1740 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) |
| 1633 | 1741 | ||
| 1634 | /* Used by PM_L4PER_GPIO5_WKDEP */ | 1742 | /* Used by PM_L4PER_GPIO5_WKDEP */ |
| 1635 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 | 1743 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 |
| 1636 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1744 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) |
| 1637 | 1745 | ||
| 1638 | /* Used by PM_L4PER_GPIO6_WKDEP */ | 1746 | /* Used by PM_L4PER_GPIO6_WKDEP */ |
| 1639 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 | 1747 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 |
| 1640 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) | 1748 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) |
| 1641 | 1749 | ||
| 1642 | /* Used by PM_L4PER_GPIO6_WKDEP */ | 1750 | /* Used by PM_L4PER_GPIO6_WKDEP */ |
| 1643 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 | 1751 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 |
| 1644 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) | 1752 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) |
| 1645 | 1753 | ||
| 1646 | /* Used by PM_DSS_DSS_WKDEP */ | 1754 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1647 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 | 1755 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 |
| 1648 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) | 1756 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) |
| 1649 | 1757 | ||
| 1650 | /* Used by PM_DSS_DSS_WKDEP */ | 1758 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1651 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 | 1759 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 |
| 1652 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) | 1760 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) |
| 1653 | 1761 | ||
| 1654 | /* Used by PM_DSS_DSS_WKDEP */ | 1762 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1655 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 | 1763 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 |
| 1656 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) | 1764 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) |
| 1657 | 1765 | ||
| 1658 | /* Used by PM_DSS_DSS_WKDEP */ | 1766 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1659 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 | 1767 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 |
| 1660 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) | 1768 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) |
| 1661 | 1769 | ||
| 1662 | /* Used by PM_L4PER_HECC1_WKDEP */ | 1770 | /* Used by PM_L4PER_HECC1_WKDEP */ |
| 1663 | #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 | 1771 | #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 |
| 1664 | #define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) | 1772 | #define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) |
| 1665 | 1773 | ||
| 1666 | /* Used by PM_L4PER_HECC2_WKDEP */ | 1774 | /* Used by PM_L4PER_HECC2_WKDEP */ |
| 1667 | #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 | 1775 | #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 |
| 1668 | #define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) | 1776 | #define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) |
| 1669 | 1777 | ||
| 1670 | /* Used by PM_L3INIT_HSI_WKDEP */ | 1778 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 1671 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 | 1779 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 |
| 1672 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) | 1780 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) |
| 1673 | 1781 | ||
| 1674 | /* Used by PM_L3INIT_HSI_WKDEP */ | 1782 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 1675 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 | 1783 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 |
| 1676 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) | 1784 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) |
| 1677 | 1785 | ||
| 1678 | /* Used by PM_L3INIT_HSI_WKDEP */ | 1786 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 1679 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 | 1787 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 |
| 1680 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) | 1788 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) |
| 1681 | 1789 | ||
| 1682 | /* Used by PM_L4PER_I2C1_WKDEP */ | 1790 | /* Used by PM_L4PER_I2C1_WKDEP */ |
| 1683 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 | 1791 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 |
| 1684 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) | 1792 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) |
| 1685 | 1793 | ||
| 1686 | /* Used by PM_L4PER_I2C1_WKDEP */ | 1794 | /* Used by PM_L4PER_I2C1_WKDEP */ |
| 1687 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 | 1795 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 |
| 1688 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) | 1796 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) |
| 1689 | 1797 | ||
| 1690 | /* Used by PM_L4PER_I2C1_WKDEP */ | 1798 | /* Used by PM_L4PER_I2C1_WKDEP */ |
| 1691 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 | 1799 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 |
| 1692 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) | 1800 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) |
| 1693 | 1801 | ||
| 1694 | /* Used by PM_L4PER_I2C2_WKDEP */ | 1802 | /* Used by PM_L4PER_I2C2_WKDEP */ |
| 1695 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 | 1803 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 |
| 1696 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) | 1804 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) |
| 1697 | 1805 | ||
| 1698 | /* Used by PM_L4PER_I2C2_WKDEP */ | 1806 | /* Used by PM_L4PER_I2C2_WKDEP */ |
| 1699 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 | 1807 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 |
| 1700 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) | 1808 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) |
| 1701 | 1809 | ||
| 1702 | /* Used by PM_L4PER_I2C2_WKDEP */ | 1810 | /* Used by PM_L4PER_I2C2_WKDEP */ |
| 1703 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 | 1811 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 |
| 1704 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) | 1812 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) |
| 1705 | 1813 | ||
| 1706 | /* Used by PM_L4PER_I2C3_WKDEP */ | 1814 | /* Used by PM_L4PER_I2C3_WKDEP */ |
| 1707 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 | 1815 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 |
| 1708 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) | 1816 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) |
| 1709 | 1817 | ||
| 1710 | /* Used by PM_L4PER_I2C3_WKDEP */ | 1818 | /* Used by PM_L4PER_I2C3_WKDEP */ |
| 1711 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 | 1819 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 |
| 1712 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) | 1820 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) |
| 1713 | 1821 | ||
| 1714 | /* Used by PM_L4PER_I2C3_WKDEP */ | 1822 | /* Used by PM_L4PER_I2C3_WKDEP */ |
| 1715 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 | 1823 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 |
| 1716 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) | 1824 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) |
| 1717 | 1825 | ||
| 1718 | /* Used by PM_L4PER_I2C4_WKDEP */ | 1826 | /* Used by PM_L4PER_I2C4_WKDEP */ |
| 1719 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 | 1827 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 |
| 1720 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) | 1828 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) |
| 1721 | 1829 | ||
| 1722 | /* Used by PM_L4PER_I2C4_WKDEP */ | 1830 | /* Used by PM_L4PER_I2C4_WKDEP */ |
| 1723 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 | 1831 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 |
| 1724 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) | 1832 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) |
| 1725 | 1833 | ||
| 1726 | /* Used by PM_L4PER_I2C4_WKDEP */ | 1834 | /* Used by PM_L4PER_I2C4_WKDEP */ |
| 1727 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 | 1835 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 |
| 1728 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) | 1836 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) |
| 1729 | 1837 | ||
| 1730 | /* Used by PM_L4PER_I2C5_WKDEP */ | 1838 | /* Used by PM_L4PER_I2C5_WKDEP */ |
| 1731 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 | 1839 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 |
| 1732 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) | 1840 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) |
| 1733 | 1841 | ||
| 1734 | /* Used by PM_L4PER_I2C5_WKDEP */ | 1842 | /* Used by PM_L4PER_I2C5_WKDEP */ |
| 1735 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 | 1843 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 |
| 1736 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) | 1844 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) |
| 1737 | 1845 | ||
| 1738 | /* Used by PM_WKUP_KEYBOARD_WKDEP */ | 1846 | /* Used by PM_WKUP_KEYBOARD_WKDEP */ |
| 1739 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 | 1847 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 |
| 1740 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) | 1848 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) |
| 1741 | 1849 | ||
| 1742 | /* Used by PM_ABE_MCASP_WKDEP */ | 1850 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 1743 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 | 1851 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 |
| 1744 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) | 1852 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) |
| 1745 | 1853 | ||
| 1746 | /* Used by PM_ABE_MCASP_WKDEP */ | 1854 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 1747 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 | 1855 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 |
| 1748 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) | 1856 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) |
| 1749 | 1857 | ||
| 1750 | /* Used by PM_ABE_MCASP_WKDEP */ | 1858 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 1751 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 | 1859 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 |
| 1752 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) | 1860 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) |
| 1753 | 1861 | ||
| 1754 | /* Used by PM_ABE_MCASP_WKDEP */ | 1862 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 1755 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 | 1863 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 |
| 1756 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) | 1864 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) |
| 1757 | 1865 | ||
| 1758 | /* Used by PM_L4PER_MCASP2_WKDEP */ | 1866 | /* Used by PM_L4PER_MCASP2_WKDEP */ |
| 1759 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 | 1867 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 |
| 1760 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) | 1868 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) |
| 1761 | 1869 | ||
| 1762 | /* Used by PM_L4PER_MCASP2_WKDEP */ | 1870 | /* Used by PM_L4PER_MCASP2_WKDEP */ |
| 1763 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 | 1871 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 |
| 1764 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) | 1872 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) |
| 1765 | 1873 | ||
| 1766 | /* Used by PM_L4PER_MCASP2_WKDEP */ | 1874 | /* Used by PM_L4PER_MCASP2_WKDEP */ |
| 1767 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 | 1875 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 |
| 1768 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) | 1876 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) |
| 1769 | 1877 | ||
| 1770 | /* Used by PM_L4PER_MCASP2_WKDEP */ | 1878 | /* Used by PM_L4PER_MCASP2_WKDEP */ |
| 1771 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 | 1879 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 |
| 1772 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) | 1880 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) |
| 1773 | 1881 | ||
| 1774 | /* Used by PM_L4PER_MCASP3_WKDEP */ | 1882 | /* Used by PM_L4PER_MCASP3_WKDEP */ |
| 1775 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 | 1883 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 |
| 1776 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) | 1884 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) |
| 1777 | 1885 | ||
| 1778 | /* Used by PM_L4PER_MCASP3_WKDEP */ | 1886 | /* Used by PM_L4PER_MCASP3_WKDEP */ |
| 1779 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 | 1887 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 |
| 1780 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) | 1888 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) |
| 1781 | 1889 | ||
| 1782 | /* Used by PM_L4PER_MCASP3_WKDEP */ | 1890 | /* Used by PM_L4PER_MCASP3_WKDEP */ |
| 1783 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 | 1891 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 |
| 1784 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) | 1892 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) |
| 1785 | 1893 | ||
| 1786 | /* Used by PM_L4PER_MCASP3_WKDEP */ | 1894 | /* Used by PM_L4PER_MCASP3_WKDEP */ |
| 1787 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 | 1895 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 |
| 1788 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) | 1896 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) |
| 1789 | 1897 | ||
| 1790 | /* Used by PM_ABE_MCBSP1_WKDEP */ | 1898 | /* Used by PM_ABE_MCBSP1_WKDEP */ |
| 1791 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 | 1899 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 |
| 1792 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) | 1900 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) |
| 1793 | 1901 | ||
| 1794 | /* Used by PM_ABE_MCBSP1_WKDEP */ | 1902 | /* Used by PM_ABE_MCBSP1_WKDEP */ |
| 1795 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 | 1903 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 |
| 1796 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) | 1904 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) |
| 1797 | 1905 | ||
| 1798 | /* Used by PM_ABE_MCBSP1_WKDEP */ | 1906 | /* Used by PM_ABE_MCBSP1_WKDEP */ |
| 1799 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 | 1907 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 |
| 1800 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) | 1908 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) |
| 1801 | 1909 | ||
| 1802 | /* Used by PM_ABE_MCBSP2_WKDEP */ | 1910 | /* Used by PM_ABE_MCBSP2_WKDEP */ |
| 1803 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 | 1911 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 |
| 1804 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) | 1912 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) |
| 1805 | 1913 | ||
| 1806 | /* Used by PM_ABE_MCBSP2_WKDEP */ | 1914 | /* Used by PM_ABE_MCBSP2_WKDEP */ |
| 1807 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 | 1915 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 |
| 1808 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) | 1916 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) |
| 1809 | 1917 | ||
| 1810 | /* Used by PM_ABE_MCBSP2_WKDEP */ | 1918 | /* Used by PM_ABE_MCBSP2_WKDEP */ |
| 1811 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 | 1919 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 |
| 1812 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) | 1920 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) |
| 1813 | 1921 | ||
| 1814 | /* Used by PM_ABE_MCBSP3_WKDEP */ | 1922 | /* Used by PM_ABE_MCBSP3_WKDEP */ |
| 1815 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 | 1923 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 |
| 1816 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) | 1924 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) |
| 1817 | 1925 | ||
| 1818 | /* Used by PM_ABE_MCBSP3_WKDEP */ | 1926 | /* Used by PM_ABE_MCBSP3_WKDEP */ |
| 1819 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 | 1927 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 |
| 1820 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) | 1928 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) |
| 1821 | 1929 | ||
| 1822 | /* Used by PM_ABE_MCBSP3_WKDEP */ | 1930 | /* Used by PM_ABE_MCBSP3_WKDEP */ |
| 1823 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 | 1931 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 |
| 1824 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) | 1932 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) |
| 1825 | 1933 | ||
| 1826 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | 1934 | /* Used by PM_L4PER_MCBSP4_WKDEP */ |
| 1827 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 | 1935 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 |
| 1828 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) | 1936 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) |
| 1829 | 1937 | ||
| 1830 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | 1938 | /* Used by PM_L4PER_MCBSP4_WKDEP */ |
| 1831 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 | 1939 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 |
| 1832 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) | 1940 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) |
| 1833 | 1941 | ||
| 1834 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | 1942 | /* Used by PM_L4PER_MCBSP4_WKDEP */ |
| 1835 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 | 1943 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 |
| 1836 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) | 1944 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) |
| 1837 | 1945 | ||
| 1838 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | 1946 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 1839 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 | 1947 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 |
| 1840 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) | 1948 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) |
| 1841 | 1949 | ||
| 1842 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | 1950 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 1843 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 | 1951 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 |
| 1844 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) | 1952 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) |
| 1845 | 1953 | ||
| 1846 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | 1954 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 1847 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 | 1955 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 |
| 1848 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) | 1956 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) |
| 1849 | 1957 | ||
| 1850 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | 1958 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 1851 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 | 1959 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 |
| 1852 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) | 1960 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) |
| 1853 | 1961 | ||
| 1854 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | 1962 | /* Used by PM_L4PER_MCSPI2_WKDEP */ |
| 1855 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 | 1963 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 |
| 1856 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) | 1964 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) |
| 1857 | 1965 | ||
| 1858 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | 1966 | /* Used by PM_L4PER_MCSPI2_WKDEP */ |
| 1859 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 | 1967 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 |
| 1860 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) | 1968 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) |
| 1861 | 1969 | ||
| 1862 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | 1970 | /* Used by PM_L4PER_MCSPI2_WKDEP */ |
| 1863 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 | 1971 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 |
| 1864 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) | 1972 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) |
| 1865 | 1973 | ||
| 1866 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | 1974 | /* Used by PM_L4PER_MCSPI3_WKDEP */ |
| 1867 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 | 1975 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 |
| 1868 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) | 1976 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) |
| 1869 | 1977 | ||
| 1870 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | 1978 | /* Used by PM_L4PER_MCSPI3_WKDEP */ |
| 1871 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 | 1979 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 |
| 1872 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) | 1980 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) |
| 1873 | 1981 | ||
| 1874 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | 1982 | /* Used by PM_L4PER_MCSPI4_WKDEP */ |
| 1875 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 | 1983 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 |
| 1876 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) | 1984 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) |
| 1877 | 1985 | ||
| 1878 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | 1986 | /* Used by PM_L4PER_MCSPI4_WKDEP */ |
| 1879 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 | 1987 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 |
| 1880 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) | 1988 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) |
| 1881 | 1989 | ||
| 1882 | /* Used by PM_L3INIT_MMC1_WKDEP */ | 1990 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 1883 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 | 1991 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 |
| 1884 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) | 1992 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) |
| 1885 | 1993 | ||
| 1886 | /* Used by PM_L3INIT_MMC1_WKDEP */ | 1994 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 1887 | #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 | 1995 | #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 |
| 1888 | #define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) | 1996 | #define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) |
| 1889 | 1997 | ||
| 1890 | /* Used by PM_L3INIT_MMC1_WKDEP */ | 1998 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 1891 | #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 | 1999 | #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 |
| 1892 | #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) | 2000 | #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) |
| 1893 | 2001 | ||
| 1894 | /* Used by PM_L3INIT_MMC1_WKDEP */ | 2002 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 1895 | #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 | 2003 | #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 |
| 1896 | #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) | 2004 | #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) |
| 1897 | 2005 | ||
| 1898 | /* Used by PM_L3INIT_MMC2_WKDEP */ | 2006 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 1899 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 | 2007 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 |
| 1900 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) | 2008 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) |
| 1901 | 2009 | ||
| 1902 | /* Used by PM_L3INIT_MMC2_WKDEP */ | 2010 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 1903 | #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 | 2011 | #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 |
| 1904 | #define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) | 2012 | #define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) |
| 1905 | 2013 | ||
| 1906 | /* Used by PM_L3INIT_MMC2_WKDEP */ | 2014 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 1907 | #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 | 2015 | #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 |
| 1908 | #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) | 2016 | #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) |
| 1909 | 2017 | ||
| 1910 | /* Used by PM_L3INIT_MMC2_WKDEP */ | 2018 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 1911 | #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 | 2019 | #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 |
| 1912 | #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) | 2020 | #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) |
| 1913 | 2021 | ||
| 1914 | /* Used by PM_L3INIT_MMC6_WKDEP */ | 2022 | /* Used by PM_L3INIT_MMC6_WKDEP */ |
| 1915 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 | 2023 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 |
| 1916 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) | 2024 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) |
| 1917 | 2025 | ||
| 1918 | /* Used by PM_L3INIT_MMC6_WKDEP */ | 2026 | /* Used by PM_L3INIT_MMC6_WKDEP */ |
| 1919 | #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 | 2027 | #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 |
| 1920 | #define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) | 2028 | #define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) |
| 1921 | 2029 | ||
| 1922 | /* Used by PM_L3INIT_MMC6_WKDEP */ | 2030 | /* Used by PM_L3INIT_MMC6_WKDEP */ |
| 1923 | #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 | 2031 | #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 |
| 1924 | #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) | 2032 | #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) |
| 1925 | 2033 | ||
| 1926 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | 2034 | /* Used by PM_L4PER_MMCSD3_WKDEP */ |
| 1927 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 | 2035 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 |
| 1928 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) | 2036 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) |
| 1929 | 2037 | ||
| 1930 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | 2038 | /* Used by PM_L4PER_MMCSD3_WKDEP */ |
| 1931 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 | 2039 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 |
| 1932 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) | 2040 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) |
| 1933 | 2041 | ||
| 1934 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | 2042 | /* Used by PM_L4PER_MMCSD3_WKDEP */ |
| 1935 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 | 2043 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 |
| 1936 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) | 2044 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) |
| 1937 | 2045 | ||
| 1938 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | 2046 | /* Used by PM_L4PER_MMCSD4_WKDEP */ |
| 1939 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 | 2047 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 |
| 1940 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) | 2048 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) |
| 1941 | 2049 | ||
| 1942 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | 2050 | /* Used by PM_L4PER_MMCSD4_WKDEP */ |
| 1943 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 | 2051 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 |
| 1944 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) | 2052 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) |
| 1945 | 2053 | ||
| 1946 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | 2054 | /* Used by PM_L4PER_MMCSD4_WKDEP */ |
| 1947 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 | 2055 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 |
| 1948 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) | 2056 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) |
| 1949 | 2057 | ||
| 1950 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | 2058 | /* Used by PM_L4PER_MMCSD5_WKDEP */ |
| 1951 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 | 2059 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 |
| 1952 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) | 2060 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) |
| 1953 | 2061 | ||
| 1954 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | 2062 | /* Used by PM_L4PER_MMCSD5_WKDEP */ |
| 1955 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 | 2063 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 |
| 1956 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) | 2064 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) |
| 1957 | 2065 | ||
| 1958 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | 2066 | /* Used by PM_L4PER_MMCSD5_WKDEP */ |
| 1959 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 | 2067 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 |
| 1960 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) | 2068 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) |
| 1961 | 2069 | ||
| 1962 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | 2070 | /* Used by PM_L3INIT_PCIESS_WKDEP */ |
| 1963 | #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 | 2071 | #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 |
| 1964 | #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) | 2072 | #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) |
| 1965 | 2073 | ||
| 1966 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | 2074 | /* Used by PM_L3INIT_PCIESS_WKDEP */ |
| 1967 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 | 2075 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 |
| 1968 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) | 2076 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) |
| 1969 | 2077 | ||
| 1970 | /* Used by PM_ABE_PDM_WKDEP */ | 2078 | /* Used by PM_ABE_PDM_WKDEP */ |
| 1971 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 | 2079 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 |
| 1972 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) | 2080 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) |
| 1973 | 2081 | ||
| 1974 | /* Used by PM_ABE_PDM_WKDEP */ | 2082 | /* Used by PM_ABE_PDM_WKDEP */ |
| 1975 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 | 2083 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 |
| 1976 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) | 2084 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) |
| 1977 | 2085 | ||
| 1978 | /* Used by PM_ABE_PDM_WKDEP */ | 2086 | /* Used by PM_ABE_PDM_WKDEP */ |
| 1979 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 | 2087 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 |
| 1980 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) | 2088 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) |
| 1981 | 2089 | ||
| 1982 | /* Used by PM_ABE_PDM_WKDEP */ | 2090 | /* Used by PM_ABE_PDM_WKDEP */ |
| 1983 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 | 2091 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 |
| 1984 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) | 2092 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) |
| 1985 | 2093 | ||
| 1986 | /* Used by PM_WKUP_RTC_WKDEP */ | 2094 | /* Used by PM_WKUP_RTC_WKDEP */ |
| 1987 | #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 | 2095 | #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 |
| 1988 | #define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) | 2096 | #define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) |
| 1989 | 2097 | ||
| 1990 | /* Used by PM_L3INIT_SATA_WKDEP */ | 2098 | /* Used by PM_L3INIT_SATA_WKDEP */ |
| 1991 | #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 | 2099 | #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 |
| 1992 | #define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) | 2100 | #define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) |
| 1993 | 2101 | ||
| 1994 | /* Used by PM_L3INIT_SATA_WKDEP */ | 2102 | /* Used by PM_L3INIT_SATA_WKDEP */ |
| 1995 | #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 | 2103 | #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 |
| 1996 | #define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) | 2104 | #define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) |
| 1997 | 2105 | ||
| 1998 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | 2106 | /* Used by PM_ABE_SLIMBUS_WKDEP */ |
| 1999 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 | 2107 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 |
| 2000 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) | 2108 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) |
| 2001 | 2109 | ||
| 2002 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | 2110 | /* Used by PM_ABE_SLIMBUS_WKDEP */ |
| 2003 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 | 2111 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 |
| 2004 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) | 2112 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) |
| 2005 | 2113 | ||
| 2006 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | 2114 | /* Used by PM_ABE_SLIMBUS_WKDEP */ |
| 2007 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 | 2115 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 |
| 2008 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) | 2116 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) |
| 2009 | 2117 | ||
| 2010 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | 2118 | /* Used by PM_ABE_SLIMBUS_WKDEP */ |
| 2011 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 | 2119 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 |
| 2012 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) | 2120 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) |
| 2013 | 2121 | ||
| 2014 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | 2122 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ |
| 2015 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 | 2123 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 |
| 2016 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) | 2124 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) |
| 2017 | 2125 | ||
| 2018 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | 2126 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ |
| 2019 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 | 2127 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 |
| 2020 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) | 2128 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) |
| 2021 | 2129 | ||
| 2022 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | 2130 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ |
| 2023 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 | 2131 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 |
| 2024 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) | 2132 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) |
| 2025 | 2133 | ||
| 2026 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | 2134 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ |
| 2027 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 | 2135 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 |
| 2028 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) | 2136 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) |
| 2029 | 2137 | ||
| 2030 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | 2138 | /* Used by PM_ALWON_SR_CORE_WKDEP */ |
| 2031 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 | 2139 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 |
| 2032 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) | 2140 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) |
| 2033 | 2141 | ||
| 2034 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | 2142 | /* Used by PM_ALWON_SR_CORE_WKDEP */ |
| 2035 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 | 2143 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 |
| 2036 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) | 2144 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) |
| 2037 | 2145 | ||
| 2038 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | 2146 | /* Used by PM_ALWON_SR_IVA_WKDEP */ |
| 2039 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 | 2147 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 |
| 2040 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) | 2148 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) |
| 2041 | 2149 | ||
| 2042 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | 2150 | /* Used by PM_ALWON_SR_IVA_WKDEP */ |
| 2043 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 | 2151 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 |
| 2044 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) | 2152 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) |
| 2045 | 2153 | ||
| 2046 | /* Used by PM_ALWON_SR_MPU_WKDEP */ | 2154 | /* Used by PM_ALWON_SR_MPU_WKDEP */ |
| 2047 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 | 2155 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 |
| 2048 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) | 2156 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) |
| 2049 | 2157 | ||
| 2050 | /* Used by PM_WKUP_TIMER12_WKDEP */ | 2158 | /* Used by PM_WKUP_TIMER12_WKDEP */ |
| 2051 | #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 | 2159 | #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 |
| 2052 | #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) | 2160 | #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) |
| 2053 | 2161 | ||
| 2054 | /* Used by PM_WKUP_TIMER1_WKDEP */ | 2162 | /* Used by PM_WKUP_TIMER1_WKDEP */ |
| 2055 | #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 | 2163 | #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 |
| 2056 | #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) | 2164 | #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) |
| 2057 | 2165 | ||
| 2058 | /* Used by PM_ABE_TIMER5_WKDEP */ | 2166 | /* Used by PM_ABE_TIMER5_WKDEP */ |
| 2059 | #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 | 2167 | #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 |
| 2060 | #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) | 2168 | #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) |
| 2061 | 2169 | ||
| 2062 | /* Used by PM_ABE_TIMER5_WKDEP */ | 2170 | /* Used by PM_ABE_TIMER5_WKDEP */ |
| 2063 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 | 2171 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 |
| 2064 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) | 2172 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) |
| 2065 | 2173 | ||
| 2066 | /* Used by PM_ABE_TIMER6_WKDEP */ | 2174 | /* Used by PM_ABE_TIMER6_WKDEP */ |
| 2067 | #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 | 2175 | #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 |
| 2068 | #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) | 2176 | #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) |
| 2069 | 2177 | ||
| 2070 | /* Used by PM_ABE_TIMER6_WKDEP */ | 2178 | /* Used by PM_ABE_TIMER6_WKDEP */ |
| 2071 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 | 2179 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 |
| 2072 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) | 2180 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) |
| 2073 | 2181 | ||
| 2074 | /* Used by PM_ABE_TIMER7_WKDEP */ | 2182 | /* Used by PM_ABE_TIMER7_WKDEP */ |
| 2075 | #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 | 2183 | #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 |
| 2076 | #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) | 2184 | #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) |
| 2077 | 2185 | ||
| 2078 | /* Used by PM_ABE_TIMER7_WKDEP */ | 2186 | /* Used by PM_ABE_TIMER7_WKDEP */ |
| 2079 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 | 2187 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 |
| 2080 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) | 2188 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) |
| 2081 | 2189 | ||
| 2082 | /* Used by PM_ABE_TIMER8_WKDEP */ | 2190 | /* Used by PM_ABE_TIMER8_WKDEP */ |
| 2083 | #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 | 2191 | #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 |
| 2084 | #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) | 2192 | #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) |
| 2085 | 2193 | ||
| 2086 | /* Used by PM_ABE_TIMER8_WKDEP */ | 2194 | /* Used by PM_ABE_TIMER8_WKDEP */ |
| 2087 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 | 2195 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 |
| 2088 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) | 2196 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) |
| 2089 | 2197 | ||
| 2090 | /* Used by PM_L4PER_UART1_WKDEP */ | 2198 | /* Used by PM_L4PER_UART1_WKDEP */ |
| 2091 | #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 | 2199 | #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 |
| 2092 | #define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) | 2200 | #define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) |
| 2093 | 2201 | ||
| 2094 | /* Used by PM_L4PER_UART1_WKDEP */ | 2202 | /* Used by PM_L4PER_UART1_WKDEP */ |
| 2095 | #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 | 2203 | #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 |
| 2096 | #define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) | 2204 | #define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) |
| 2097 | 2205 | ||
| 2098 | /* Used by PM_L4PER_UART2_WKDEP */ | 2206 | /* Used by PM_L4PER_UART2_WKDEP */ |
| 2099 | #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 | 2207 | #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 |
| 2100 | #define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) | 2208 | #define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) |
| 2101 | 2209 | ||
| 2102 | /* Used by PM_L4PER_UART2_WKDEP */ | 2210 | /* Used by PM_L4PER_UART2_WKDEP */ |
| 2103 | #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 | 2211 | #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 |
| 2104 | #define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) | 2212 | #define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) |
| 2105 | 2213 | ||
| 2106 | /* Used by PM_L4PER_UART3_WKDEP */ | 2214 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2107 | #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 | 2215 | #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 |
| 2108 | #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) | 2216 | #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) |
| 2109 | 2217 | ||
| 2110 | /* Used by PM_L4PER_UART3_WKDEP */ | 2218 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2111 | #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 | 2219 | #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 |
| 2112 | #define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) | 2220 | #define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) |
| 2113 | 2221 | ||
| 2114 | /* Used by PM_L4PER_UART3_WKDEP */ | 2222 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2115 | #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 | 2223 | #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 |
| 2116 | #define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) | 2224 | #define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) |
| 2117 | 2225 | ||
| 2118 | /* Used by PM_L4PER_UART3_WKDEP */ | 2226 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2119 | #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 | 2227 | #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 |
| 2120 | #define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) | 2228 | #define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) |
| 2121 | 2229 | ||
| 2122 | /* Used by PM_L4PER_UART4_WKDEP */ | 2230 | /* Used by PM_L4PER_UART4_WKDEP */ |
| 2123 | #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 | 2231 | #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 |
| 2124 | #define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) | 2232 | #define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) |
| 2125 | 2233 | ||
| 2126 | /* Used by PM_L4PER_UART4_WKDEP */ | 2234 | /* Used by PM_L4PER_UART4_WKDEP */ |
| 2127 | #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 | 2235 | #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 |
| 2128 | #define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) | 2236 | #define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) |
| 2129 | 2237 | ||
| 2130 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | 2238 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ |
| 2131 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 | 2239 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 |
| 2132 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) | 2240 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) |
| 2133 | 2241 | ||
| 2134 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | 2242 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ |
| 2135 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 | 2243 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 |
| 2136 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) | 2244 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) |
| 2137 | 2245 | ||
| 2138 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | 2246 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ |
| 2139 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 | 2247 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 |
| 2140 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) | 2248 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) |
| 2141 | 2249 | ||
| 2142 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | 2250 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ |
| 2143 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 | 2251 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 |
| 2144 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) | 2252 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) |
| 2145 | 2253 | ||
| 2146 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | 2254 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ |
| 2147 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 | 2255 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 |
| 2148 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) | 2256 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) |
| 2149 | 2257 | ||
| 2150 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | 2258 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ |
| 2151 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 | 2259 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 |
| 2152 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) | 2260 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) |
| 2153 | 2261 | ||
| 2154 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | 2262 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ |
| 2155 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 | 2263 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 |
| 2156 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) | 2264 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) |
| 2157 | 2265 | ||
| 2158 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | 2266 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ |
| 2159 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 | 2267 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 |
| 2160 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) | 2268 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) |
| 2161 | 2269 | ||
| 2162 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | 2270 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ |
| 2163 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 | 2271 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 |
| 2164 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) | 2272 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) |
| 2165 | 2273 | ||
| 2166 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | 2274 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ |
| 2167 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 | 2275 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 |
| 2168 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) | 2276 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) |
| 2169 | 2277 | ||
| 2170 | /* Used by PM_WKUP_USIM_WKDEP */ | 2278 | /* Used by PM_WKUP_USIM_WKDEP */ |
| 2171 | #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 | 2279 | #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 |
| 2172 | #define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) | 2280 | #define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) |
| 2173 | 2281 | ||
| 2174 | /* Used by PM_WKUP_USIM_WKDEP */ | 2282 | /* Used by PM_WKUP_USIM_WKDEP */ |
| 2175 | #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 | 2283 | #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 |
| 2176 | #define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) | 2284 | #define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) |
| 2177 | 2285 | ||
| 2178 | /* Used by PM_WKUP_WDT2_WKDEP */ | 2286 | /* Used by PM_WKUP_WDT2_WKDEP */ |
| 2179 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 | 2287 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 |
| 2180 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) | 2288 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) |
| 2181 | 2289 | ||
| 2182 | /* Used by PM_WKUP_WDT2_WKDEP */ | 2290 | /* Used by PM_WKUP_WDT2_WKDEP */ |
| 2183 | #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 | 2291 | #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 |
| 2184 | #define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) | 2292 | #define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) |
| 2185 | 2293 | ||
| 2186 | /* Used by PM_ABE_WDT3_WKDEP */ | 2294 | /* Used by PM_ABE_WDT3_WKDEP */ |
| 2187 | #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 | 2295 | #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 |
| 2188 | #define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) | 2296 | #define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) |
| 2189 | 2297 | ||
| 2190 | /* Used by PM_L3INIT_HSI_WKDEP */ | 2298 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 2191 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 | 2299 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 |
| 2192 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) | 2300 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) |
| 2193 | 2301 | ||
| 2194 | /* Used by PM_L3INIT_XHPI_WKDEP */ | 2302 | /* Used by PM_L3INIT_XHPI_WKDEP */ |
| 2195 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 | 2303 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 |
| 2196 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) | 2304 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) |
| 2197 | 2305 | ||
| 2198 | /* Used by PRM_IO_PMCTRL */ | 2306 | /* Used by PRM_IO_PMCTRL */ |
| 2199 | #define OMAP4430_WUCLK_CTRL_SHIFT 8 | 2307 | #define OMAP4430_WUCLK_CTRL_SHIFT 8 |
| 2200 | #define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) | 2308 | #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) |
| 2201 | 2309 | ||
| 2202 | /* Used by PRM_IO_PMCTRL */ | 2310 | /* Used by PRM_IO_PMCTRL */ |
| 2203 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 | 2311 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 |
| 2204 | #define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) | 2312 | #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) |
| 2313 | |||
| 2314 | /* Used by REVISION_PRM */ | ||
| 2315 | #define OMAP4430_X_MAJOR_SHIFT 8 | ||
| 2316 | #define OMAP4430_X_MAJOR_MASK (0x7 << 8) | ||
| 2317 | |||
| 2318 | /* Used by REVISION_PRM */ | ||
| 2319 | #define OMAP4430_Y_MINOR_SHIFT 0 | ||
| 2320 | #define OMAP4430_Y_MINOR_MASK (0x3f << 0) | ||
| 2205 | #endif | 2321 | #endif |