diff options
Diffstat (limited to 'arch/arm/mach-omap2/prm-regbits-34xx.h')
-rw-r--r-- | arch/arm/mach-omap2/prm-regbits-34xx.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 64c087af6a8b..838b594d4e13 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
@@ -14,7 +14,7 @@ | |||
14 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H | 14 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H |
15 | 15 | ||
16 | 16 | ||
17 | #include "prm2xxx_3xxx.h" | 17 | #include "prm3xxx.h" |
18 | 18 | ||
19 | /* Shared register bits */ | 19 | /* Shared register bits */ |
20 | 20 | ||
@@ -509,15 +509,25 @@ | |||
509 | #define OMAP3430_RSTTIME1_MASK (0xff << 0) | 509 | #define OMAP3430_RSTTIME1_MASK (0xff << 0) |
510 | 510 | ||
511 | /* PRM_RSTST */ | 511 | /* PRM_RSTST */ |
512 | #define OMAP3430_ICECRUSHER_RST_SHIFT 10 | ||
512 | #define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) | 513 | #define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) |
514 | #define OMAP3430_ICEPICK_RST_SHIFT 9 | ||
513 | #define OMAP3430_ICEPICK_RST_MASK (1 << 9) | 515 | #define OMAP3430_ICEPICK_RST_MASK (1 << 9) |
516 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 | ||
514 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) | 517 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) |
518 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 | ||
515 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) | 519 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) |
520 | #define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 | ||
516 | #define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) | 521 | #define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) |
522 | #define OMAP3430_SECURE_WD_RST_SHIFT 5 | ||
517 | #define OMAP3430_SECURE_WD_RST_MASK (1 << 5) | 523 | #define OMAP3430_SECURE_WD_RST_MASK (1 << 5) |
524 | #define OMAP3430_MPU_WD_RST_SHIFT 4 | ||
518 | #define OMAP3430_MPU_WD_RST_MASK (1 << 4) | 525 | #define OMAP3430_MPU_WD_RST_MASK (1 << 4) |
526 | #define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 | ||
519 | #define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) | 527 | #define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) |
528 | #define OMAP3430_GLOBAL_SW_RST_SHIFT 1 | ||
520 | #define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) | 529 | #define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) |
530 | #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 | ||
521 | #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) | 531 | #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) |
522 | 532 | ||
523 | /* PRM_VOLTCTRL */ | 533 | /* PRM_VOLTCTRL */ |