diff options
Diffstat (limited to 'arch/arm/mach-omap2/prm-regbits-34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-34xx.h | 360 |
1 files changed, 180 insertions, 180 deletions
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 8f21bae6dc1c..7fd6023edf96 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
| @@ -35,10 +35,10 @@ | |||
| 35 | #define OMAP3430_ERRORGAIN_MASK (0xff << 16) | 35 | #define OMAP3430_ERRORGAIN_MASK (0xff << 16) |
| 36 | #define OMAP3430_INITVOLTAGE_SHIFT 8 | 36 | #define OMAP3430_INITVOLTAGE_SHIFT 8 |
| 37 | #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) | 37 | #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) |
| 38 | #define OMAP3430_TIMEOUTEN (1 << 3) | 38 | #define OMAP3430_TIMEOUTEN_MASK (1 << 3) |
| 39 | #define OMAP3430_INITVDD (1 << 2) | 39 | #define OMAP3430_INITVDD_MASK (1 << 2) |
| 40 | #define OMAP3430_FORCEUPDATE (1 << 1) | 40 | #define OMAP3430_FORCEUPDATE_MASK (1 << 1) |
| 41 | #define OMAP3430_VPENABLE (1 << 0) | 41 | #define OMAP3430_VPENABLE_MASK (1 << 0) |
| 42 | 42 | ||
| 43 | /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ | 43 | /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ |
| 44 | #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 | 44 | #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 |
| @@ -65,53 +65,53 @@ | |||
| 65 | #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) | 65 | #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) |
| 66 | 66 | ||
| 67 | /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ | 67 | /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ |
| 68 | #define OMAP3430_VPINIDLE (1 << 0) | 68 | #define OMAP3430_VPINIDLE_MASK (1 << 0) |
| 69 | 69 | ||
| 70 | /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ | 70 | /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ |
| 71 | #define OMAP3430_EN_PER_SHIFT 7 | 71 | #define OMAP3430_EN_PER_SHIFT 7 |
| 72 | #define OMAP3430_EN_PER_MASK (1 << 7) | 72 | #define OMAP3430_EN_PER_MASK (1 << 7) |
| 73 | 73 | ||
| 74 | /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ | 74 | /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ |
| 75 | #define OMAP3430_MEMORYCHANGE (1 << 3) | 75 | #define OMAP3430_MEMORYCHANGE_MASK (1 << 3) |
| 76 | 76 | ||
| 77 | /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ | 77 | /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ |
| 78 | #define OMAP3430_LOGICSTATEST (1 << 2) | 78 | #define OMAP3430_LOGICSTATEST_MASK (1 << 2) |
| 79 | 79 | ||
| 80 | /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ | 80 | /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ |
| 81 | #define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) | 81 | #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) |
| 82 | 82 | ||
| 83 | /* | 83 | /* |
| 84 | * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, | 84 | * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, |
| 85 | * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, | 85 | * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, |
| 86 | * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits | 86 | * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits |
| 87 | */ | 87 | */ |
| 88 | #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 | 88 | #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 |
| 89 | #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) | 89 | #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) |
| 90 | 90 | ||
| 91 | /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ | 91 | /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ |
| 92 | #define OMAP3430_WKUP_ST (1 << 0) | 92 | #define OMAP3430_WKUP_ST_MASK (1 << 0) |
| 93 | 93 | ||
| 94 | /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ | 94 | /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ |
| 95 | #define OMAP3430_WKUP_EN (1 << 0) | 95 | #define OMAP3430_WKUP_EN_MASK (1 << 0) |
| 96 | 96 | ||
| 97 | /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ | 97 | /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ |
| 98 | #define OMAP3430_GRPSEL_MMC2 (1 << 25) | 98 | #define OMAP3430_GRPSEL_MMC2_MASK (1 << 25) |
| 99 | #define OMAP3430_GRPSEL_MMC1 (1 << 24) | 99 | #define OMAP3430_GRPSEL_MMC1_MASK (1 << 24) |
| 100 | #define OMAP3430_GRPSEL_MCSPI4 (1 << 21) | 100 | #define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21) |
| 101 | #define OMAP3430_GRPSEL_MCSPI3 (1 << 20) | 101 | #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) |
| 102 | #define OMAP3430_GRPSEL_MCSPI2 (1 << 19) | 102 | #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) |
| 103 | #define OMAP3430_GRPSEL_MCSPI1 (1 << 18) | 103 | #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) |
| 104 | #define OMAP3430_GRPSEL_I2C3 (1 << 17) | 104 | #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) |
| 105 | #define OMAP3430_GRPSEL_I2C2 (1 << 16) | 105 | #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) |
| 106 | #define OMAP3430_GRPSEL_I2C1 (1 << 15) | 106 | #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) |
| 107 | #define OMAP3430_GRPSEL_UART2 (1 << 14) | 107 | #define OMAP3430_GRPSEL_UART2_MASK (1 << 14) |
| 108 | #define OMAP3430_GRPSEL_UART1 (1 << 13) | 108 | #define OMAP3430_GRPSEL_UART1_MASK (1 << 13) |
| 109 | #define OMAP3430_GRPSEL_GPT11 (1 << 12) | 109 | #define OMAP3430_GRPSEL_GPT11_MASK (1 << 12) |
| 110 | #define OMAP3430_GRPSEL_GPT10 (1 << 11) | 110 | #define OMAP3430_GRPSEL_GPT10_MASK (1 << 11) |
| 111 | #define OMAP3430_GRPSEL_MCBSP5 (1 << 10) | 111 | #define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10) |
| 112 | #define OMAP3430_GRPSEL_MCBSP1 (1 << 9) | 112 | #define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9) |
| 113 | #define OMAP3430_GRPSEL_HSOTGUSB (1 << 4) | 113 | #define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4) |
| 114 | #define OMAP3430_GRPSEL_D2D (1 << 3) | 114 | #define OMAP3430_GRPSEL_D2D_MASK (1 << 3) |
| 115 | 115 | ||
| 116 | /* | 116 | /* |
| 117 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, | 117 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, |
| @@ -119,49 +119,49 @@ | |||
| 119 | */ | 119 | */ |
| 120 | #define OMAP3430_MEMONSTATE_SHIFT 16 | 120 | #define OMAP3430_MEMONSTATE_SHIFT 16 |
| 121 | #define OMAP3430_MEMONSTATE_MASK (0x3 << 16) | 121 | #define OMAP3430_MEMONSTATE_MASK (0x3 << 16) |
| 122 | #define OMAP3430_MEMRETSTATE (1 << 8) | 122 | #define OMAP3430_MEMRETSTATE_MASK (1 << 8) |
| 123 | 123 | ||
| 124 | /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ | 124 | /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ |
| 125 | #define OMAP3430_GRPSEL_GPIO6 (1 << 17) | 125 | #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) |
| 126 | #define OMAP3430_GRPSEL_GPIO5 (1 << 16) | 126 | #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) |
| 127 | #define OMAP3430_GRPSEL_GPIO4 (1 << 15) | 127 | #define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15) |
| 128 | #define OMAP3430_GRPSEL_GPIO3 (1 << 14) | 128 | #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) |
| 129 | #define OMAP3430_GRPSEL_GPIO2 (1 << 13) | 129 | #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) |
| 130 | #define OMAP3430_GRPSEL_UART3 (1 << 11) | 130 | #define OMAP3430_GRPSEL_UART3_MASK (1 << 11) |
| 131 | #define OMAP3430_GRPSEL_GPT9 (1 << 10) | 131 | #define OMAP3430_GRPSEL_GPT9_MASK (1 << 10) |
| 132 | #define OMAP3430_GRPSEL_GPT8 (1 << 9) | 132 | #define OMAP3430_GRPSEL_GPT8_MASK (1 << 9) |
| 133 | #define OMAP3430_GRPSEL_GPT7 (1 << 8) | 133 | #define OMAP3430_GRPSEL_GPT7_MASK (1 << 8) |
| 134 | #define OMAP3430_GRPSEL_GPT6 (1 << 7) | 134 | #define OMAP3430_GRPSEL_GPT6_MASK (1 << 7) |
| 135 | #define OMAP3430_GRPSEL_GPT5 (1 << 6) | 135 | #define OMAP3430_GRPSEL_GPT5_MASK (1 << 6) |
| 136 | #define OMAP3430_GRPSEL_GPT4 (1 << 5) | 136 | #define OMAP3430_GRPSEL_GPT4_MASK (1 << 5) |
| 137 | #define OMAP3430_GRPSEL_GPT3 (1 << 4) | 137 | #define OMAP3430_GRPSEL_GPT3_MASK (1 << 4) |
| 138 | #define OMAP3430_GRPSEL_GPT2 (1 << 3) | 138 | #define OMAP3430_GRPSEL_GPT2_MASK (1 << 3) |
| 139 | #define OMAP3430_GRPSEL_MCBSP4 (1 << 2) | 139 | #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) |
| 140 | #define OMAP3430_GRPSEL_MCBSP3 (1 << 1) | 140 | #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) |
| 141 | #define OMAP3430_GRPSEL_MCBSP2 (1 << 0) | 141 | #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) |
| 142 | 142 | ||
| 143 | /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ | 143 | /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ |
| 144 | #define OMAP3430_GRPSEL_IO (1 << 8) | 144 | #define OMAP3430_GRPSEL_IO_MASK (1 << 8) |
| 145 | #define OMAP3430_GRPSEL_SR2 (1 << 7) | 145 | #define OMAP3430_GRPSEL_SR2_MASK (1 << 7) |
| 146 | #define OMAP3430_GRPSEL_SR1 (1 << 6) | 146 | #define OMAP3430_GRPSEL_SR1_MASK (1 << 6) |
| 147 | #define OMAP3430_GRPSEL_GPIO1 (1 << 3) | 147 | #define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) |
| 148 | #define OMAP3430_GRPSEL_GPT12 (1 << 1) | 148 | #define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) |
| 149 | #define OMAP3430_GRPSEL_GPT1 (1 << 0) | 149 | #define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) |
| 150 | 150 | ||
| 151 | /* Bits specific to each register */ | 151 | /* Bits specific to each register */ |
| 152 | 152 | ||
| 153 | /* RM_RSTCTRL_IVA2 */ | 153 | /* RM_RSTCTRL_IVA2 */ |
| 154 | #define OMAP3430_RST3_IVA2 (1 << 2) | 154 | #define OMAP3430_RST3_IVA2_MASK (1 << 2) |
| 155 | #define OMAP3430_RST2_IVA2 (1 << 1) | 155 | #define OMAP3430_RST2_IVA2_MASK (1 << 1) |
| 156 | #define OMAP3430_RST1_IVA2 (1 << 0) | 156 | #define OMAP3430_RST1_IVA2_MASK (1 << 0) |
| 157 | 157 | ||
| 158 | /* RM_RSTST_IVA2 specific bits */ | 158 | /* RM_RSTST_IVA2 specific bits */ |
| 159 | #define OMAP3430_EMULATION_VSEQ_RST (1 << 13) | 159 | #define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13) |
| 160 | #define OMAP3430_EMULATION_VHWA_RST (1 << 12) | 160 | #define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12) |
| 161 | #define OMAP3430_EMULATION_IVA2_RST (1 << 11) | 161 | #define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11) |
| 162 | #define OMAP3430_IVA2_SW_RST3 (1 << 10) | 162 | #define OMAP3430_IVA2_SW_RST3_MASK (1 << 10) |
| 163 | #define OMAP3430_IVA2_SW_RST2 (1 << 9) | 163 | #define OMAP3430_IVA2_SW_RST2_MASK (1 << 9) |
| 164 | #define OMAP3430_IVA2_SW_RST1 (1 << 8) | 164 | #define OMAP3430_IVA2_SW_RST1_MASK (1 << 8) |
| 165 | 165 | ||
| 166 | /* PM_WKDEP_IVA2 specific bits */ | 166 | /* PM_WKDEP_IVA2 specific bits */ |
| 167 | 167 | ||
| @@ -174,10 +174,10 @@ | |||
| 174 | #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) | 174 | #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) |
| 175 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 | 175 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 |
| 176 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) | 176 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) |
| 177 | #define OMAP3430_L2FLATMEMRETSTATE (1 << 11) | 177 | #define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) |
| 178 | #define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10) | 178 | #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) |
| 179 | #define OMAP3430_L1FLATMEMRETSTATE (1 << 9) | 179 | #define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) |
| 180 | #define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8) | 180 | #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) |
| 181 | 181 | ||
| 182 | /* PM_PWSTST_IVA2 specific bits */ | 182 | /* PM_PWSTST_IVA2 specific bits */ |
| 183 | #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 | 183 | #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 |
| @@ -200,12 +200,12 @@ | |||
| 200 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) | 200 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) |
| 201 | 201 | ||
| 202 | /* PRM_IRQSTATUS_IVA2 specific bits */ | 202 | /* PRM_IRQSTATUS_IVA2 specific bits */ |
| 203 | #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2) | 203 | #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2) |
| 204 | #define OMAP3430_FORCEWKUP_ST (1 << 1) | 204 | #define OMAP3430_FORCEWKUP_ST_MASK (1 << 1) |
| 205 | 205 | ||
| 206 | /* PRM_IRQENABLE_IVA2 specific bits */ | 206 | /* PRM_IRQENABLE_IVA2 specific bits */ |
| 207 | #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2) | 207 | #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2) |
| 208 | #define OMAP3430_FORCEWKUP_EN (1 << 1) | 208 | #define OMAP3430_FORCEWKUP_EN_MASK (1 << 1) |
| 209 | 209 | ||
| 210 | /* PRM_REVISION specific bits */ | 210 | /* PRM_REVISION specific bits */ |
| 211 | 211 | ||
| @@ -213,70 +213,70 @@ | |||
| 213 | 213 | ||
| 214 | /* PRM_IRQSTATUS_MPU specific bits */ | 214 | /* PRM_IRQSTATUS_MPU specific bits */ |
| 215 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 | 215 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 |
| 216 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25) | 216 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25) |
| 217 | #define OMAP3430_VC_TIMEOUTERR_ST (1 << 24) | 217 | #define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24) |
| 218 | #define OMAP3430_VC_RAERR_ST (1 << 23) | 218 | #define OMAP3430_VC_RAERR_ST_MASK (1 << 23) |
| 219 | #define OMAP3430_VC_SAERR_ST (1 << 22) | 219 | #define OMAP3430_VC_SAERR_ST_MASK (1 << 22) |
| 220 | #define OMAP3430_VP2_TRANXDONE_ST (1 << 21) | 220 | #define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) |
| 221 | #define OMAP3430_VP2_EQVALUE_ST (1 << 20) | 221 | #define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20) |
| 222 | #define OMAP3430_VP2_NOSMPSACK_ST (1 << 19) | 222 | #define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19) |
| 223 | #define OMAP3430_VP2_MAXVDD_ST (1 << 18) | 223 | #define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18) |
| 224 | #define OMAP3430_VP2_MINVDD_ST (1 << 17) | 224 | #define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17) |
| 225 | #define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16) | 225 | #define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16) |
| 226 | #define OMAP3430_VP1_TRANXDONE_ST (1 << 15) | 226 | #define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) |
| 227 | #define OMAP3430_VP1_EQVALUE_ST (1 << 14) | 227 | #define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14) |
| 228 | #define OMAP3430_VP1_NOSMPSACK_ST (1 << 13) | 228 | #define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13) |
| 229 | #define OMAP3430_VP1_MAXVDD_ST (1 << 12) | 229 | #define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12) |
| 230 | #define OMAP3430_VP1_MINVDD_ST (1 << 11) | 230 | #define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11) |
| 231 | #define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10) | 231 | #define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10) |
| 232 | #define OMAP3430_IO_ST (1 << 9) | 232 | #define OMAP3430_IO_ST_MASK (1 << 9) |
| 233 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8) | 233 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8) |
| 234 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 | 234 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 |
| 235 | #define OMAP3430_MPU_DPLL_ST (1 << 7) | 235 | #define OMAP3430_MPU_DPLL_ST_MASK (1 << 7) |
| 236 | #define OMAP3430_MPU_DPLL_ST_SHIFT 7 | 236 | #define OMAP3430_MPU_DPLL_ST_SHIFT 7 |
| 237 | #define OMAP3430_PERIPH_DPLL_ST (1 << 6) | 237 | #define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6) |
| 238 | #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 | 238 | #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 |
| 239 | #define OMAP3430_CORE_DPLL_ST (1 << 5) | 239 | #define OMAP3430_CORE_DPLL_ST_MASK (1 << 5) |
| 240 | #define OMAP3430_CORE_DPLL_ST_SHIFT 5 | 240 | #define OMAP3430_CORE_DPLL_ST_SHIFT 5 |
| 241 | #define OMAP3430_TRANSITION_ST (1 << 4) | 241 | #define OMAP3430_TRANSITION_ST_MASK (1 << 4) |
| 242 | #define OMAP3430_EVGENOFF_ST (1 << 3) | 242 | #define OMAP3430_EVGENOFF_ST_MASK (1 << 3) |
| 243 | #define OMAP3430_EVGENON_ST (1 << 2) | 243 | #define OMAP3430_EVGENON_ST_MASK (1 << 2) |
| 244 | #define OMAP3430_FS_USB_WKUP_ST (1 << 1) | 244 | #define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1) |
| 245 | 245 | ||
| 246 | /* PRM_IRQENABLE_MPU specific bits */ | 246 | /* PRM_IRQENABLE_MPU specific bits */ |
| 247 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 | 247 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 |
| 248 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25) | 248 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25) |
| 249 | #define OMAP3430_VC_TIMEOUTERR_EN (1 << 24) | 249 | #define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24) |
| 250 | #define OMAP3430_VC_RAERR_EN (1 << 23) | 250 | #define OMAP3430_VC_RAERR_EN_MASK (1 << 23) |
| 251 | #define OMAP3430_VC_SAERR_EN (1 << 22) | 251 | #define OMAP3430_VC_SAERR_EN_MASK (1 << 22) |
| 252 | #define OMAP3430_VP2_TRANXDONE_EN (1 << 21) | 252 | #define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21) |
| 253 | #define OMAP3430_VP2_EQVALUE_EN (1 << 20) | 253 | #define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20) |
| 254 | #define OMAP3430_VP2_NOSMPSACK_EN (1 << 19) | 254 | #define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19) |
| 255 | #define OMAP3430_VP2_MAXVDD_EN (1 << 18) | 255 | #define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18) |
| 256 | #define OMAP3430_VP2_MINVDD_EN (1 << 17) | 256 | #define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17) |
| 257 | #define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16) | 257 | #define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16) |
| 258 | #define OMAP3430_VP1_TRANXDONE_EN (1 << 15) | 258 | #define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15) |
| 259 | #define OMAP3430_VP1_EQVALUE_EN (1 << 14) | 259 | #define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14) |
| 260 | #define OMAP3430_VP1_NOSMPSACK_EN (1 << 13) | 260 | #define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13) |
| 261 | #define OMAP3430_VP1_MAXVDD_EN (1 << 12) | 261 | #define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12) |
| 262 | #define OMAP3430_VP1_MINVDD_EN (1 << 11) | 262 | #define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11) |
| 263 | #define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10) | 263 | #define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10) |
| 264 | #define OMAP3430_IO_EN (1 << 9) | 264 | #define OMAP3430_IO_EN_MASK (1 << 9) |
| 265 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8) | 265 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8) |
| 266 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 | 266 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 |
| 267 | #define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7) | 267 | #define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7) |
| 268 | #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 | 268 | #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 |
| 269 | #define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6) | 269 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6) |
| 270 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 | 270 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 |
| 271 | #define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5) | 271 | #define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5) |
| 272 | #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 | 272 | #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 |
| 273 | #define OMAP3430_TRANSITION_EN (1 << 4) | 273 | #define OMAP3430_TRANSITION_EN_MASK (1 << 4) |
| 274 | #define OMAP3430_EVGENOFF_EN (1 << 3) | 274 | #define OMAP3430_EVGENOFF_EN_MASK (1 << 3) |
| 275 | #define OMAP3430_EVGENON_EN (1 << 2) | 275 | #define OMAP3430_EVGENON_EN_MASK (1 << 2) |
| 276 | #define OMAP3430_FS_USB_WKUP_EN (1 << 1) | 276 | #define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1) |
| 277 | 277 | ||
| 278 | /* RM_RSTST_MPU specific bits */ | 278 | /* RM_RSTST_MPU specific bits */ |
| 279 | #define OMAP3430_EMULATION_MPU_RST (1 << 11) | 279 | #define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11) |
| 280 | 280 | ||
| 281 | /* PM_WKDEP_MPU specific bits */ | 281 | /* PM_WKDEP_MPU specific bits */ |
| 282 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 | 282 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 |
| @@ -289,7 +289,7 @@ | |||
| 289 | #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) | 289 | #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) |
| 290 | #define OMAP3430_ONLOADMODE_SHIFT 1 | 290 | #define OMAP3430_ONLOADMODE_SHIFT 1 |
| 291 | #define OMAP3430_ONLOADMODE_MASK (0x3 << 1) | 291 | #define OMAP3430_ONLOADMODE_MASK (0x3 << 1) |
| 292 | #define OMAP3430_ENABLE (1 << 0) | 292 | #define OMAP3430_ENABLE_MASK (1 << 0) |
| 293 | 293 | ||
| 294 | /* PM_EVGENONTIM_MPU */ | 294 | /* PM_EVGENONTIM_MPU */ |
| 295 | #define OMAP3430_ONTIMEVAL_SHIFT 0 | 295 | #define OMAP3430_ONTIMEVAL_SHIFT 0 |
| @@ -302,32 +302,32 @@ | |||
| 302 | /* PM_PWSTCTRL_MPU specific bits */ | 302 | /* PM_PWSTCTRL_MPU specific bits */ |
| 303 | #define OMAP3430_L2CACHEONSTATE_SHIFT 16 | 303 | #define OMAP3430_L2CACHEONSTATE_SHIFT 16 |
| 304 | #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) | 304 | #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) |
| 305 | #define OMAP3430_L2CACHERETSTATE (1 << 8) | 305 | #define OMAP3430_L2CACHERETSTATE_MASK (1 << 8) |
| 306 | #define OMAP3430_LOGICL1CACHERETSTATE (1 << 2) | 306 | #define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2) |
| 307 | 307 | ||
| 308 | /* PM_PWSTST_MPU specific bits */ | 308 | /* PM_PWSTST_MPU specific bits */ |
| 309 | #define OMAP3430_L2CACHESTATEST_SHIFT 6 | 309 | #define OMAP3430_L2CACHESTATEST_SHIFT 6 |
| 310 | #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) | 310 | #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) |
| 311 | #define OMAP3430_LOGICL1CACHESTATEST (1 << 2) | 311 | #define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2) |
| 312 | 312 | ||
| 313 | /* PM_PREPWSTST_MPU specific bits */ | 313 | /* PM_PREPWSTST_MPU specific bits */ |
| 314 | #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 | 314 | #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 |
| 315 | #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) | 315 | #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) |
| 316 | #define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2) | 316 | #define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2) |
| 317 | 317 | ||
| 318 | /* RM_RSTCTRL_CORE */ | 318 | /* RM_RSTCTRL_CORE */ |
| 319 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1) | 319 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) |
| 320 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0) | 320 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) |
| 321 | 321 | ||
| 322 | /* RM_RSTST_CORE specific bits */ | 322 | /* RM_RSTST_CORE specific bits */ |
| 323 | #define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10) | 323 | #define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10) |
| 324 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9) | 324 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9) |
| 325 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8) | 325 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8) |
| 326 | 326 | ||
| 327 | /* PM_WKEN1_CORE specific bits */ | 327 | /* PM_WKEN1_CORE specific bits */ |
| 328 | 328 | ||
| 329 | /* PM_MPUGRPSEL1_CORE specific bits */ | 329 | /* PM_MPUGRPSEL1_CORE specific bits */ |
| 330 | #define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5) | 330 | #define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5) |
| 331 | 331 | ||
| 332 | /* PM_IVA2GRPSEL1_CORE specific bits */ | 332 | /* PM_IVA2GRPSEL1_CORE specific bits */ |
| 333 | 333 | ||
| @@ -338,8 +338,8 @@ | |||
| 338 | #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) | 338 | #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) |
| 339 | #define OMAP3430_MEM1ONSTATE_SHIFT 16 | 339 | #define OMAP3430_MEM1ONSTATE_SHIFT 16 |
| 340 | #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) | 340 | #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) |
| 341 | #define OMAP3430_MEM2RETSTATE (1 << 9) | 341 | #define OMAP3430_MEM2RETSTATE_MASK (1 << 9) |
| 342 | #define OMAP3430_MEM1RETSTATE (1 << 8) | 342 | #define OMAP3430_MEM1RETSTATE_MASK (1 << 8) |
| 343 | 343 | ||
| 344 | /* PM_PWSTST_CORE specific bits */ | 344 | /* PM_PWSTST_CORE specific bits */ |
| 345 | #define OMAP3430_MEM2STATEST_SHIFT 6 | 345 | #define OMAP3430_MEM2STATEST_SHIFT 6 |
| @@ -356,7 +356,7 @@ | |||
| 356 | /* RM_RSTST_GFX specific bits */ | 356 | /* RM_RSTST_GFX specific bits */ |
| 357 | 357 | ||
| 358 | /* PM_WKDEP_GFX specific bits */ | 358 | /* PM_WKDEP_GFX specific bits */ |
| 359 | #define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2) | 359 | #define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2) |
| 360 | 360 | ||
| 361 | /* PM_PWSTCTRL_GFX specific bits */ | 361 | /* PM_PWSTCTRL_GFX specific bits */ |
| 362 | 362 | ||
| @@ -365,33 +365,33 @@ | |||
| 365 | /* PM_PREPWSTST_GFX specific bits */ | 365 | /* PM_PREPWSTST_GFX specific bits */ |
| 366 | 366 | ||
| 367 | /* PM_WKEN_WKUP specific bits */ | 367 | /* PM_WKEN_WKUP specific bits */ |
| 368 | #define OMAP3430_EN_IO_CHAIN (1 << 16) | 368 | #define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) |
| 369 | #define OMAP3430_EN_IO (1 << 8) | 369 | #define OMAP3430_EN_IO_MASK (1 << 8) |
| 370 | #define OMAP3430_EN_GPIO1 (1 << 3) | 370 | #define OMAP3430_EN_GPIO1_MASK (1 << 3) |
| 371 | 371 | ||
| 372 | /* PM_MPUGRPSEL_WKUP specific bits */ | 372 | /* PM_MPUGRPSEL_WKUP specific bits */ |
| 373 | 373 | ||
| 374 | /* PM_IVA2GRPSEL_WKUP specific bits */ | 374 | /* PM_IVA2GRPSEL_WKUP specific bits */ |
| 375 | 375 | ||
| 376 | /* PM_WKST_WKUP specific bits */ | 376 | /* PM_WKST_WKUP specific bits */ |
| 377 | #define OMAP3430_ST_IO_CHAIN (1 << 16) | 377 | #define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) |
| 378 | #define OMAP3430_ST_IO (1 << 8) | 378 | #define OMAP3430_ST_IO_MASK (1 << 8) |
| 379 | 379 | ||
| 380 | /* PRM_CLKSEL */ | 380 | /* PRM_CLKSEL */ |
| 381 | #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 | 381 | #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 |
| 382 | #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) | 382 | #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) |
| 383 | 383 | ||
| 384 | /* PRM_CLKOUT_CTRL */ | 384 | /* PRM_CLKOUT_CTRL */ |
| 385 | #define OMAP3430_CLKOUT_EN (1 << 7) | 385 | #define OMAP3430_CLKOUT_EN_MASK (1 << 7) |
| 386 | #define OMAP3430_CLKOUT_EN_SHIFT 7 | 386 | #define OMAP3430_CLKOUT_EN_SHIFT 7 |
| 387 | 387 | ||
| 388 | /* RM_RSTST_DSS specific bits */ | 388 | /* RM_RSTST_DSS specific bits */ |
| 389 | 389 | ||
| 390 | /* PM_WKEN_DSS */ | 390 | /* PM_WKEN_DSS */ |
| 391 | #define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0) | 391 | #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) |
| 392 | 392 | ||
| 393 | /* PM_WKDEP_DSS specific bits */ | 393 | /* PM_WKDEP_DSS specific bits */ |
| 394 | #define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2) | 394 | #define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2) |
| 395 | 395 | ||
| 396 | /* PM_PWSTCTRL_DSS specific bits */ | 396 | /* PM_PWSTCTRL_DSS specific bits */ |
| 397 | 397 | ||
| @@ -402,7 +402,7 @@ | |||
| 402 | /* RM_RSTST_CAM specific bits */ | 402 | /* RM_RSTST_CAM specific bits */ |
| 403 | 403 | ||
| 404 | /* PM_WKDEP_CAM specific bits */ | 404 | /* PM_WKDEP_CAM specific bits */ |
| 405 | #define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2) | 405 | #define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2) |
| 406 | 406 | ||
| 407 | /* PM_PWSTCTRL_CAM specific bits */ | 407 | /* PM_PWSTCTRL_CAM specific bits */ |
| 408 | 408 | ||
| @@ -424,7 +424,7 @@ | |||
| 424 | /* PM_WKST_PER specific bits */ | 424 | /* PM_WKST_PER specific bits */ |
| 425 | 425 | ||
| 426 | /* PM_WKDEP_PER specific bits */ | 426 | /* PM_WKDEP_PER specific bits */ |
| 427 | #define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2) | 427 | #define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2) |
| 428 | 428 | ||
| 429 | /* PM_PWSTCTRL_PER specific bits */ | 429 | /* PM_PWSTCTRL_PER specific bits */ |
| 430 | 430 | ||
| @@ -467,26 +467,26 @@ | |||
| 467 | /* PRM_VC_CMD_VAL_1 specific bits */ | 467 | /* PRM_VC_CMD_VAL_1 specific bits */ |
| 468 | 468 | ||
| 469 | /* PRM_VC_CH_CONF */ | 469 | /* PRM_VC_CH_CONF */ |
| 470 | #define OMAP3430_CMD1 (1 << 20) | 470 | #define OMAP3430_CMD1_MASK (1 << 20) |
| 471 | #define OMAP3430_RACEN1 (1 << 19) | 471 | #define OMAP3430_RACEN1_MASK (1 << 19) |
| 472 | #define OMAP3430_RAC1 (1 << 18) | 472 | #define OMAP3430_RAC1_MASK (1 << 18) |
| 473 | #define OMAP3430_RAV1 (1 << 17) | 473 | #define OMAP3430_RAV1_MASK (1 << 17) |
| 474 | #define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16) | 474 | #define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16) |
| 475 | #define OMAP3430_CMD0 (1 << 4) | 475 | #define OMAP3430_CMD0_MASK (1 << 4) |
| 476 | #define OMAP3430_RACEN0 (1 << 3) | 476 | #define OMAP3430_RACEN0_MASK (1 << 3) |
| 477 | #define OMAP3430_RAC0 (1 << 2) | 477 | #define OMAP3430_RAC0_MASK (1 << 2) |
| 478 | #define OMAP3430_RAV0 (1 << 1) | 478 | #define OMAP3430_RAV0_MASK (1 << 1) |
| 479 | #define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0) | 479 | #define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0) |
| 480 | 480 | ||
| 481 | /* PRM_VC_I2C_CFG */ | 481 | /* PRM_VC_I2C_CFG */ |
| 482 | #define OMAP3430_HSMASTER (1 << 5) | 482 | #define OMAP3430_HSMASTER_MASK (1 << 5) |
| 483 | #define OMAP3430_SREN (1 << 4) | 483 | #define OMAP3430_SREN_MASK (1 << 4) |
| 484 | #define OMAP3430_HSEN (1 << 3) | 484 | #define OMAP3430_HSEN_MASK (1 << 3) |
| 485 | #define OMAP3430_MCODE_SHIFT 0 | 485 | #define OMAP3430_MCODE_SHIFT 0 |
| 486 | #define OMAP3430_MCODE_MASK (0x7 << 0) | 486 | #define OMAP3430_MCODE_MASK (0x7 << 0) |
| 487 | 487 | ||
| 488 | /* PRM_VC_BYPASS_VAL */ | 488 | /* PRM_VC_BYPASS_VAL */ |
| 489 | #define OMAP3430_VALID (1 << 24) | 489 | #define OMAP3430_VALID_MASK (1 << 24) |
| 490 | #define OMAP3430_DATA_SHIFT 16 | 490 | #define OMAP3430_DATA_SHIFT 16 |
| 491 | #define OMAP3430_DATA_MASK (0xff << 16) | 491 | #define OMAP3430_DATA_MASK (0xff << 16) |
| 492 | #define OMAP3430_REGADDR_SHIFT 8 | 492 | #define OMAP3430_REGADDR_SHIFT 8 |
| @@ -495,8 +495,8 @@ | |||
| 495 | #define OMAP3430_SLAVEADDR_MASK (0x7f << 0) | 495 | #define OMAP3430_SLAVEADDR_MASK (0x7f << 0) |
| 496 | 496 | ||
| 497 | /* PRM_RSTCTRL */ | 497 | /* PRM_RSTCTRL */ |
| 498 | #define OMAP3430_RST_DPLL3 (1 << 2) | 498 | #define OMAP3430_RST_DPLL3_MASK (1 << 2) |
| 499 | #define OMAP3430_RST_GS (1 << 1) | 499 | #define OMAP3430_RST_GS_MASK (1 << 1) |
| 500 | 500 | ||
| 501 | /* PRM_RSTTIME */ | 501 | /* PRM_RSTTIME */ |
| 502 | #define OMAP3430_RSTTIME2_SHIFT 8 | 502 | #define OMAP3430_RSTTIME2_SHIFT 8 |
| @@ -505,23 +505,23 @@ | |||
| 505 | #define OMAP3430_RSTTIME1_MASK (0xff << 0) | 505 | #define OMAP3430_RSTTIME1_MASK (0xff << 0) |
| 506 | 506 | ||
| 507 | /* PRM_RSTST */ | 507 | /* PRM_RSTST */ |
| 508 | #define OMAP3430_ICECRUSHER_RST (1 << 10) | 508 | #define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) |
| 509 | #define OMAP3430_ICEPICK_RST (1 << 9) | 509 | #define OMAP3430_ICEPICK_RST_MASK (1 << 9) |
| 510 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8) | 510 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) |
| 511 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7) | 511 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) |
| 512 | #define OMAP3430_EXTERNAL_WARM_RST (1 << 6) | 512 | #define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) |
| 513 | #define OMAP3430_SECURE_WD_RST (1 << 5) | 513 | #define OMAP3430_SECURE_WD_RST_MASK (1 << 5) |
| 514 | #define OMAP3430_MPU_WD_RST (1 << 4) | 514 | #define OMAP3430_MPU_WD_RST_MASK (1 << 4) |
| 515 | #define OMAP3430_SECURITY_VIOL_RST (1 << 3) | 515 | #define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) |
| 516 | #define OMAP3430_GLOBAL_SW_RST (1 << 1) | 516 | #define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) |
| 517 | #define OMAP3430_GLOBAL_COLD_RST (1 << 0) | 517 | #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) |
| 518 | 518 | ||
| 519 | /* PRM_VOLTCTRL */ | 519 | /* PRM_VOLTCTRL */ |
| 520 | #define OMAP3430_SEL_VMODE (1 << 4) | 520 | #define OMAP3430_SEL_VMODE_MASK (1 << 4) |
| 521 | #define OMAP3430_SEL_OFF (1 << 3) | 521 | #define OMAP3430_SEL_OFF_MASK (1 << 3) |
| 522 | #define OMAP3430_AUTO_OFF (1 << 2) | 522 | #define OMAP3430_AUTO_OFF_MASK (1 << 2) |
| 523 | #define OMAP3430_AUTO_RET (1 << 1) | 523 | #define OMAP3430_AUTO_RET_MASK (1 << 1) |
| 524 | #define OMAP3430_AUTO_SLEEP (1 << 0) | 524 | #define OMAP3430_AUTO_SLEEP_MASK (1 << 0) |
| 525 | 525 | ||
| 526 | /* PRM_SRAM_PCHARGE */ | 526 | /* PRM_SRAM_PCHARGE */ |
| 527 | #define OMAP3430_PCHARGE_TIME_SHIFT 0 | 527 | #define OMAP3430_PCHARGE_TIME_SHIFT 0 |
| @@ -550,10 +550,10 @@ | |||
| 550 | #define OMAP3430_SETUP_TIME_MASK (0xffff << 0) | 550 | #define OMAP3430_SETUP_TIME_MASK (0xffff << 0) |
| 551 | 551 | ||
| 552 | /* PRM_POLCTRL */ | 552 | /* PRM_POLCTRL */ |
| 553 | #define OMAP3430_OFFMODE_POL (1 << 3) | 553 | #define OMAP3430_OFFMODE_POL_MASK (1 << 3) |
| 554 | #define OMAP3430_CLKOUT_POL (1 << 2) | 554 | #define OMAP3430_CLKOUT_POL_MASK (1 << 2) |
| 555 | #define OMAP3430_CLKREQ_POL (1 << 1) | 555 | #define OMAP3430_CLKREQ_POL_MASK (1 << 1) |
| 556 | #define OMAP3430_EXTVOL_POL (1 << 0) | 556 | #define OMAP3430_EXTVOL_POL_MASK (1 << 0) |
| 557 | 557 | ||
| 558 | /* PRM_VOLTSETUP2 */ | 558 | /* PRM_VOLTSETUP2 */ |
| 559 | #define OMAP3430_OFFMODESETUPTIME_SHIFT 0 | 559 | #define OMAP3430_OFFMODESETUPTIME_SHIFT 0 |