1 files changed, 60 insertions, 60 deletions
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 4002051c20b9..0b188ffa710e 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -19,14 +19,14 @@
 /* Bits shared between registers */
 /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
-#define OMAP24XX_VOLTTRANS_ST                           (1 << 2)
+#define OMAP24XX_VOLTTRANS_ST_MASK                      (1 << 2)
-#define OMAP24XX_WKUP2_ST                               (1 << 1)
+#define OMAP24XX_WKUP2_ST_MASK                          (1 << 1)
-#define OMAP24XX_WKUP1_ST                               (1 << 0)
+#define OMAP24XX_WKUP1_ST_MASK                          (1 << 0)
 /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
-#define OMAP24XX_VOLTTRANS_EN                           (1 << 2)
+#define OMAP24XX_VOLTTRANS_EN_MASK                      (1 << 2)
-#define OMAP24XX_WKUP2_EN                               (1 << 1)
+#define OMAP24XX_WKUP2_EN_MASK                          (1 << 1)
-#define OMAP24XX_WKUP1_EN                               (1 << 0)
+#define OMAP24XX_WKUP1_EN_MASK                          (1 << 0)
 /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
 #define OMAP24XX_EN_MPU_SHIFT                           1
@@ -40,16 +40,16 @@
 */
 #define OMAP24XX_MEMONSTATE_SHIFT                       10
 #define OMAP24XX_MEMONSTATE_MASK                        (0x3 << 10)
-#define OMAP24XX_MEMRETSTATE                            (1 << 3)
+#define OMAP24XX_MEMRETSTATE_MASK                       (1 << 3)
 /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
-#define OMAP24XX_FORCESTATE                             (1 << 18)
+#define OMAP24XX_FORCESTATE_MASK                        (1 << 18)
 /*
 * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
 * PM_PWSTST_MDM shared bits
 */
-#define OMAP24XX_CLKACTIVITY                            (1 << 19)
+#define OMAP24XX_CLKACTIVITY_MASK                       (1 << 19)
 /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
 #define OMAP24XX_LASTSTATEENTERED_SHIFT                 4
@@ -71,26 +71,26 @@
 #define OMAP24XX_REV_MASK                               (0xff << 0)
 /* PRCM_SYSCONFIG */
-#define OMAP24XX_AUTOIDLE                               (1 << 0)
+#define OMAP24XX_AUTOIDLE_MASK                          (1 << 0)
 /* PRCM_IRQSTATUS_MPU specific bits */
-#define OMAP2430_DPLL_RECAL_ST                          (1 << 6)
+#define OMAP2430_DPLL_RECAL_ST_MASK                     (1 << 6)
-#define OMAP24XX_TRANSITION_ST                          (1 << 5)
+#define OMAP24XX_TRANSITION_ST_MASK                     (1 << 5)
-#define OMAP24XX_EVGENOFF_ST                            (1 << 4)
+#define OMAP24XX_EVGENOFF_ST_MASK                       (1 << 4)
-#define OMAP24XX_EVGENON_ST                             (1 << 3)
+#define OMAP24XX_EVGENON_ST_MASK                        (1 << 3)
 /* PRCM_IRQENABLE_MPU specific bits */
-#define OMAP2430_DPLL_RECAL_EN                          (1 << 6)
+#define OMAP2430_DPLL_RECAL_EN_MASK                     (1 << 6)
-#define OMAP24XX_TRANSITION_EN                          (1 << 5)
+#define OMAP24XX_TRANSITION_EN_MASK                     (1 << 5)
-#define OMAP24XX_EVGENOFF_EN                            (1 << 4)
+#define OMAP24XX_EVGENOFF_EN_MASK                       (1 << 4)
-#define OMAP24XX_EVGENON_EN                             (1 << 3)
+#define OMAP24XX_EVGENON_EN_MASK                        (1 << 3)
 /* PRCM_VOLTCTRL */
-#define OMAP24XX_AUTO_EXTVOLT                           (1 << 15)
+#define OMAP24XX_AUTO_EXTVOLT_MASK                      (1 << 15)
-#define OMAP24XX_FORCE_EXTVOLT                          (1 << 14)
+#define OMAP24XX_FORCE_EXTVOLT_MASK                     (1 << 14)
 #define OMAP24XX_SETOFF_LEVEL_SHIFT                     12
 #define OMAP24XX_SETOFF_LEVEL_MASK                      (0x3 << 12)
-#define OMAP24XX_MEMRETCTRL                             (1 << 8)
+#define OMAP24XX_MEMRETCTRL_MASK                        (1 << 8)
 #define OMAP24XX_SETRET_LEVEL_SHIFT                     6
 #define OMAP24XX_SETRET_LEVEL_MASK                      (0x3 << 6)
 #define OMAP24XX_VOLT_LEVEL_SHIFT                       0
@@ -104,13 +104,13 @@
 /* PRCM_CLKOUT_CTRL */
 #define OMAP2420_CLKOUT2_EN_SHIFT                       15
-#define OMAP2420_CLKOUT2_EN                             (1 << 15)
+#define OMAP2420_CLKOUT2_EN_MASK                        (1 << 15)
 #define OMAP2420_CLKOUT2_DIV_SHIFT                      11
 #define OMAP2420_CLKOUT2_DIV_MASK                       (0x7 << 11)
 #define OMAP2420_CLKOUT2_SOURCE_SHIFT                   8
 #define OMAP2420_CLKOUT2_SOURCE_MASK                    (0x3 << 8)
 #define OMAP24XX_CLKOUT_EN_SHIFT                        7
-#define OMAP24XX_CLKOUT_EN                              (1 << 7)
+#define OMAP24XX_CLKOUT_EN_MASK                         (1 << 7)
 #define OMAP24XX_CLKOUT_DIV_SHIFT                       3
 #define OMAP24XX_CLKOUT_DIV_MASK                        (0x7 << 3)
 #define OMAP24XX_CLKOUT_SOURCE_SHIFT                    0
@@ -118,25 +118,25 @@
 /* PRCM_CLKEMUL_CTRL */
 #define OMAP24XX_EMULATION_EN_SHIFT                     0
-#define OMAP24XX_EMULATION_EN                           (1 << 0)
+#define OMAP24XX_EMULATION_EN_MASK                      (1 << 0)
 /* PRCM_CLKCFG_CTRL */
-#define OMAP24XX_VALID_CONFIG                           (1 << 0)
+#define OMAP24XX_VALID_CONFIG_MASK                      (1 << 0)
 /* PRCM_CLKCFG_STATUS */
-#define OMAP24XX_CONFIG_STATUS                          (1 << 0)
+#define OMAP24XX_CONFIG_STATUS_MASK                     (1 << 0)
 /* PRCM_VOLTSETUP specific bits */
 /* PRCM_CLKSSETUP specific bits */
 /* PRCM_POLCTRL */
-#define OMAP2420_CLKOUT2_POL                            (1 << 10)
+#define OMAP2420_CLKOUT2_POL_MASK                       (1 << 10)
-#define OMAP24XX_CLKOUT_POL                             (1 << 9)
+#define OMAP24XX_CLKOUT_POL_MASK                        (1 << 9)
-#define OMAP24XX_CLKREQ_POL                             (1 << 8)
+#define OMAP24XX_CLKREQ_POL_MASK                        (1 << 8)
-#define OMAP2430_USE_POWEROK                            (1 << 2)
+#define OMAP2430_USE_POWEROK_MASK                       (1 << 2)
-#define OMAP2430_POWEROK_POL                            (1 << 1)
+#define OMAP2430_POWEROK_POL_MASK                       (1 << 1)
-#define OMAP24XX_EXTVOL_POL                             (1 << 0)
+#define OMAP24XX_EXTVOL_POL_MASK                        (1 << 0)
 /* RM_RSTST_MPU specific bits */
 /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
@@ -154,7 +154,7 @@
 /* PM_EVEGENOFFTIM_MPU specific bits */
 /* PM_PWSTCTRL_MPU specific bits */
-#define OMAP2430_FORCESTATE                             (1 << 18)
+#define OMAP2430_FORCESTATE_MASK                        (1 << 18)
 /* PM_PWSTST_MPU specific bits */
 /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
@@ -168,21 +168,21 @@
 /* PM_WKST2_CORE specific bits */
 /* PM_WKDEP_CORE specific bits*/
-#define OMAP2430_PM_WKDEP_CORE_EN_MDM                   (1 << 5)
+#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK              (1 << 5)
-#define OMAP24XX_PM_WKDEP_CORE_EN_GFX                   (1 << 3)
+#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK              (1 << 3)
-#define OMAP24XX_PM_WKDEP_CORE_EN_DSP                   (1 << 2)
+#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK              (1 << 2)
 /* PM_PWSTCTRL_CORE specific bits */
-#define OMAP24XX_MEMORYCHANGE                           (1 << 20)
+#define OMAP24XX_MEMORYCHANGE_MASK                      (1 << 20)
 #define OMAP24XX_MEM3ONSTATE_SHIFT                      14
 #define OMAP24XX_MEM3ONSTATE_MASK                       (0x3 << 14)
 #define OMAP24XX_MEM2ONSTATE_SHIFT                      12
 #define OMAP24XX_MEM2ONSTATE_MASK                       (0x3 << 12)
 #define OMAP24XX_MEM1ONSTATE_SHIFT                      10
 #define OMAP24XX_MEM1ONSTATE_MASK                       (0x3 << 10)
-#define OMAP24XX_MEM3RETSTATE                           (1 << 5)
+#define OMAP24XX_MEM3RETSTATE_MASK                      (1 << 5)
-#define OMAP24XX_MEM2RETSTATE                           (1 << 4)
+#define OMAP24XX_MEM2RETSTATE_MASK                      (1 << 4)
-#define OMAP24XX_MEM1RETSTATE                           (1 << 3)
+#define OMAP24XX_MEM1RETSTATE_MASK                      (1 << 3)
 /* PM_PWSTST_CORE specific bits */
 #define OMAP24XX_MEM3STATEST_SHIFT                      14
@@ -193,10 +193,10 @@
 #define OMAP24XX_MEM1STATEST_MASK                       (0x3 << 10)
 /* RM_RSTCTRL_GFX */
-#define OMAP24XX_GFX_RST                                (1 << 0)
+#define OMAP24XX_GFX_RST_MASK                           (1 << 0)
 /* RM_RSTST_GFX specific bits */
-#define OMAP24XX_GFX_SW_RST                             (1 << 4)
+#define OMAP24XX_GFX_SW_RST_MASK                        (1 << 4)
 /* PM_PWSTCTRL_GFX specific bits */
@@ -209,25 +209,25 @@
 /* RM_RSTST_WKUP specific bits */
 /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
-#define OMAP24XX_EXTWMPU_RST                            (1 << 6)
+#define OMAP24XX_EXTWMPU_RST_MASK                       (1 << 6)
-#define OMAP24XX_SECU_WD_RST                            (1 << 5)
+#define OMAP24XX_SECU_WD_RST_MASK                       (1 << 5)
-#define OMAP24XX_MPU_WD_RST                             (1 << 4)
+#define OMAP24XX_MPU_WD_RST_MASK                        (1 << 4)
-#define OMAP24XX_SECU_VIOL_RST                          (1 << 3)
+#define OMAP24XX_SECU_VIOL_RST_MASK                     (1 << 3)
 /* PM_WKEN_WKUP specific bits */
 /* PM_WKST_WKUP specific bits */
 /* RM_RSTCTRL_DSP */
-#define OMAP2420_RST_IVA                                (1 << 8)
+#define OMAP2420_RST_IVA_MASK                           (1 << 8)
-#define OMAP24XX_RST2_DSP                               (1 << 1)
+#define OMAP24XX_RST2_DSP_MASK                          (1 << 1)
-#define OMAP24XX_RST1_DSP                               (1 << 0)
+#define OMAP24XX_RST1_DSP_MASK                          (1 << 0)
 /* RM_RSTST_DSP specific bits */
 /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
-#define OMAP2420_IVA_SW_RST                             (1 << 8)
+#define OMAP2420_IVA_SW_RST_MASK                        (1 << 8)
-#define OMAP24XX_DSP_SW_RST2                            (1 << 5)
+#define OMAP24XX_DSP_SW_RST2_MASK                       (1 << 5)
-#define OMAP24XX_DSP_SW_RST1                            (1 << 4)
+#define OMAP24XX_DSP_SW_RST1_MASK                       (1 << 4)
 /* PM_WKDEP_DSP specific bits */
@@ -235,7 +235,7 @@
 /* 2430 only: MEMONSTATE, MEMRETSTATE */
 #define OMAP2420_MEMIONSTATE_SHIFT                      12
 #define OMAP2420_MEMIONSTATE_MASK                       (0x3 << 12)
-#define OMAP2420_MEMIRETSTATE                           (1 << 4)
+#define OMAP2420_MEMIRETSTATE_MASK                      (1 << 4)
 /* PM_PWSTST_DSP specific bits */
 /* MEMSTATEST is 2430 only */
@@ -248,18 +248,18 @@
 /* RM_RSTCTRL_MDM */
 /* 2430 only */
-#define OMAP2430_PWRON1_MDM                             (1 << 1)
+#define OMAP2430_PWRON1_MDM_MASK                        (1 << 1)
-#define OMAP2430_RST1_MDM                               (1 << 0)
+#define OMAP2430_RST1_MDM_MASK                          (1 << 0)
 /* RM_RSTST_MDM specific bits */
 /* 2430 only */
-#define OMAP2430_MDM_SECU_VIOL                          (1 << 6)
+#define OMAP2430_MDM_SECU_VIOL_MASK                     (1 << 6)
-#define OMAP2430_MDM_SW_PWRON1                          (1 << 5)
+#define OMAP2430_MDM_SW_PWRON1_MASK                     (1 << 5)
-#define OMAP2430_MDM_SW_RST1                            (1 << 4)
+#define OMAP2430_MDM_SW_RST1_MASK                       (1 << 4)
 /* PM_WKEN_MDM */
 /* 2430 only */
-#define OMAP2430_PM_WKEN_MDM_EN_MDM                     (1 << 0)
+#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK                (1 << 0)
 /* PM_WKST_MDM specific bits */
 /* 2430 only */
@@ -269,7 +269,7 @@
 /* PM_PWSTCTRL_MDM specific bits */
 /* 2430 only */
-#define OMAP2430_KILLDOMAINWKUP                         (1 << 19)
+#define OMAP2430_KILLDOMAINWKUP_MASK                    (1 << 19)
 /* PM_PWSTST_MDM specific bits */
 /* 2430 only */

diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 4002051c20b9..0b188ffa710e 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -19,14 +19,14 @@
19	/* Bits shared between registers */	19	/* Bits shared between registers */
20		20
21	/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */	21	/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
22	#define OMAP24XX_VOLTTRANS_ST (1 << 2)	22	#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2)
23	#define OMAP24XX_WKUP2_ST (1 << 1)	23	#define OMAP24XX_WKUP2_ST_MASK (1 << 1)
24	#define OMAP24XX_WKUP1_ST (1 << 0)	24	#define OMAP24XX_WKUP1_ST_MASK (1 << 0)
25		25
26	/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */	26	/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
27	#define OMAP24XX_VOLTTRANS_EN (1 << 2)	27	#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2)
28	#define OMAP24XX_WKUP2_EN (1 << 1)	28	#define OMAP24XX_WKUP2_EN_MASK (1 << 1)
29	#define OMAP24XX_WKUP1_EN (1 << 0)	29	#define OMAP24XX_WKUP1_EN_MASK (1 << 0)
30		30
31	/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */	31	/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
32	#define OMAP24XX_EN_MPU_SHIFT 1	32	#define OMAP24XX_EN_MPU_SHIFT 1
@@ -40,16 +40,16 @@
40	*/	40	*/
41	#define OMAP24XX_MEMONSTATE_SHIFT 10	41	#define OMAP24XX_MEMONSTATE_SHIFT 10
42	#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)	42	#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
43	#define OMAP24XX_MEMRETSTATE (1 << 3)	43	#define OMAP24XX_MEMRETSTATE_MASK (1 << 3)
44		44
45	/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */	45	/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
46	#define OMAP24XX_FORCESTATE (1 << 18)	46	#define OMAP24XX_FORCESTATE_MASK (1 << 18)
47		47
48	/*	48	/*
49	* PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,	49	* PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
50	* PM_PWSTST_MDM shared bits	50	* PM_PWSTST_MDM shared bits
51	*/	51	*/
52	#define OMAP24XX_CLKACTIVITY (1 << 19)	52	#define OMAP24XX_CLKACTIVITY_MASK (1 << 19)
53		53
54	/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */	54	/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
55	#define OMAP24XX_LASTSTATEENTERED_SHIFT 4	55	#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
@@ -71,26 +71,26 @@
71	#define OMAP24XX_REV_MASK (0xff << 0)	71	#define OMAP24XX_REV_MASK (0xff << 0)
72		72
73	/* PRCM_SYSCONFIG */	73	/* PRCM_SYSCONFIG */
74	#define OMAP24XX_AUTOIDLE (1 << 0)	74	#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
75		75
76	/* PRCM_IRQSTATUS_MPU specific bits */	76	/* PRCM_IRQSTATUS_MPU specific bits */
77	#define OMAP2430_DPLL_RECAL_ST (1 << 6)	77	#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6)
78	#define OMAP24XX_TRANSITION_ST (1 << 5)	78	#define OMAP24XX_TRANSITION_ST_MASK (1 << 5)
79	#define OMAP24XX_EVGENOFF_ST (1 << 4)	79	#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4)
80	#define OMAP24XX_EVGENON_ST (1 << 3)	80	#define OMAP24XX_EVGENON_ST_MASK (1 << 3)
81		81
82	/* PRCM_IRQENABLE_MPU specific bits */	82	/* PRCM_IRQENABLE_MPU specific bits */
83	#define OMAP2430_DPLL_RECAL_EN (1 << 6)	83	#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6)
84	#define OMAP24XX_TRANSITION_EN (1 << 5)	84	#define OMAP24XX_TRANSITION_EN_MASK (1 << 5)
85	#define OMAP24XX_EVGENOFF_EN (1 << 4)	85	#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4)
86	#define OMAP24XX_EVGENON_EN (1 << 3)	86	#define OMAP24XX_EVGENON_EN_MASK (1 << 3)
87		87
88	/* PRCM_VOLTCTRL */	88	/* PRCM_VOLTCTRL */
89	#define OMAP24XX_AUTO_EXTVOLT (1 << 15)	89	#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
90	#define OMAP24XX_FORCE_EXTVOLT (1 << 14)	90	#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14)
91	#define OMAP24XX_SETOFF_LEVEL_SHIFT 12	91	#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
92	#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)	92	#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
93	#define OMAP24XX_MEMRETCTRL (1 << 8)	93	#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
94	#define OMAP24XX_SETRET_LEVEL_SHIFT 6	94	#define OMAP24XX_SETRET_LEVEL_SHIFT 6
95	#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)	95	#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
96	#define OMAP24XX_VOLT_LEVEL_SHIFT 0	96	#define OMAP24XX_VOLT_LEVEL_SHIFT 0
@@ -104,13 +104,13 @@
104		104
105	/* PRCM_CLKOUT_CTRL */	105	/* PRCM_CLKOUT_CTRL */
106	#define OMAP2420_CLKOUT2_EN_SHIFT 15	106	#define OMAP2420_CLKOUT2_EN_SHIFT 15
107	#define OMAP2420_CLKOUT2_EN (1 << 15)	107	#define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
108	#define OMAP2420_CLKOUT2_DIV_SHIFT 11	108	#define OMAP2420_CLKOUT2_DIV_SHIFT 11
109	#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)	109	#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
110	#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8	110	#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
111	#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)	111	#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
112	#define OMAP24XX_CLKOUT_EN_SHIFT 7	112	#define OMAP24XX_CLKOUT_EN_SHIFT 7
113	#define OMAP24XX_CLKOUT_EN (1 << 7)	113	#define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
114	#define OMAP24XX_CLKOUT_DIV_SHIFT 3	114	#define OMAP24XX_CLKOUT_DIV_SHIFT 3
115	#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)	115	#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
116	#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0	116	#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
@@ -118,25 +118,25 @@
118		118
119	/* PRCM_CLKEMUL_CTRL */	119	/* PRCM_CLKEMUL_CTRL */
120	#define OMAP24XX_EMULATION_EN_SHIFT 0	120	#define OMAP24XX_EMULATION_EN_SHIFT 0
121	#define OMAP24XX_EMULATION_EN (1 << 0)	121	#define OMAP24XX_EMULATION_EN_MASK (1 << 0)
122		122
123	/* PRCM_CLKCFG_CTRL */	123	/* PRCM_CLKCFG_CTRL */
124	#define OMAP24XX_VALID_CONFIG (1 << 0)	124	#define OMAP24XX_VALID_CONFIG_MASK (1 << 0)
125		125
126	/* PRCM_CLKCFG_STATUS */	126	/* PRCM_CLKCFG_STATUS */
127	#define OMAP24XX_CONFIG_STATUS (1 << 0)	127	#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0)
128		128
129	/* PRCM_VOLTSETUP specific bits */	129	/* PRCM_VOLTSETUP specific bits */
130		130
131	/* PRCM_CLKSSETUP specific bits */	131	/* PRCM_CLKSSETUP specific bits */
132		132
133	/* PRCM_POLCTRL */	133	/* PRCM_POLCTRL */
134	#define OMAP2420_CLKOUT2_POL (1 << 10)	134	#define OMAP2420_CLKOUT2_POL_MASK (1 << 10)
135	#define OMAP24XX_CLKOUT_POL (1 << 9)	135	#define OMAP24XX_CLKOUT_POL_MASK (1 << 9)
136	#define OMAP24XX_CLKREQ_POL (1 << 8)	136	#define OMAP24XX_CLKREQ_POL_MASK (1 << 8)
137	#define OMAP2430_USE_POWEROK (1 << 2)	137	#define OMAP2430_USE_POWEROK_MASK (1 << 2)
138	#define OMAP2430_POWEROK_POL (1 << 1)	138	#define OMAP2430_POWEROK_POL_MASK (1 << 1)
139	#define OMAP24XX_EXTVOL_POL (1 << 0)	139	#define OMAP24XX_EXTVOL_POL_MASK (1 << 0)
140		140
141	/* RM_RSTST_MPU specific bits */	141	/* RM_RSTST_MPU specific bits */
142	/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */	142	/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
@@ -154,7 +154,7 @@
154	/* PM_EVEGENOFFTIM_MPU specific bits */	154	/* PM_EVEGENOFFTIM_MPU specific bits */
155		155
156	/* PM_PWSTCTRL_MPU specific bits */	156	/* PM_PWSTCTRL_MPU specific bits */
157	#define OMAP2430_FORCESTATE (1 << 18)	157	#define OMAP2430_FORCESTATE_MASK (1 << 18)
158		158
159	/* PM_PWSTST_MPU specific bits */	159	/* PM_PWSTST_MPU specific bits */
160	/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */	160	/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
@@ -168,21 +168,21 @@
168	/* PM_WKST2_CORE specific bits */	168	/* PM_WKST2_CORE specific bits */
169		169
170	/* PM_WKDEP_CORE specific bits*/	170	/* PM_WKDEP_CORE specific bits*/
171	#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5)	171	#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5)
172	#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3)	172	#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3)
173	#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2)	173	#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2)
174		174
175	/* PM_PWSTCTRL_CORE specific bits */	175	/* PM_PWSTCTRL_CORE specific bits */
176	#define OMAP24XX_MEMORYCHANGE (1 << 20)	176	#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20)
177	#define OMAP24XX_MEM3ONSTATE_SHIFT 14	177	#define OMAP24XX_MEM3ONSTATE_SHIFT 14
178	#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)	178	#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
179	#define OMAP24XX_MEM2ONSTATE_SHIFT 12	179	#define OMAP24XX_MEM2ONSTATE_SHIFT 12
180	#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)	180	#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
181	#define OMAP24XX_MEM1ONSTATE_SHIFT 10	181	#define OMAP24XX_MEM1ONSTATE_SHIFT 10
182	#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)	182	#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
183	#define OMAP24XX_MEM3RETSTATE (1 << 5)	183	#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5)
184	#define OMAP24XX_MEM2RETSTATE (1 << 4)	184	#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4)
185	#define OMAP24XX_MEM1RETSTATE (1 << 3)	185	#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3)
186		186
187	/* PM_PWSTST_CORE specific bits */	187	/* PM_PWSTST_CORE specific bits */
188	#define OMAP24XX_MEM3STATEST_SHIFT 14	188	#define OMAP24XX_MEM3STATEST_SHIFT 14
@@ -193,10 +193,10 @@
193	#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)	193	#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
194		194
195	/* RM_RSTCTRL_GFX */	195	/* RM_RSTCTRL_GFX */
196	#define OMAP24XX_GFX_RST (1 << 0)	196	#define OMAP24XX_GFX_RST_MASK (1 << 0)
197		197
198	/* RM_RSTST_GFX specific bits */	198	/* RM_RSTST_GFX specific bits */
199	#define OMAP24XX_GFX_SW_RST (1 << 4)	199	#define OMAP24XX_GFX_SW_RST_MASK (1 << 4)
200		200
201	/* PM_PWSTCTRL_GFX specific bits */	201	/* PM_PWSTCTRL_GFX specific bits */
202		202
@@ -209,25 +209,25 @@
209		209
210	/* RM_RSTST_WKUP specific bits */	210	/* RM_RSTST_WKUP specific bits */
211	/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */	211	/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
212	#define OMAP24XX_EXTWMPU_RST (1 << 6)	212	#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6)
213	#define OMAP24XX_SECU_WD_RST (1 << 5)	213	#define OMAP24XX_SECU_WD_RST_MASK (1 << 5)
214	#define OMAP24XX_MPU_WD_RST (1 << 4)	214	#define OMAP24XX_MPU_WD_RST_MASK (1 << 4)
215	#define OMAP24XX_SECU_VIOL_RST (1 << 3)	215	#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3)
216		216
217	/* PM_WKEN_WKUP specific bits */	217	/* PM_WKEN_WKUP specific bits */
218		218
219	/* PM_WKST_WKUP specific bits */	219	/* PM_WKST_WKUP specific bits */
220		220
221	/* RM_RSTCTRL_DSP */	221	/* RM_RSTCTRL_DSP */
222	#define OMAP2420_RST_IVA (1 << 8)	222	#define OMAP2420_RST_IVA_MASK (1 << 8)
223	#define OMAP24XX_RST2_DSP (1 << 1)	223	#define OMAP24XX_RST2_DSP_MASK (1 << 1)
224	#define OMAP24XX_RST1_DSP (1 << 0)	224	#define OMAP24XX_RST1_DSP_MASK (1 << 0)
225		225
226	/* RM_RSTST_DSP specific bits */	226	/* RM_RSTST_DSP specific bits */
227	/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */	227	/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
228	#define OMAP2420_IVA_SW_RST (1 << 8)	228	#define OMAP2420_IVA_SW_RST_MASK (1 << 8)
229	#define OMAP24XX_DSP_SW_RST2 (1 << 5)	229	#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5)
230	#define OMAP24XX_DSP_SW_RST1 (1 << 4)	230	#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4)
231		231
232	/* PM_WKDEP_DSP specific bits */	232	/* PM_WKDEP_DSP specific bits */
233		233
@@ -235,7 +235,7 @@
235	/* 2430 only: MEMONSTATE, MEMRETSTATE */	235	/* 2430 only: MEMONSTATE, MEMRETSTATE */
236	#define OMAP2420_MEMIONSTATE_SHIFT 12	236	#define OMAP2420_MEMIONSTATE_SHIFT 12
237	#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)	237	#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
238	#define OMAP2420_MEMIRETSTATE (1 << 4)	238	#define OMAP2420_MEMIRETSTATE_MASK (1 << 4)
239		239
240	/* PM_PWSTST_DSP specific bits */	240	/* PM_PWSTST_DSP specific bits */
241	/* MEMSTATEST is 2430 only */	241	/* MEMSTATEST is 2430 only */
@@ -248,18 +248,18 @@
248		248
249	/* RM_RSTCTRL_MDM */	249	/* RM_RSTCTRL_MDM */
250	/* 2430 only */	250	/* 2430 only */
251	#define OMAP2430_PWRON1_MDM (1 << 1)	251	#define OMAP2430_PWRON1_MDM_MASK (1 << 1)
252	#define OMAP2430_RST1_MDM (1 << 0)	252	#define OMAP2430_RST1_MDM_MASK (1 << 0)
253		253
254	/* RM_RSTST_MDM specific bits */	254	/* RM_RSTST_MDM specific bits */
255	/* 2430 only */	255	/* 2430 only */
256	#define OMAP2430_MDM_SECU_VIOL (1 << 6)	256	#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6)
257	#define OMAP2430_MDM_SW_PWRON1 (1 << 5)	257	#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5)
258	#define OMAP2430_MDM_SW_RST1 (1 << 4)	258	#define OMAP2430_MDM_SW_RST1_MASK (1 << 4)
259		259
260	/* PM_WKEN_MDM */	260	/* PM_WKEN_MDM */
261	/* 2430 only */	261	/* 2430 only */
262	#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0)	262	#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0)
263		263
264	/* PM_WKST_MDM specific bits */	264	/* PM_WKST_MDM specific bits */
265	/* 2430 only */	265	/* 2430 only */
@@ -269,7 +269,7 @@
269		269
270	/* PM_PWSTCTRL_MDM specific bits */	270	/* PM_PWSTCTRL_MDM specific bits */
271	/* 2430 only */	271	/* 2430 only */
272	#define OMAP2430_KILLDOMAINWKUP (1 << 19)	272	#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19)
273		273
274	/* PM_PWSTST_MDM specific bits */	274	/* PM_PWSTST_MDM specific bits */
275	/* 2430 only */	275	/* 2430 only */