diff options
Diffstat (limited to 'arch/arm/mach-omap2/prcm.c')
-rw-r--r-- | arch/arm/mach-omap2/prcm.c | 114 |
1 files changed, 75 insertions, 39 deletions
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index cf466ea1dffc..81872aacb801 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c | |||
@@ -11,6 +11,7 @@ | |||
11 | * Rajendra Nayak <rnayak@ti.com> | 11 | * Rajendra Nayak <rnayak@ti.com> |
12 | * | 12 | * |
13 | * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. | 13 | * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. |
14 | * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com> | ||
14 | * | 15 | * |
15 | * This program is free software; you can redistribute it and/or modify | 16 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | 17 | * it under the terms of the GNU General Public License version 2 as |
@@ -28,6 +29,7 @@ | |||
28 | #include <plat/control.h> | 29 | #include <plat/control.h> |
29 | 30 | ||
30 | #include "clock.h" | 31 | #include "clock.h" |
32 | #include "clock2xxx.h" | ||
31 | #include "cm.h" | 33 | #include "cm.h" |
32 | #include "prm.h" | 34 | #include "prm.h" |
33 | #include "prm-regbits-24xx.h" | 35 | #include "prm-regbits-24xx.h" |
@@ -121,19 +123,25 @@ struct omap3_prcm_regs prcm_context; | |||
121 | u32 omap_prcm_get_reset_sources(void) | 123 | u32 omap_prcm_get_reset_sources(void) |
122 | { | 124 | { |
123 | /* XXX This presumably needs modification for 34XX */ | 125 | /* XXX This presumably needs modification for 34XX */ |
124 | return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f; | 126 | if (cpu_is_omap24xx() | cpu_is_omap34xx()) |
127 | return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; | ||
128 | if (cpu_is_omap44xx()) | ||
129 | return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; | ||
130 | |||
131 | return 0; | ||
125 | } | 132 | } |
126 | EXPORT_SYMBOL(omap_prcm_get_reset_sources); | 133 | EXPORT_SYMBOL(omap_prcm_get_reset_sources); |
127 | 134 | ||
128 | /* Resets clock rates and reboots the system. Only called from system.h */ | 135 | /* Resets clock rates and reboots the system. Only called from system.h */ |
129 | void omap_prcm_arch_reset(char mode) | 136 | void omap_prcm_arch_reset(char mode) |
130 | { | 137 | { |
131 | s16 prcm_offs; | 138 | s16 prcm_offs = 0; |
132 | omap2_clk_prepare_for_reboot(); | 139 | |
140 | if (cpu_is_omap24xx()) { | ||
141 | omap2xxx_clk_prepare_for_reboot(); | ||
133 | 142 | ||
134 | if (cpu_is_omap24xx()) | ||
135 | prcm_offs = WKUP_MOD; | 143 | prcm_offs = WKUP_MOD; |
136 | else if (cpu_is_omap34xx()) { | 144 | } else if (cpu_is_omap34xx()) { |
137 | u32 l; | 145 | u32 l; |
138 | 146 | ||
139 | prcm_offs = OMAP3430_GR_MOD; | 147 | prcm_offs = OMAP3430_GR_MOD; |
@@ -144,10 +152,17 @@ void omap_prcm_arch_reset(char mode) | |||
144 | * cf. OMAP34xx TRM, Initialization / Software Booting | 152 | * cf. OMAP34xx TRM, Initialization / Software Booting |
145 | * Configuration. */ | 153 | * Configuration. */ |
146 | omap_writel(l, OMAP343X_SCRATCHPAD + 4); | 154 | omap_writel(l, OMAP343X_SCRATCHPAD + 4); |
147 | } else | 155 | } else if (cpu_is_omap44xx()) |
156 | prcm_offs = OMAP4430_PRM_DEVICE_MOD; | ||
157 | else | ||
148 | WARN_ON(1); | 158 | WARN_ON(1); |
149 | 159 | ||
150 | prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); | 160 | if (cpu_is_omap24xx() | cpu_is_omap34xx()) |
161 | prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, | ||
162 | OMAP2_RM_RSTCTRL); | ||
163 | if (cpu_is_omap44xx()) | ||
164 | prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, | ||
165 | OMAP4_RM_RSTCTRL); | ||
151 | } | 166 | } |
152 | 167 | ||
153 | static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) | 168 | static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) |
@@ -188,6 +203,18 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | |||
188 | return v; | 203 | return v; |
189 | } | 204 | } |
190 | 205 | ||
206 | /* Read a PRM register, AND it, and shift the result down to bit 0 */ | ||
207 | u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) | ||
208 | { | ||
209 | u32 v; | ||
210 | |||
211 | v = prm_read_mod_reg(domain, idx); | ||
212 | v &= mask; | ||
213 | v >>= __ffs(mask); | ||
214 | |||
215 | return v; | ||
216 | } | ||
217 | |||
191 | /* Read a register in a CM module */ | 218 | /* Read a register in a CM module */ |
192 | u32 cm_read_mod_reg(s16 module, u16 idx) | 219 | u32 cm_read_mod_reg(s16 module, u16 idx) |
193 | { | 220 | { |
@@ -217,26 +244,22 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | |||
217 | * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness | 244 | * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness |
218 | * @reg: physical address of module IDLEST register | 245 | * @reg: physical address of module IDLEST register |
219 | * @mask: value to mask against to determine if the module is active | 246 | * @mask: value to mask against to determine if the module is active |
247 | * @idlest: idle state indicator (0 or 1) for the clock | ||
220 | * @name: name of the clock (for printk) | 248 | * @name: name of the clock (for printk) |
221 | * | 249 | * |
222 | * Returns 1 if the module indicated readiness in time, or 0 if it | 250 | * Returns 1 if the module indicated readiness in time, or 0 if it |
223 | * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. | 251 | * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. |
224 | */ | 252 | */ |
225 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name) | 253 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, |
254 | const char *name) | ||
226 | { | 255 | { |
227 | int i = 0; | 256 | int i = 0; |
228 | int ena = 0; | 257 | int ena = 0; |
229 | 258 | ||
230 | /* | 259 | if (idlest) |
231 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | ||
232 | * 34xx reverses this, just to keep us on our toes | ||
233 | */ | ||
234 | if (cpu_is_omap24xx()) | ||
235 | ena = mask; | ||
236 | else if (cpu_is_omap34xx()) | ||
237 | ena = 0; | 260 | ena = 0; |
238 | else | 261 | else |
239 | BUG(); | 262 | ena = mask; |
240 | 263 | ||
241 | /* Wait for lock */ | 264 | /* Wait for lock */ |
242 | omap_test_timeout(((__raw_readl(reg) & mask) == ena), | 265 | omap_test_timeout(((__raw_readl(reg) & mask) == ena), |
@@ -254,9 +277,19 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name) | |||
254 | 277 | ||
255 | void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) | 278 | void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) |
256 | { | 279 | { |
257 | prm_base = omap2_globals->prm; | 280 | /* Static mapping, never released */ |
258 | cm_base = omap2_globals->cm; | 281 | if (omap2_globals->prm) { |
259 | cm2_base = omap2_globals->cm2; | 282 | prm_base = ioremap(omap2_globals->prm, SZ_8K); |
283 | WARN_ON(!prm_base); | ||
284 | } | ||
285 | if (omap2_globals->cm) { | ||
286 | cm_base = ioremap(omap2_globals->cm, SZ_8K); | ||
287 | WARN_ON(!cm_base); | ||
288 | } | ||
289 | if (omap2_globals->cm2) { | ||
290 | cm2_base = ioremap(omap2_globals->cm2, SZ_8K); | ||
291 | WARN_ON(!cm2_base); | ||
292 | } | ||
260 | } | 293 | } |
261 | 294 | ||
262 | #ifdef CONFIG_ARCH_OMAP3 | 295 | #ifdef CONFIG_ARCH_OMAP3 |
@@ -280,7 +313,7 @@ void omap3_prcm_save_context(void) | |||
280 | prcm_context.emu_cm_clksel = | 313 | prcm_context.emu_cm_clksel = |
281 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); | 314 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); |
282 | prcm_context.emu_cm_clkstctrl = | 315 | prcm_context.emu_cm_clkstctrl = |
283 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL); | 316 | cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); |
284 | prcm_context.pll_cm_autoidle2 = | 317 | prcm_context.pll_cm_autoidle2 = |
285 | cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); | 318 | cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); |
286 | prcm_context.pll_cm_clksel4 = | 319 | prcm_context.pll_cm_clksel4 = |
@@ -333,23 +366,25 @@ void omap3_prcm_save_context(void) | |||
333 | prcm_context.mpu_cm_autoidle2 = | 366 | prcm_context.mpu_cm_autoidle2 = |
334 | cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); | 367 | cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); |
335 | prcm_context.iva2_cm_clkstctrl = | 368 | prcm_context.iva2_cm_clkstctrl = |
336 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); | 369 | cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); |
337 | prcm_context.mpu_cm_clkstctrl = | 370 | prcm_context.mpu_cm_clkstctrl = |
338 | cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL); | 371 | cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); |
339 | prcm_context.core_cm_clkstctrl = | 372 | prcm_context.core_cm_clkstctrl = |
340 | cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL); | 373 | cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); |
341 | prcm_context.sgx_cm_clkstctrl = | 374 | prcm_context.sgx_cm_clkstctrl = |
342 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL); | 375 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, |
376 | OMAP2_CM_CLKSTCTRL); | ||
343 | prcm_context.dss_cm_clkstctrl = | 377 | prcm_context.dss_cm_clkstctrl = |
344 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL); | 378 | cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); |
345 | prcm_context.cam_cm_clkstctrl = | 379 | prcm_context.cam_cm_clkstctrl = |
346 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL); | 380 | cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); |
347 | prcm_context.per_cm_clkstctrl = | 381 | prcm_context.per_cm_clkstctrl = |
348 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL); | 382 | cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); |
349 | prcm_context.neon_cm_clkstctrl = | 383 | prcm_context.neon_cm_clkstctrl = |
350 | cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL); | 384 | cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); |
351 | prcm_context.usbhost_cm_clkstctrl = | 385 | prcm_context.usbhost_cm_clkstctrl = |
352 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); | 386 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, |
387 | OMAP2_CM_CLKSTCTRL); | ||
353 | prcm_context.core_cm_autoidle1 = | 388 | prcm_context.core_cm_autoidle1 = |
354 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); | 389 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); |
355 | prcm_context.core_cm_autoidle2 = | 390 | prcm_context.core_cm_autoidle2 = |
@@ -432,7 +467,7 @@ void omap3_prcm_restore_context(void) | |||
432 | cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, | 467 | cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, |
433 | CM_CLKSEL1); | 468 | CM_CLKSEL1); |
434 | cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, | 469 | cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, |
435 | CM_CLKSTCTRL); | 470 | OMAP2_CM_CLKSTCTRL); |
436 | cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, | 471 | cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, |
437 | CM_AUTOIDLE2); | 472 | CM_AUTOIDLE2); |
438 | cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, | 473 | cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, |
@@ -478,22 +513,23 @@ void omap3_prcm_restore_context(void) | |||
478 | CM_AUTOIDLE2); | 513 | CM_AUTOIDLE2); |
479 | cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); | 514 | cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); |
480 | cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, | 515 | cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, |
481 | CM_CLKSTCTRL); | 516 | OMAP2_CM_CLKSTCTRL); |
482 | cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL); | 517 | cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, |
518 | OMAP2_CM_CLKSTCTRL); | ||
483 | cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, | 519 | cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, |
484 | CM_CLKSTCTRL); | 520 | OMAP2_CM_CLKSTCTRL); |
485 | cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, | 521 | cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, |
486 | CM_CLKSTCTRL); | 522 | OMAP2_CM_CLKSTCTRL); |
487 | cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, | 523 | cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, |
488 | CM_CLKSTCTRL); | 524 | OMAP2_CM_CLKSTCTRL); |
489 | cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, | 525 | cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, |
490 | CM_CLKSTCTRL); | 526 | OMAP2_CM_CLKSTCTRL); |
491 | cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, | 527 | cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, |
492 | CM_CLKSTCTRL); | 528 | OMAP2_CM_CLKSTCTRL); |
493 | cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, | 529 | cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, |
494 | CM_CLKSTCTRL); | 530 | OMAP2_CM_CLKSTCTRL); |
495 | cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, | 531 | cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, |
496 | OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); | 532 | OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); |
497 | cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, | 533 | cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, |
498 | CM_AUTOIDLE1); | 534 | CM_AUTOIDLE1); |
499 | cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, | 535 | cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, |