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-rw-r--r--arch/arm/mach-omap2/prcm.c556
1 files changed, 51 insertions, 505 deletions
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index a51846e3a6fa..679bcd28576e 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,7 +17,8 @@
17 * it under the terms of the GNU General Public License version 2 as 17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation. 18 * published by the Free Software Foundation.
19 */ 19 */
20#include <linux/module.h> 20
21#include <linux/kernel.h>
21#include <linux/init.h> 22#include <linux/init.h>
22#include <linux/clk.h> 23#include <linux/clk.h>
23#include <linux/io.h> 24#include <linux/io.h>
@@ -29,105 +30,27 @@
29 30
30#include "clock.h" 31#include "clock.h"
31#include "clock2xxx.h" 32#include "clock2xxx.h"
32#include "cm.h" 33#include "cm2xxx_3xxx.h"
33#include "prm.h" 34#include "prm2xxx_3xxx.h"
35#include "prm44xx.h"
36#include "prminst44xx.h"
34#include "prm-regbits-24xx.h" 37#include "prm-regbits-24xx.h"
35#include "prm-regbits-44xx.h" 38#include "prm-regbits-44xx.h"
36#include "control.h" 39#include "control.h"
37 40
38static void __iomem *prm_base; 41void __iomem *prm_base;
39static void __iomem *cm_base; 42void __iomem *cm_base;
40static void __iomem *cm2_base; 43void __iomem *cm2_base;
41 44
42#define MAX_MODULE_ENABLE_WAIT 100000 45#define MAX_MODULE_ENABLE_WAIT 100000
43 46
44struct omap3_prcm_regs {
45 u32 control_padconf_sys_nirq;
46 u32 iva2_cm_clksel1;
47 u32 iva2_cm_clksel2;
48 u32 cm_sysconfig;
49 u32 sgx_cm_clksel;
50 u32 dss_cm_clksel;
51 u32 cam_cm_clksel;
52 u32 per_cm_clksel;
53 u32 emu_cm_clksel;
54 u32 emu_cm_clkstctrl;
55 u32 pll_cm_autoidle2;
56 u32 pll_cm_clksel4;
57 u32 pll_cm_clksel5;
58 u32 pll_cm_clken2;
59 u32 cm_polctrl;
60 u32 iva2_cm_fclken;
61 u32 iva2_cm_clken_pll;
62 u32 core_cm_fclken1;
63 u32 core_cm_fclken3;
64 u32 sgx_cm_fclken;
65 u32 wkup_cm_fclken;
66 u32 dss_cm_fclken;
67 u32 cam_cm_fclken;
68 u32 per_cm_fclken;
69 u32 usbhost_cm_fclken;
70 u32 core_cm_iclken1;
71 u32 core_cm_iclken2;
72 u32 core_cm_iclken3;
73 u32 sgx_cm_iclken;
74 u32 wkup_cm_iclken;
75 u32 dss_cm_iclken;
76 u32 cam_cm_iclken;
77 u32 per_cm_iclken;
78 u32 usbhost_cm_iclken;
79 u32 iva2_cm_autiidle2;
80 u32 mpu_cm_autoidle2;
81 u32 iva2_cm_clkstctrl;
82 u32 mpu_cm_clkstctrl;
83 u32 core_cm_clkstctrl;
84 u32 sgx_cm_clkstctrl;
85 u32 dss_cm_clkstctrl;
86 u32 cam_cm_clkstctrl;
87 u32 per_cm_clkstctrl;
88 u32 neon_cm_clkstctrl;
89 u32 usbhost_cm_clkstctrl;
90 u32 core_cm_autoidle1;
91 u32 core_cm_autoidle2;
92 u32 core_cm_autoidle3;
93 u32 wkup_cm_autoidle;
94 u32 dss_cm_autoidle;
95 u32 cam_cm_autoidle;
96 u32 per_cm_autoidle;
97 u32 usbhost_cm_autoidle;
98 u32 sgx_cm_sleepdep;
99 u32 dss_cm_sleepdep;
100 u32 cam_cm_sleepdep;
101 u32 per_cm_sleepdep;
102 u32 usbhost_cm_sleepdep;
103 u32 cm_clkout_ctrl;
104 u32 prm_clkout_ctrl;
105 u32 sgx_pm_wkdep;
106 u32 dss_pm_wkdep;
107 u32 cam_pm_wkdep;
108 u32 per_pm_wkdep;
109 u32 neon_pm_wkdep;
110 u32 usbhost_pm_wkdep;
111 u32 core_pm_mpugrpsel1;
112 u32 iva2_pm_ivagrpsel1;
113 u32 core_pm_mpugrpsel3;
114 u32 core_pm_ivagrpsel3;
115 u32 wkup_pm_mpugrpsel;
116 u32 wkup_pm_ivagrpsel;
117 u32 per_pm_mpugrpsel;
118 u32 per_pm_ivagrpsel;
119 u32 wkup_pm_wken;
120};
121
122static struct omap3_prcm_regs prcm_context;
123
124u32 omap_prcm_get_reset_sources(void) 47u32 omap_prcm_get_reset_sources(void)
125{ 48{
126 /* XXX This presumably needs modification for 34XX */ 49 /* XXX This presumably needs modification for 34XX */
127 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 50 if (cpu_is_omap24xx() || cpu_is_omap34xx())
128 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; 51 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
129 if (cpu_is_omap44xx()) 52 if (cpu_is_omap44xx())
130 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; 53 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
131 54
132 return 0; 55 return 0;
133} 56}
@@ -143,126 +66,46 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
143 66
144 prcm_offs = WKUP_MOD; 67 prcm_offs = WKUP_MOD;
145 } else if (cpu_is_omap34xx()) { 68 } else if (cpu_is_omap34xx()) {
146 u32 l;
147
148 prcm_offs = OMAP3430_GR_MOD; 69 prcm_offs = OMAP3430_GR_MOD;
149 l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0); 70 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
150 /* Reserve the first word in scratchpad for communicating 71 } else if (cpu_is_omap44xx()) {
151 * with the boot ROM. A pointer to a data structure 72 omap4_prm_global_warm_sw_reset(); /* never returns */
152 * describing the boot process can be stored there, 73 } else {
153 * cf. OMAP34xx TRM, Initialization / Software Booting
154 * Configuration. */
155 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
156 } else if (cpu_is_omap44xx())
157 prcm_offs = OMAP4430_PRM_DEVICE_MOD;
158 else
159 WARN_ON(1); 74 WARN_ON(1);
75 }
160 76
161 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 77 /*
162 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, 78 * As per Errata i520, in some cases, user will not be able to
163 OMAP2_RM_RSTCTRL); 79 * access DDR memory after warm-reset.
164 if (cpu_is_omap44xx()) 80 * This situation occurs while the warm-reset happens during a read
165 prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK, 81 * access to DDR memory. In that particular condition, DDR memory
166 prcm_offs, OMAP4_RM_RSTCTRL); 82 * does not respond to a corrupted read command due to the warm
167} 83 * reset occurrence but SDRC is waiting for read completion.
168 84 * SDRC is not sensitive to the warm reset, but the interconnect is
169static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) 85 * reset on the fly, thus causing a misalignment between SDRC logic,
170{ 86 * interconnect logic and DDR memory state.
171 BUG_ON(!base); 87 * WORKAROUND:
172 return __raw_readl(base + module + reg); 88 * Steps to perform before a Warm reset is trigged:
173} 89 * 1. enable self-refresh on idle request
174 90 * 2. put SDRC in idle
175static inline void __omap_prcm_write(u32 value, void __iomem *base, 91 * 3. wait until SDRC goes to idle
176 s16 module, u16 reg) 92 * 4. generate SW reset (Global SW reset)
177{ 93 *
178 BUG_ON(!base); 94 * Steps to be performed after warm reset occurs (in bootloader):
179 __raw_writel(value, base + module + reg); 95 * if HW warm reset is the source, apply below steps before any
180} 96 * accesses to SDRAM:
181 97 * 1. Reset SMS and SDRC and wait till reset is complete
182/* Read a register in a PRM module */ 98 * 2. Re-initialize SMS, SDRC and memory
183u32 prm_read_mod_reg(s16 module, u16 idx) 99 *
184{ 100 * NOTE: Above work around is required only if arch reset is implemented
185 return __omap_prcm_read(prm_base, module, idx); 101 * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
186} 102 * the WA since it resets SDRC as well as part of cold reset.
187 103 */
188/* Write into a register in a PRM module */ 104
189void prm_write_mod_reg(u32 val, s16 module, u16 idx) 105 /* XXX should be moved to some OMAP2/3 specific code */
190{ 106 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
191 __omap_prcm_write(val, prm_base, module, idx); 107 OMAP2_RM_RSTCTRL);
192} 108 omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
193
194/* Read-modify-write a register in a PRM module. Caller must lock */
195u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
196{
197 u32 v;
198
199 v = prm_read_mod_reg(module, idx);
200 v &= ~mask;
201 v |= bits;
202 prm_write_mod_reg(v, module, idx);
203
204 return v;
205}
206
207/* Read a PRM register, AND it, and shift the result down to bit 0 */
208u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
209{
210 u32 v;
211
212 v = prm_read_mod_reg(domain, idx);
213 v &= mask;
214 v >>= __ffs(mask);
215
216 return v;
217}
218
219/* Read a PRM register, AND it, and shift the result down to bit 0 */
220u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
221{
222 u32 v;
223
224 v = __raw_readl(reg);
225 v &= mask;
226 v >>= __ffs(mask);
227
228 return v;
229}
230
231/* Read-modify-write a register in a PRM module. Caller must lock */
232u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
233{
234 u32 v;
235
236 v = __raw_readl(reg);
237 v &= ~mask;
238 v |= bits;
239 __raw_writel(v, reg);
240
241 return v;
242}
243/* Read a register in a CM module */
244u32 cm_read_mod_reg(s16 module, u16 idx)
245{
246 return __omap_prcm_read(cm_base, module, idx);
247}
248
249/* Write into a register in a CM module */
250void cm_write_mod_reg(u32 val, s16 module, u16 idx)
251{
252 __omap_prcm_write(val, cm_base, module, idx);
253}
254
255/* Read-modify-write a register in a CM module. Caller must lock */
256u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
257{
258 u32 v;
259
260 v = cm_read_mod_reg(module, idx);
261 v &= ~mask;
262 v |= bits;
263 cm_write_mod_reg(v, module, idx);
264
265 return v;
266} 109}
267 110
268/** 111/**
@@ -274,6 +117,9 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
274 * 117 *
275 * Returns 1 if the module indicated readiness in time, or 0 if it 118 * Returns 1 if the module indicated readiness in time, or 0 if it
276 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. 119 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
120 *
121 * XXX This function is deprecated. It should be removed once the
122 * hwmod conversion is complete.
277 */ 123 */
278int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, 124int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
279 const char *name) 125 const char *name)
@@ -316,303 +162,3 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
316 WARN_ON(!cm2_base); 162 WARN_ON(!cm2_base);
317 } 163 }
318} 164}
319
320#ifdef CONFIG_ARCH_OMAP3
321void omap3_prcm_save_context(void)
322{
323 prcm_context.control_padconf_sys_nirq =
324 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
325 prcm_context.iva2_cm_clksel1 =
326 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
327 prcm_context.iva2_cm_clksel2 =
328 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
329 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
330 prcm_context.sgx_cm_clksel =
331 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
332 prcm_context.dss_cm_clksel =
333 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
334 prcm_context.cam_cm_clksel =
335 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
336 prcm_context.per_cm_clksel =
337 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
338 prcm_context.emu_cm_clksel =
339 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
340 prcm_context.emu_cm_clkstctrl =
341 cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
342 prcm_context.pll_cm_autoidle2 =
343 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
344 prcm_context.pll_cm_clksel4 =
345 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
346 prcm_context.pll_cm_clksel5 =
347 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
348 prcm_context.pll_cm_clken2 =
349 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
350 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
351 prcm_context.iva2_cm_fclken =
352 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
353 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
354 OMAP3430_CM_CLKEN_PLL);
355 prcm_context.core_cm_fclken1 =
356 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
357 prcm_context.core_cm_fclken3 =
358 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
359 prcm_context.sgx_cm_fclken =
360 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
361 prcm_context.wkup_cm_fclken =
362 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
363 prcm_context.dss_cm_fclken =
364 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
365 prcm_context.cam_cm_fclken =
366 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
367 prcm_context.per_cm_fclken =
368 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
369 prcm_context.usbhost_cm_fclken =
370 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
371 prcm_context.core_cm_iclken1 =
372 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
373 prcm_context.core_cm_iclken2 =
374 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
375 prcm_context.core_cm_iclken3 =
376 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
377 prcm_context.sgx_cm_iclken =
378 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
379 prcm_context.wkup_cm_iclken =
380 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
381 prcm_context.dss_cm_iclken =
382 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
383 prcm_context.cam_cm_iclken =
384 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
385 prcm_context.per_cm_iclken =
386 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
387 prcm_context.usbhost_cm_iclken =
388 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
389 prcm_context.iva2_cm_autiidle2 =
390 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
391 prcm_context.mpu_cm_autoidle2 =
392 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
393 prcm_context.iva2_cm_clkstctrl =
394 cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
395 prcm_context.mpu_cm_clkstctrl =
396 cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
397 prcm_context.core_cm_clkstctrl =
398 cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
399 prcm_context.sgx_cm_clkstctrl =
400 cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
401 OMAP2_CM_CLKSTCTRL);
402 prcm_context.dss_cm_clkstctrl =
403 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
404 prcm_context.cam_cm_clkstctrl =
405 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
406 prcm_context.per_cm_clkstctrl =
407 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
408 prcm_context.neon_cm_clkstctrl =
409 cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
410 prcm_context.usbhost_cm_clkstctrl =
411 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
412 OMAP2_CM_CLKSTCTRL);
413 prcm_context.core_cm_autoidle1 =
414 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
415 prcm_context.core_cm_autoidle2 =
416 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
417 prcm_context.core_cm_autoidle3 =
418 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
419 prcm_context.wkup_cm_autoidle =
420 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
421 prcm_context.dss_cm_autoidle =
422 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
423 prcm_context.cam_cm_autoidle =
424 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
425 prcm_context.per_cm_autoidle =
426 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
427 prcm_context.usbhost_cm_autoidle =
428 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
429 prcm_context.sgx_cm_sleepdep =
430 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
431 prcm_context.dss_cm_sleepdep =
432 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
433 prcm_context.cam_cm_sleepdep =
434 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
435 prcm_context.per_cm_sleepdep =
436 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
437 prcm_context.usbhost_cm_sleepdep =
438 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
439 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
440 OMAP3_CM_CLKOUT_CTRL_OFFSET);
441 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
442 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
443 prcm_context.sgx_pm_wkdep =
444 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
445 prcm_context.dss_pm_wkdep =
446 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
447 prcm_context.cam_pm_wkdep =
448 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
449 prcm_context.per_pm_wkdep =
450 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
451 prcm_context.neon_pm_wkdep =
452 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
453 prcm_context.usbhost_pm_wkdep =
454 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
455 prcm_context.core_pm_mpugrpsel1 =
456 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
457 prcm_context.iva2_pm_ivagrpsel1 =
458 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
459 prcm_context.core_pm_mpugrpsel3 =
460 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
461 prcm_context.core_pm_ivagrpsel3 =
462 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
463 prcm_context.wkup_pm_mpugrpsel =
464 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
465 prcm_context.wkup_pm_ivagrpsel =
466 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
467 prcm_context.per_pm_mpugrpsel =
468 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
469 prcm_context.per_pm_ivagrpsel =
470 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
471 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
472 return;
473}
474
475void omap3_prcm_restore_context(void)
476{
477 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
478 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
479 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
480 CM_CLKSEL1);
481 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
482 CM_CLKSEL2);
483 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
484 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
485 CM_CLKSEL);
486 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
487 CM_CLKSEL);
488 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
489 CM_CLKSEL);
490 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
491 CM_CLKSEL);
492 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
493 CM_CLKSEL1);
494 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
495 OMAP2_CM_CLKSTCTRL);
496 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
497 CM_AUTOIDLE2);
498 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
499 OMAP3430ES2_CM_CLKSEL4);
500 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
501 OMAP3430ES2_CM_CLKSEL5);
502 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
503 OMAP3430ES2_CM_CLKEN2);
504 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
505 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
506 CM_FCLKEN);
507 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
508 OMAP3430_CM_CLKEN_PLL);
509 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
510 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
511 OMAP3430ES2_CM_FCLKEN3);
512 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
513 CM_FCLKEN);
514 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
515 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
516 CM_FCLKEN);
517 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
518 CM_FCLKEN);
519 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
520 CM_FCLKEN);
521 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
522 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
523 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
524 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
525 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
526 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
527 CM_ICLKEN);
528 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
529 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
530 CM_ICLKEN);
531 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
532 CM_ICLKEN);
533 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
534 CM_ICLKEN);
535 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
536 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
537 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
538 CM_AUTOIDLE2);
539 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
540 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
541 OMAP2_CM_CLKSTCTRL);
542 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
543 OMAP2_CM_CLKSTCTRL);
544 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
545 OMAP2_CM_CLKSTCTRL);
546 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
547 OMAP2_CM_CLKSTCTRL);
548 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
549 OMAP2_CM_CLKSTCTRL);
550 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
551 OMAP2_CM_CLKSTCTRL);
552 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
553 OMAP2_CM_CLKSTCTRL);
554 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
555 OMAP2_CM_CLKSTCTRL);
556 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
557 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
558 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
559 CM_AUTOIDLE1);
560 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
561 CM_AUTOIDLE2);
562 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
563 CM_AUTOIDLE3);
564 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
565 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
566 CM_AUTOIDLE);
567 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
568 CM_AUTOIDLE);
569 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
570 CM_AUTOIDLE);
571 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
572 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
573 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
574 OMAP3430_CM_SLEEPDEP);
575 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
576 OMAP3430_CM_SLEEPDEP);
577 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
578 OMAP3430_CM_SLEEPDEP);
579 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
580 OMAP3430_CM_SLEEPDEP);
581 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
582 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
583 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
584 OMAP3_CM_CLKOUT_CTRL_OFFSET);
585 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
586 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
587 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
588 PM_WKDEP);
589 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
590 PM_WKDEP);
591 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
592 PM_WKDEP);
593 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
594 PM_WKDEP);
595 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
596 PM_WKDEP);
597 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
598 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
599 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
600 OMAP3430_PM_MPUGRPSEL1);
601 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
602 OMAP3430_PM_IVAGRPSEL1);
603 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
604 OMAP3430ES2_PM_MPUGRPSEL3);
605 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
606 OMAP3430ES2_PM_IVAGRPSEL3);
607 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
608 OMAP3430_PM_MPUGRPSEL);
609 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
610 OMAP3430_PM_IVAGRPSEL);
611 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
612 OMAP3430_PM_MPUGRPSEL);
613 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
614 OMAP3430_PM_IVAGRPSEL);
615 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
616 return;
617}
618#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 21:17:55 -0500