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-rw-r--r--arch/arm/mach-omap2/powerdomains44xx.h23
1 files changed, 16 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h
index c1015147d579..c7219513472a 100644
--- a/arch/arm/mach-omap2/powerdomains44xx.h
+++ b/arch/arm/mach-omap2/powerdomains44xx.h
@@ -1,12 +1,12 @@
1/* 1/*
2 * OMAP4 Power domains framework 2 * OMAP4 Power domains framework
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com) 8 * Benoit Cousson (b-cousson@ti.com)
9 * Paul Walmsley 9 * Paul Walmsley (paul@pwsan.com)
10 * 10 *
11 * This file is automatically generated from the OMAP hardware databases. 11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated 12 * We respectfully ask that any modifications to this file be coordinated
@@ -54,6 +54,7 @@ static struct powerdomain core_44xx_pwrdm = {
54 [3] = PWRDM_POWER_ON, /* ducati_l2ram */ 54 [3] = PWRDM_POWER_ON, /* ducati_l2ram */
55 [4] = PWRDM_POWER_ON, /* ducati_unicache */ 55 [4] = PWRDM_POWER_ON, /* ducati_unicache */
56 }, 56 },
57 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
57}; 58};
58 59
59/* gfx_44xx_pwrdm: 3D accelerator power domain */ 60/* gfx_44xx_pwrdm: 3D accelerator power domain */
@@ -69,6 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
69 .pwrsts_mem_on = { 70 .pwrsts_mem_on = {
70 [0] = PWRDM_POWER_ON, /* gfx_mem */ 71 [0] = PWRDM_POWER_ON, /* gfx_mem */
71 }, 72 },
73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
72}; 74};
73 75
74/* abe_44xx_pwrdm: Audio back end power domain */ 76/* abe_44xx_pwrdm: Audio back end power domain */
@@ -87,6 +89,7 @@ static struct powerdomain abe_44xx_pwrdm = {
87 [0] = PWRDM_POWER_ON, /* aessmem */ 89 [0] = PWRDM_POWER_ON, /* aessmem */
88 [1] = PWRDM_POWER_ON, /* periphmem */ 90 [1] = PWRDM_POWER_ON, /* periphmem */
89 }, 91 },
92 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
90}; 93};
91 94
92/* dss_44xx_pwrdm: Display subsystem power domain */ 95/* dss_44xx_pwrdm: Display subsystem power domain */
@@ -103,6 +106,7 @@ static struct powerdomain dss_44xx_pwrdm = {
103 .pwrsts_mem_on = { 106 .pwrsts_mem_on = {
104 [0] = PWRDM_POWER_ON, /* dss_mem */ 107 [0] = PWRDM_POWER_ON, /* dss_mem */
105 }, 108 },
109 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
106}; 110};
107 111
108/* tesla_44xx_pwrdm: Tesla processor power domain */ 112/* tesla_44xx_pwrdm: Tesla processor power domain */
@@ -123,6 +127,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
123 [1] = PWRDM_POWER_ON, /* tesla_l1 */ 127 [1] = PWRDM_POWER_ON, /* tesla_l1 */
124 [2] = PWRDM_POWER_ON, /* tesla_l2 */ 128 [2] = PWRDM_POWER_ON, /* tesla_l2 */
125 }, 129 },
130 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
126}; 131};
127 132
128/* wkup_44xx_pwrdm: Wake-up power domain */ 133/* wkup_44xx_pwrdm: Wake-up power domain */
@@ -130,7 +135,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
130 .name = "wkup_pwrdm", 135 .name = "wkup_pwrdm",
131 .prcm_offs = OMAP4430_PRM_WKUP_MOD, 136 .prcm_offs = OMAP4430_PRM_WKUP_MOD,
132 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
133 .pwrsts = PWRDM_POWER_ON, 138 .pwrsts = PWRSTS_ON,
134 .banks = 1, 139 .banks = 1,
135 .pwrsts_mem_ret = { 140 .pwrsts_mem_ret = {
136 [0] = PWRDM_POWER_OFF, /* wkup_bank */ 141 [0] = PWRDM_POWER_OFF, /* wkup_bank */
@@ -143,7 +148,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
143/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ 148/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
144static struct powerdomain cpu0_44xx_pwrdm = { 149static struct powerdomain cpu0_44xx_pwrdm = {
145 .name = "cpu0_pwrdm", 150 .name = "cpu0_pwrdm",
146 .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 151 .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD,
147 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
148 .pwrsts = PWRSTS_OFF_RET_ON, 153 .pwrsts = PWRSTS_OFF_RET_ON,
149 .pwrsts_logic_ret = PWRSTS_OFF_RET, 154 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -159,7 +164,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
159/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ 164/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
160static struct powerdomain cpu1_44xx_pwrdm = { 165static struct powerdomain cpu1_44xx_pwrdm = {
161 .name = "cpu1_pwrdm", 166 .name = "cpu1_pwrdm",
162 .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 167 .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD,
163 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 168 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
164 .pwrsts = PWRSTS_OFF_RET_ON, 169 .pwrsts = PWRSTS_OFF_RET_ON,
165 .pwrsts_logic_ret = PWRSTS_OFF_RET, 170 .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -227,6 +232,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
227 [2] = PWRDM_POWER_ON, /* tcm1_mem */ 232 [2] = PWRDM_POWER_ON, /* tcm1_mem */
228 [3] = PWRDM_POWER_ON, /* tcm2_mem */ 233 [3] = PWRDM_POWER_ON, /* tcm2_mem */
229 }, 234 },
235 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
230}; 236};
231 237
232/* cam_44xx_pwrdm: Camera subsystem power domain */ 238/* cam_44xx_pwrdm: Camera subsystem power domain */
@@ -242,6 +248,7 @@ static struct powerdomain cam_44xx_pwrdm = {
242 .pwrsts_mem_on = { 248 .pwrsts_mem_on = {
243 [0] = PWRDM_POWER_ON, /* cam_mem */ 249 [0] = PWRDM_POWER_ON, /* cam_mem */
244 }, 250 },
251 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
245}; 252};
246 253
247/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ 254/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
@@ -258,6 +265,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
258 .pwrsts_mem_on = { 265 .pwrsts_mem_on = {
259 [0] = PWRDM_POWER_ON, /* l3init_bank1 */ 266 [0] = PWRDM_POWER_ON, /* l3init_bank1 */
260 }, 267 },
268 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
261}; 269};
262 270
263/* l4per_44xx_pwrdm: Target peripherals power domain */ 271/* l4per_44xx_pwrdm: Target peripherals power domain */
@@ -276,6 +284,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
276 [0] = PWRDM_POWER_ON, /* nonretained_bank */ 284 [0] = PWRDM_POWER_ON, /* nonretained_bank */
277 [1] = PWRDM_POWER_ON, /* retained_bank */ 285 [1] = PWRDM_POWER_ON, /* retained_bank */
278 }, 286 },
287 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
279}; 288};
280 289
281/* 290/*
@@ -286,7 +295,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
286 .name = "always_on_core_pwrdm", 295 .name = "always_on_core_pwrdm",
287 .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, 296 .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD,
288 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 297 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
289 .pwrsts = PWRDM_POWER_ON, 298 .pwrsts = PWRSTS_ON,
290}; 299};
291 300
292/* cefuse_44xx_pwrdm: Customer efuse controller power domain */ 301/* cefuse_44xx_pwrdm: Customer efuse controller power domain */