diff options
Diffstat (limited to 'arch/arm/mach-omap2/powerdomains34xx.h')
-rw-r--r-- | arch/arm/mach-omap2/powerdomains34xx.h | 159 |
1 files changed, 9 insertions, 150 deletions
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index 588f7e07d0ea..bd87112beea8 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
@@ -1,8 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP34XX powerdomain definitions | 2 | * OMAP3 powerdomain definitions |
3 | * | 3 | * |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2007-2008 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
6 | * | 6 | * |
7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
8 | * Debugging and integration fixes by Jouni Högander | 8 | * Debugging and integration fixes by Jouni Högander |
@@ -32,128 +32,7 @@ | |||
32 | * 34XX-specific powerdomains, dependencies | 32 | * 34XX-specific powerdomains, dependencies |
33 | */ | 33 | */ |
34 | 34 | ||
35 | #ifdef CONFIG_ARCH_OMAP34XX | 35 | #ifdef CONFIG_ARCH_OMAP3 |
36 | |||
37 | /* | ||
38 | * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP | ||
39 | * (USBHOST is ES2 only) | ||
40 | */ | ||
41 | static struct pwrdm_dep per_usbhost_wkdeps[] = { | ||
42 | { | ||
43 | .pwrdm_name = "core_pwrdm", | ||
44 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
45 | }, | ||
46 | { | ||
47 | .pwrdm_name = "iva2_pwrdm", | ||
48 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
49 | }, | ||
50 | { | ||
51 | .pwrdm_name = "mpu_pwrdm", | ||
52 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
53 | }, | ||
54 | { | ||
55 | .pwrdm_name = "wkup_pwrdm", | ||
56 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
57 | }, | ||
58 | { NULL }, | ||
59 | }; | ||
60 | |||
61 | /* | ||
62 | * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER | ||
63 | */ | ||
64 | static struct pwrdm_dep mpu_34xx_wkdeps[] = { | ||
65 | { | ||
66 | .pwrdm_name = "core_pwrdm", | ||
67 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
68 | }, | ||
69 | { | ||
70 | .pwrdm_name = "iva2_pwrdm", | ||
71 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
72 | }, | ||
73 | { | ||
74 | .pwrdm_name = "dss_pwrdm", | ||
75 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
76 | }, | ||
77 | { | ||
78 | .pwrdm_name = "per_pwrdm", | ||
79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
80 | }, | ||
81 | { NULL }, | ||
82 | }; | ||
83 | |||
84 | /* | ||
85 | * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER | ||
86 | */ | ||
87 | static struct pwrdm_dep iva2_wkdeps[] = { | ||
88 | { | ||
89 | .pwrdm_name = "core_pwrdm", | ||
90 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
91 | }, | ||
92 | { | ||
93 | .pwrdm_name = "mpu_pwrdm", | ||
94 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
95 | }, | ||
96 | { | ||
97 | .pwrdm_name = "wkup_pwrdm", | ||
98 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
99 | }, | ||
100 | { | ||
101 | .pwrdm_name = "dss_pwrdm", | ||
102 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
103 | }, | ||
104 | { | ||
105 | .pwrdm_name = "per_pwrdm", | ||
106 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
107 | }, | ||
108 | { NULL }, | ||
109 | }; | ||
110 | |||
111 | |||
112 | /* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */ | ||
113 | static struct pwrdm_dep cam_dss_wkdeps[] = { | ||
114 | { | ||
115 | .pwrdm_name = "iva2_pwrdm", | ||
116 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
117 | }, | ||
118 | { | ||
119 | .pwrdm_name = "mpu_pwrdm", | ||
120 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
121 | }, | ||
122 | { | ||
123 | .pwrdm_name = "wkup_pwrdm", | ||
124 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
125 | }, | ||
126 | { NULL }, | ||
127 | }; | ||
128 | |||
129 | /* 3430: PM_WKDEP_NEON: MPU */ | ||
130 | static struct pwrdm_dep neon_wkdeps[] = { | ||
131 | { | ||
132 | .pwrdm_name = "mpu_pwrdm", | ||
133 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
134 | }, | ||
135 | { NULL }, | ||
136 | }; | ||
137 | |||
138 | |||
139 | /* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */ | ||
140 | |||
141 | /* | ||
142 | * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA | ||
143 | * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA | ||
144 | */ | ||
145 | static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = { | ||
146 | { | ||
147 | .pwrdm_name = "mpu_pwrdm", | ||
148 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
149 | }, | ||
150 | { | ||
151 | .pwrdm_name = "iva2_pwrdm", | ||
152 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
153 | }, | ||
154 | { NULL }, | ||
155 | }; | ||
156 | |||
157 | 36 | ||
158 | /* | 37 | /* |
159 | * Powerdomains | 38 | * Powerdomains |
@@ -163,8 +42,6 @@ static struct powerdomain iva2_pwrdm = { | |||
163 | .name = "iva2_pwrdm", | 42 | .name = "iva2_pwrdm", |
164 | .prcm_offs = OMAP3430_IVA2_MOD, | 43 | .prcm_offs = OMAP3430_IVA2_MOD, |
165 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 44 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
166 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, | ||
167 | .wkdep_srcs = iva2_wkdeps, | ||
168 | .pwrsts = PWRSTS_OFF_RET_ON, | 45 | .pwrsts = PWRSTS_OFF_RET_ON, |
169 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 46 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
170 | .banks = 4, | 47 | .banks = 4, |
@@ -182,12 +59,10 @@ static struct powerdomain iva2_pwrdm = { | |||
182 | }, | 59 | }, |
183 | }; | 60 | }; |
184 | 61 | ||
185 | static struct powerdomain mpu_34xx_pwrdm = { | 62 | static struct powerdomain mpu_3xxx_pwrdm = { |
186 | .name = "mpu_pwrdm", | 63 | .name = "mpu_pwrdm", |
187 | .prcm_offs = MPU_MOD, | 64 | .prcm_offs = MPU_MOD, |
188 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 65 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
189 | .dep_bit = OMAP3430_EN_MPU_SHIFT, | ||
190 | .wkdep_srcs = mpu_34xx_wkdeps, | ||
191 | .pwrsts = PWRSTS_OFF_RET_ON, | 66 | .pwrsts = PWRSTS_OFF_RET_ON, |
192 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 67 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
193 | .flags = PWRDM_HAS_MPU_QUIRK, | 68 | .flags = PWRDM_HAS_MPU_QUIRK, |
@@ -200,15 +75,14 @@ static struct powerdomain mpu_34xx_pwrdm = { | |||
200 | }, | 75 | }, |
201 | }; | 76 | }; |
202 | 77 | ||
203 | /* No wkdeps or sleepdeps for 34xx core apparently */ | 78 | static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { |
204 | static struct powerdomain core_34xx_pre_es3_1_pwrdm = { | ||
205 | .name = "core_pwrdm", | 79 | .name = "core_pwrdm", |
206 | .prcm_offs = CORE_MOD, | 80 | .prcm_offs = CORE_MOD, |
207 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | 81 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | |
208 | CHIP_IS_OMAP3430ES2 | | 82 | CHIP_IS_OMAP3430ES2 | |
209 | CHIP_IS_OMAP3430ES3_0), | 83 | CHIP_IS_OMAP3430ES3_0), |
210 | .pwrsts = PWRSTS_OFF_RET_ON, | 84 | .pwrsts = PWRSTS_OFF_RET_ON, |
211 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | 85 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
212 | .banks = 2, | 86 | .banks = 2, |
213 | .pwrsts_mem_ret = { | 87 | .pwrsts_mem_ret = { |
214 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | 88 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
@@ -220,13 +94,12 @@ static struct powerdomain core_34xx_pre_es3_1_pwrdm = { | |||
220 | }, | 94 | }, |
221 | }; | 95 | }; |
222 | 96 | ||
223 | /* No wkdeps or sleepdeps for 34xx core apparently */ | 97 | static struct powerdomain core_3xxx_es3_1_pwrdm = { |
224 | static struct powerdomain core_34xx_es3_1_pwrdm = { | ||
225 | .name = "core_pwrdm", | 98 | .name = "core_pwrdm", |
226 | .prcm_offs = CORE_MOD, | 99 | .prcm_offs = CORE_MOD, |
227 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), | 100 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), |
228 | .pwrsts = PWRSTS_OFF_RET_ON, | 101 | .pwrsts = PWRSTS_OFF_RET_ON, |
229 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | 102 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
230 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ | 103 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ |
231 | .banks = 2, | 104 | .banks = 2, |
232 | .pwrsts_mem_ret = { | 105 | .pwrsts_mem_ret = { |
@@ -239,14 +112,10 @@ static struct powerdomain core_34xx_es3_1_pwrdm = { | |||
239 | }, | 112 | }, |
240 | }; | 113 | }; |
241 | 114 | ||
242 | /* Another case of bit name collisions between several registers: EN_DSS */ | ||
243 | static struct powerdomain dss_pwrdm = { | 115 | static struct powerdomain dss_pwrdm = { |
244 | .name = "dss_pwrdm", | 116 | .name = "dss_pwrdm", |
245 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 117 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
246 | .prcm_offs = OMAP3430_DSS_MOD, | 118 | .prcm_offs = OMAP3430_DSS_MOD, |
247 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, | ||
248 | .wkdep_srcs = cam_dss_wkdeps, | ||
249 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | ||
250 | .pwrsts = PWRSTS_OFF_RET_ON, | 119 | .pwrsts = PWRSTS_OFF_RET_ON, |
251 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 120 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
252 | .banks = 1, | 121 | .banks = 1, |
@@ -267,8 +136,6 @@ static struct powerdomain sgx_pwrdm = { | |||
267 | .name = "sgx_pwrdm", | 136 | .name = "sgx_pwrdm", |
268 | .prcm_offs = OMAP3430ES2_SGX_MOD, | 137 | .prcm_offs = OMAP3430ES2_SGX_MOD, |
269 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 138 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
270 | .wkdep_srcs = gfx_sgx_wkdeps, | ||
271 | .sleepdep_srcs = cam_gfx_sleepdeps, | ||
272 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ | 139 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ |
273 | .pwrsts = PWRSTS_OFF_ON, | 140 | .pwrsts = PWRSTS_OFF_ON, |
274 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 141 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
@@ -285,8 +152,6 @@ static struct powerdomain cam_pwrdm = { | |||
285 | .name = "cam_pwrdm", | 152 | .name = "cam_pwrdm", |
286 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 153 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
287 | .prcm_offs = OMAP3430_CAM_MOD, | 154 | .prcm_offs = OMAP3430_CAM_MOD, |
288 | .wkdep_srcs = cam_dss_wkdeps, | ||
289 | .sleepdep_srcs = cam_gfx_sleepdeps, | ||
290 | .pwrsts = PWRSTS_OFF_RET_ON, | 155 | .pwrsts = PWRSTS_OFF_RET_ON, |
291 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 156 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
292 | .banks = 1, | 157 | .banks = 1, |
@@ -302,9 +167,6 @@ static struct powerdomain per_pwrdm = { | |||
302 | .name = "per_pwrdm", | 167 | .name = "per_pwrdm", |
303 | .prcm_offs = OMAP3430_PER_MOD, | 168 | .prcm_offs = OMAP3430_PER_MOD, |
304 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 169 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
305 | .dep_bit = OMAP3430_EN_PER_SHIFT, | ||
306 | .wkdep_srcs = per_usbhost_wkdeps, | ||
307 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | ||
308 | .pwrsts = PWRSTS_OFF_RET_ON, | 170 | .pwrsts = PWRSTS_OFF_RET_ON, |
309 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 171 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
310 | .banks = 1, | 172 | .banks = 1, |
@@ -326,7 +188,6 @@ static struct powerdomain neon_pwrdm = { | |||
326 | .name = "neon_pwrdm", | 188 | .name = "neon_pwrdm", |
327 | .prcm_offs = OMAP3430_NEON_MOD, | 189 | .prcm_offs = OMAP3430_NEON_MOD, |
328 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 190 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
329 | .wkdep_srcs = neon_wkdeps, | ||
330 | .pwrsts = PWRSTS_OFF_RET_ON, | 191 | .pwrsts = PWRSTS_OFF_RET_ON, |
331 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 192 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
332 | }; | 193 | }; |
@@ -335,8 +196,6 @@ static struct powerdomain usbhost_pwrdm = { | |||
335 | .name = "usbhost_pwrdm", | 196 | .name = "usbhost_pwrdm", |
336 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, | 197 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, |
337 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 198 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
338 | .wkdep_srcs = per_usbhost_wkdeps, | ||
339 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | ||
340 | .pwrsts = PWRSTS_OFF_RET_ON, | 199 | .pwrsts = PWRSTS_OFF_RET_ON, |
341 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 200 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
342 | /* | 201 | /* |
@@ -386,7 +245,7 @@ static struct powerdomain dpll5_pwrdm = { | |||
386 | }; | 245 | }; |
387 | 246 | ||
388 | 247 | ||
389 | #endif /* CONFIG_ARCH_OMAP34XX */ | 248 | #endif /* CONFIG_ARCH_OMAP3 */ |
390 | 249 | ||
391 | 250 | ||
392 | #endif | 251 | #endif |