diff options
Diffstat (limited to 'arch/arm/mach-omap2/pm34xx.c')
-rw-r--r-- | arch/arm/mach-omap2/pm34xx.c | 99 |
1 files changed, 8 insertions, 91 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 7b03426c72a3..d2b940c7215d 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -38,7 +38,6 @@ | |||
38 | #include <plat/prcm.h> | 38 | #include <plat/prcm.h> |
39 | #include <plat/gpmc.h> | 39 | #include <plat/gpmc.h> |
40 | #include <plat/dma.h> | 40 | #include <plat/dma.h> |
41 | #include <plat/dmtimer.h> | ||
42 | 41 | ||
43 | #include <asm/tlbflush.h> | 42 | #include <asm/tlbflush.h> |
44 | 43 | ||
@@ -55,11 +54,6 @@ | |||
55 | #define OMAP343X_TABLE_VALUE_OFFSET 0x30 | 54 | #define OMAP343X_TABLE_VALUE_OFFSET 0x30 |
56 | #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 | 55 | #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 |
57 | 56 | ||
58 | u32 enable_off_mode; | ||
59 | u32 sleep_while_idle; | ||
60 | u32 wakeup_timer_seconds; | ||
61 | u32 wakeup_timer_milliseconds; | ||
62 | |||
63 | struct power_state { | 57 | struct power_state { |
64 | struct powerdomain *pwrdm; | 58 | struct powerdomain *pwrdm; |
65 | u32 next_state; | 59 | u32 next_state; |
@@ -351,7 +345,6 @@ void omap_sram_idle(void) | |||
351 | int core_next_state = PWRDM_POWER_ON; | 345 | int core_next_state = PWRDM_POWER_ON; |
352 | int core_prev_state, per_prev_state; | 346 | int core_prev_state, per_prev_state; |
353 | u32 sdrc_pwr = 0; | 347 | u32 sdrc_pwr = 0; |
354 | int per_state_modified = 0; | ||
355 | 348 | ||
356 | if (!_omap_sram_idle) | 349 | if (!_omap_sram_idle) |
357 | return; | 350 | return; |
@@ -385,9 +378,9 @@ void omap_sram_idle(void) | |||
385 | /* Enable IO-PAD and IO-CHAIN wakeups */ | 378 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
386 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); | 379 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
387 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); | 380 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
388 | if (omap3_has_io_wakeup() && \ | 381 | if (omap3_has_io_wakeup() && |
389 | (per_next_state < PWRDM_POWER_ON || | 382 | (per_next_state < PWRDM_POWER_ON || |
390 | core_next_state < PWRDM_POWER_ON)) { | 383 | core_next_state < PWRDM_POWER_ON)) { |
391 | prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); | 384 | prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
392 | omap3_enable_io_chain(); | 385 | omap3_enable_io_chain(); |
393 | } | 386 | } |
@@ -396,19 +389,10 @@ void omap_sram_idle(void) | |||
396 | if (per_next_state < PWRDM_POWER_ON) { | 389 | if (per_next_state < PWRDM_POWER_ON) { |
397 | omap_uart_prepare_idle(2); | 390 | omap_uart_prepare_idle(2); |
398 | omap2_gpio_prepare_for_idle(per_next_state); | 391 | omap2_gpio_prepare_for_idle(per_next_state); |
399 | if (per_next_state == PWRDM_POWER_OFF) { | 392 | if (per_next_state == PWRDM_POWER_OFF) |
400 | if (core_next_state == PWRDM_POWER_ON) { | ||
401 | per_next_state = PWRDM_POWER_RET; | ||
402 | pwrdm_set_next_pwrst(per_pwrdm, per_next_state); | ||
403 | per_state_modified = 1; | ||
404 | } else | ||
405 | omap3_per_save_context(); | 393 | omap3_per_save_context(); |
406 | } | ||
407 | } | 394 | } |
408 | 395 | ||
409 | if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) | ||
410 | omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); | ||
411 | |||
412 | /* CORE */ | 396 | /* CORE */ |
413 | if (core_next_state < PWRDM_POWER_ON) { | 397 | if (core_next_state < PWRDM_POWER_ON) { |
414 | omap_uart_prepare_idle(0); | 398 | omap_uart_prepare_idle(0); |
@@ -475,8 +459,6 @@ void omap_sram_idle(void) | |||
475 | if (per_prev_state == PWRDM_POWER_OFF) | 459 | if (per_prev_state == PWRDM_POWER_OFF) |
476 | omap3_per_restore_context(); | 460 | omap3_per_restore_context(); |
477 | omap_uart_resume_idle(2); | 461 | omap_uart_resume_idle(2); |
478 | if (per_state_modified) | ||
479 | pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); | ||
480 | } | 462 | } |
481 | 463 | ||
482 | /* Disable IO-PAD and IO-CHAIN wakeup */ | 464 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
@@ -501,51 +483,6 @@ int omap3_can_sleep(void) | |||
501 | return 1; | 483 | return 1; |
502 | } | 484 | } |
503 | 485 | ||
504 | /* This sets pwrdm state (other than mpu & core. Currently only ON & | ||
505 | * RET are supported. Function is assuming that clkdm doesn't have | ||
506 | * hw_sup mode enabled. */ | ||
507 | int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) | ||
508 | { | ||
509 | u32 cur_state; | ||
510 | int sleep_switch = 0; | ||
511 | int ret = 0; | ||
512 | |||
513 | if (pwrdm == NULL || IS_ERR(pwrdm)) | ||
514 | return -EINVAL; | ||
515 | |||
516 | while (!(pwrdm->pwrsts & (1 << state))) { | ||
517 | if (state == PWRDM_POWER_OFF) | ||
518 | return ret; | ||
519 | state--; | ||
520 | } | ||
521 | |||
522 | cur_state = pwrdm_read_next_pwrst(pwrdm); | ||
523 | if (cur_state == state) | ||
524 | return ret; | ||
525 | |||
526 | if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { | ||
527 | omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); | ||
528 | sleep_switch = 1; | ||
529 | pwrdm_wait_transition(pwrdm); | ||
530 | } | ||
531 | |||
532 | ret = pwrdm_set_next_pwrst(pwrdm, state); | ||
533 | if (ret) { | ||
534 | printk(KERN_ERR "Unable to set state of powerdomain: %s\n", | ||
535 | pwrdm->name); | ||
536 | goto err; | ||
537 | } | ||
538 | |||
539 | if (sleep_switch) { | ||
540 | omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); | ||
541 | pwrdm_wait_transition(pwrdm); | ||
542 | pwrdm_state_switch(pwrdm); | ||
543 | } | ||
544 | |||
545 | err: | ||
546 | return ret; | ||
547 | } | ||
548 | |||
549 | static void omap3_pm_idle(void) | 486 | static void omap3_pm_idle(void) |
550 | { | 487 | { |
551 | local_irq_disable(); | 488 | local_irq_disable(); |
@@ -567,23 +504,6 @@ out: | |||
567 | #ifdef CONFIG_SUSPEND | 504 | #ifdef CONFIG_SUSPEND |
568 | static suspend_state_t suspend_state; | 505 | static suspend_state_t suspend_state; |
569 | 506 | ||
570 | static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) | ||
571 | { | ||
572 | u32 tick_rate, cycles; | ||
573 | |||
574 | if (!seconds && !milliseconds) | ||
575 | return; | ||
576 | |||
577 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); | ||
578 | cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; | ||
579 | omap_dm_timer_stop(gptimer_wakeup); | ||
580 | omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); | ||
581 | |||
582 | pr_info("PM: Resume timer in %u.%03u secs" | ||
583 | " (%d ticks at %d ticks/sec.)\n", | ||
584 | seconds, milliseconds, cycles, tick_rate); | ||
585 | } | ||
586 | |||
587 | static int omap3_pm_prepare(void) | 507 | static int omap3_pm_prepare(void) |
588 | { | 508 | { |
589 | disable_hlt(); | 509 | disable_hlt(); |
@@ -604,7 +524,7 @@ static int omap3_pm_suspend(void) | |||
604 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | 524 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); |
605 | /* Set ones wanted by suspend */ | 525 | /* Set ones wanted by suspend */ |
606 | list_for_each_entry(pwrst, &pwrst_list, node) { | 526 | list_for_each_entry(pwrst, &pwrst_list, node) { |
607 | if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) | 527 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
608 | goto restore; | 528 | goto restore; |
609 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | 529 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) |
610 | goto restore; | 530 | goto restore; |
@@ -625,7 +545,7 @@ restore: | |||
625 | pwrst->pwrdm->name, pwrst->next_state); | 545 | pwrst->pwrdm->name, pwrst->next_state); |
626 | ret = -1; | 546 | ret = -1; |
627 | } | 547 | } |
628 | set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); | 548 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
629 | } | 549 | } |
630 | if (ret) | 550 | if (ret) |
631 | printk(KERN_ERR "Could not enter target state in pm_suspend\n"); | 551 | printk(KERN_ERR "Could not enter target state in pm_suspend\n"); |
@@ -974,7 +894,7 @@ void omap3_pm_off_mode_enable(int enable) | |||
974 | 894 | ||
975 | list_for_each_entry(pwrst, &pwrst_list, node) { | 895 | list_for_each_entry(pwrst, &pwrst_list, node) { |
976 | pwrst->next_state = state; | 896 | pwrst->next_state = state; |
977 | set_pwrdm_state(pwrst->pwrdm, state); | 897 | omap_set_pwrdm_state(pwrst->pwrdm, state); |
978 | } | 898 | } |
979 | } | 899 | } |
980 | 900 | ||
@@ -1019,7 +939,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) | |||
1019 | if (pwrdm_has_hdwr_sar(pwrdm)) | 939 | if (pwrdm_has_hdwr_sar(pwrdm)) |
1020 | pwrdm_enable_hdwr_sar(pwrdm); | 940 | pwrdm_enable_hdwr_sar(pwrdm); |
1021 | 941 | ||
1022 | return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | 942 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
1023 | } | 943 | } |
1024 | 944 | ||
1025 | /* | 945 | /* |
@@ -1029,9 +949,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) | |||
1029 | */ | 949 | */ |
1030 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) | 950 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
1031 | { | 951 | { |
1032 | clkdm_clear_all_wkdeps(clkdm); | ||
1033 | clkdm_clear_all_sleepdeps(clkdm); | ||
1034 | |||
1035 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | 952 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) |
1036 | omap2_clkdm_allow_idle(clkdm); | 953 | omap2_clkdm_allow_idle(clkdm); |
1037 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | 954 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |