1 files changed, 102 insertions, 102 deletions

diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index aea7ced9a2ff..2844b84f8d46 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -42,16 +42,16 @@
 #include <plat/dma.h>
 #include <plat/board.h>
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
 
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
 
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
@@ -79,8 +79,8 @@ static int omap2_fclks_active(void)
 {
         u32 f1, f2;
 
-        f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-        f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+        f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 
         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
         f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
@@ -105,9 +105,9 @@ static void omap2_enter_full_retention(void)
 
         /* Clear old wake-up events */
         /* REVISIT: These write to reserved bits? */
-        prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
-        prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+        omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 
         /*
          * Set MPU powerdomain's next power state to RETENTION;
@@ -120,7 +120,7 @@ static void omap2_enter_full_retention(void)
         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 
-        omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);
+        omap2_gpio_prepare_for_idle(0);
 
         if (omap2_pm_debug) {
                 omap2_pm_dump(0, 0, 0);
@@ -167,30 +167,30 @@ no_sleep:
         clk_enable(osc_ck);
 
         /* clear CORE wake-up events */
-        prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 
         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
-        prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
+        omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 
         /* MPU domain wake events */
-        l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
         if (l & 0x01)
-                prm_write_mod_reg(0x01, OCP_MOD,
+                omap2_prm_write_mod_reg(0x01, OCP_MOD,
                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
         if (l & 0x20)
-                prm_write_mod_reg(0x20, OCP_MOD,
+                omap2_prm_write_mod_reg(0x20, OCP_MOD,
                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 
         /* Mask future PRCM-to-MPU interrupts */
-        prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 }
 
 static int omap2_i2c_active(void)
 {
         u32 l;
 
-        l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 }
 
@@ -201,13 +201,13 @@ static int omap2_allow_mpu_retention(void)
         u32 l;
 
         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
-        l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
                 return 0;
         /* Check for UART3. */
-        l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+        l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
         if (l & OMAP24XX_EN_UART3_MASK)
                 return 0;
         if (sti_console_enabled)
@@ -230,18 +230,18 @@ static void omap2_enter_mpu_retention(void)
          * it is in retention mode. */
         if (omap2_allow_mpu_retention()) {
                 /* REVISIT: These write to reserved bits? */
-                prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-                prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
-                prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+                omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+                omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+                omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 
                 /* Try to enter MPU retention */
-                prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
+                omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
                                   OMAP_LOGICRETSTATE_MASK,
                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
         } else {
                 /* Block MPU retention */
 
-                prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
+                omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
                                                  OMAP2_PM_PWSTCTRL);
                 only_idle = 1;
         }
@@ -310,9 +310,9 @@ static int omap2_pm_suspend(void)
 {
         u32 wken_wkup, mir1;
 
-        wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+        wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
-        prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
+        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 
         /* Mask GPT1 */
         mir1 = omap_readl(0x480fe0a4);
@@ -322,7 +322,7 @@ static int omap2_pm_suspend(void)
         omap2_enter_full_retention();
 
         omap_writel(mir1, 0x480fe0a4);
-        prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
+        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 
         return 0;
 }
@@ -376,7 +376,7 @@ static void __init prcm_setup_regs(void)
         struct powerdomain *pwrdm;
 
         /* Enable autoidle */
-        prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
+        omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 
         /*
@@ -415,87 +415,87 @@ static void __init prcm_setup_regs(void)
         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
         /* Enable clock autoidle for all domains */
-        cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
-                         OMAP24XX_AUTO_MAILBOXES_MASK |
-                         OMAP24XX_AUTO_WDT4_MASK |
-                         OMAP2420_AUTO_WDT3_MASK |
-                         OMAP24XX_AUTO_MSPRO_MASK |
-                         OMAP2420_AUTO_MMC_MASK |
-                         OMAP24XX_AUTO_FAC_MASK |
-                         OMAP2420_AUTO_EAC_MASK |
-                         OMAP24XX_AUTO_HDQ_MASK |
-                         OMAP24XX_AUTO_UART2_MASK |
-                         OMAP24XX_AUTO_UART1_MASK |
-                         OMAP24XX_AUTO_I2C2_MASK |
-                         OMAP24XX_AUTO_I2C1_MASK |
-                         OMAP24XX_AUTO_MCSPI2_MASK |
-                         OMAP24XX_AUTO_MCSPI1_MASK |
-                         OMAP24XX_AUTO_MCBSP2_MASK |
-                         OMAP24XX_AUTO_MCBSP1_MASK |
-                         OMAP24XX_AUTO_GPT12_MASK |
-                         OMAP24XX_AUTO_GPT11_MASK |
-                         OMAP24XX_AUTO_GPT10_MASK |
-                         OMAP24XX_AUTO_GPT9_MASK |
-                         OMAP24XX_AUTO_GPT8_MASK |
-                         OMAP24XX_AUTO_GPT7_MASK |
-                         OMAP24XX_AUTO_GPT6_MASK |
-                         OMAP24XX_AUTO_GPT5_MASK |
-                         OMAP24XX_AUTO_GPT4_MASK |
-                         OMAP24XX_AUTO_GPT3_MASK |
-                         OMAP24XX_AUTO_GPT2_MASK |
-                         OMAP2420_AUTO_VLYNQ_MASK |
-                         OMAP24XX_AUTO_DSS_MASK,
-                         CORE_MOD, CM_AUTOIDLE1);
-        cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
-                         OMAP24XX_AUTO_SSI_MASK |
-                         OMAP24XX_AUTO_USB_MASK,
-                         CORE_MOD, CM_AUTOIDLE2);
-        cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
-                         OMAP24XX_AUTO_GPMC_MASK |
-                         OMAP24XX_AUTO_SDMA_MASK,
-                         CORE_MOD, CM_AUTOIDLE3);
-        cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
-                         OMAP24XX_AUTO_AES_MASK |
-                         OMAP24XX_AUTO_RNG_MASK |
-                         OMAP24XX_AUTO_SHA_MASK |
-                         OMAP24XX_AUTO_DES_MASK,
-                         CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
-
-        cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
-                         CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
+                               OMAP24XX_AUTO_MAILBOXES_MASK |
+                               OMAP24XX_AUTO_WDT4_MASK |
+                               OMAP2420_AUTO_WDT3_MASK |
+                               OMAP24XX_AUTO_MSPRO_MASK |
+                               OMAP2420_AUTO_MMC_MASK |
+                               OMAP24XX_AUTO_FAC_MASK |
+                               OMAP2420_AUTO_EAC_MASK |
+                               OMAP24XX_AUTO_HDQ_MASK |
+                               OMAP24XX_AUTO_UART2_MASK |
+                               OMAP24XX_AUTO_UART1_MASK |
+                               OMAP24XX_AUTO_I2C2_MASK |
+                               OMAP24XX_AUTO_I2C1_MASK |
+                               OMAP24XX_AUTO_MCSPI2_MASK |
+                               OMAP24XX_AUTO_MCSPI1_MASK |
+                               OMAP24XX_AUTO_MCBSP2_MASK |
+                               OMAP24XX_AUTO_MCBSP1_MASK |
+                               OMAP24XX_AUTO_GPT12_MASK |
+                               OMAP24XX_AUTO_GPT11_MASK |
+                               OMAP24XX_AUTO_GPT10_MASK |
+                               OMAP24XX_AUTO_GPT9_MASK |
+                               OMAP24XX_AUTO_GPT8_MASK |
+                               OMAP24XX_AUTO_GPT7_MASK |
+                               OMAP24XX_AUTO_GPT6_MASK |
+                               OMAP24XX_AUTO_GPT5_MASK |
+                               OMAP24XX_AUTO_GPT4_MASK |
+                               OMAP24XX_AUTO_GPT3_MASK |
+                               OMAP24XX_AUTO_GPT2_MASK |
+                               OMAP2420_AUTO_VLYNQ_MASK |
+                               OMAP24XX_AUTO_DSS_MASK,
+                               CORE_MOD, CM_AUTOIDLE1);
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
+                               OMAP24XX_AUTO_SSI_MASK |
+                               OMAP24XX_AUTO_USB_MASK,
+                               CORE_MOD, CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
+                               OMAP24XX_AUTO_GPMC_MASK |
+                               OMAP24XX_AUTO_SDMA_MASK,
+                               CORE_MOD, CM_AUTOIDLE3);
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
+                               OMAP24XX_AUTO_AES_MASK |
+                               OMAP24XX_AUTO_RNG_MASK |
+                               OMAP24XX_AUTO_SHA_MASK |
+                               OMAP24XX_AUTO_DES_MASK,
+                               CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
+
+        omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
+                               CM_AUTOIDLE);
 
         /* Put DPLL and both APLLs into autoidle mode */
-        cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
-                         (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
-                         (0x03 << OMAP24XX_AUTO_54M_SHIFT),
-                         PLL_MOD, CM_AUTOIDLE);
-
-        cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
-                         OMAP24XX_AUTO_WDT1_MASK |
-                         OMAP24XX_AUTO_MPU_WDT_MASK |
-                         OMAP24XX_AUTO_GPIOS_MASK |
-                         OMAP24XX_AUTO_32KSYNC_MASK |
-                         OMAP24XX_AUTO_GPT1_MASK,
-                         WKUP_MOD, CM_AUTOIDLE);
+        omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
+                               (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
+                               (0x03 << OMAP24XX_AUTO_54M_SHIFT),
+                               PLL_MOD, CM_AUTOIDLE);
+
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
+                               OMAP24XX_AUTO_WDT1_MASK |
+                               OMAP24XX_AUTO_MPU_WDT_MASK |
+                               OMAP24XX_AUTO_GPIOS_MASK |
+                               OMAP24XX_AUTO_32KSYNC_MASK |
+                               OMAP24XX_AUTO_GPT1_MASK,
+                               WKUP_MOD, CM_AUTOIDLE);
 
         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
          * stabilisation */
-        prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
-                          OMAP2_PRCM_CLKSSETUP_OFFSET);
+        omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                                OMAP2_PRCM_CLKSSETUP_OFFSET);
 
         /* Configure automatic voltage transition */
-        prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
-                          OMAP2_PRCM_VOLTSETUP_OFFSET);
-        prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
-                          (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
-                          OMAP24XX_MEMRETCTRL_MASK |
-                          (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
-                          (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
-                          OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
+        omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                                OMAP2_PRCM_VOLTSETUP_OFFSET);
+        omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
+                                (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
+                                OMAP24XX_MEMRETCTRL_MASK |
+                                (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
+                                (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
+                                OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 
         /* Enable wake-up events */
-        prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
-                          WKUP_MOD, PM_WKEN);
+        omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
+                                WKUP_MOD, PM_WKEN);
 }
 
 static int __init omap2_pm_init(void)
@@ -506,7 +506,7 @@ static int __init omap2_pm_init(void)
                 return -ENODEV;
 
         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
-        l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
+        l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 
         /* Look up important powerdomains */