diff options
Diffstat (limited to 'arch/arm/mach-omap2/pm24xx.c')
-rw-r--r-- | arch/arm/mach-omap2/pm24xx.c | 100 |
1 files changed, 10 insertions, 90 deletions
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a4eb5c280435..5ca45ca76946 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
@@ -26,7 +26,6 @@ | |||
26 | #include <linux/module.h> | 26 | #include <linux/module.h> |
27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
28 | #include <linux/clk.h> | 28 | #include <linux/clk.h> |
29 | #include <linux/io.h> | ||
30 | #include <linux/irq.h> | 29 | #include <linux/irq.h> |
31 | #include <linux/time.h> | 30 | #include <linux/time.h> |
32 | #include <linux/gpio.h> | 31 | #include <linux/gpio.h> |
@@ -35,12 +34,13 @@ | |||
35 | #include <asm/mach/irq.h> | 34 | #include <asm/mach/irq.h> |
36 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
37 | 36 | ||
38 | #include <mach/irqs.h> | ||
39 | #include <plat/clock.h> | 37 | #include <plat/clock.h> |
40 | #include <plat/sram.h> | 38 | #include <plat/sram.h> |
41 | #include <plat/dma.h> | 39 | #include <plat/dma.h> |
42 | #include <plat/board.h> | 40 | #include <plat/board.h> |
43 | 41 | ||
42 | #include <mach/irqs.h> | ||
43 | |||
44 | #include "common.h" | 44 | #include "common.h" |
45 | #include "prm2xxx_3xxx.h" | 45 | #include "prm2xxx_3xxx.h" |
46 | #include "prm-regbits-24xx.h" | 46 | #include "prm-regbits-24xx.h" |
@@ -49,23 +49,9 @@ | |||
49 | #include "sdrc.h" | 49 | #include "sdrc.h" |
50 | #include "pm.h" | 50 | #include "pm.h" |
51 | #include "control.h" | 51 | #include "control.h" |
52 | |||
53 | #include "powerdomain.h" | 52 | #include "powerdomain.h" |
54 | #include "clockdomain.h" | 53 | #include "clockdomain.h" |
55 | 54 | ||
56 | #ifdef CONFIG_SUSPEND | ||
57 | static suspend_state_t suspend_state = PM_SUSPEND_ON; | ||
58 | static inline bool is_suspending(void) | ||
59 | { | ||
60 | return (suspend_state != PM_SUSPEND_ON); | ||
61 | } | ||
62 | #else | ||
63 | static inline bool is_suspending(void) | ||
64 | { | ||
65 | return false; | ||
66 | } | ||
67 | #endif | ||
68 | |||
69 | static void (*omap2_sram_idle)(void); | 55 | static void (*omap2_sram_idle)(void); |
70 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, | 56 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, |
71 | void __iomem *sdrc_power); | 57 | void __iomem *sdrc_power); |
@@ -85,7 +71,7 @@ static int omap2_fclks_active(void) | |||
85 | return (f1 | f2) ? 1 : 0; | 71 | return (f1 | f2) ? 1 : 0; |
86 | } | 72 | } |
87 | 73 | ||
88 | static void omap2_enter_full_retention(void) | 74 | static int omap2_enter_full_retention(void) |
89 | { | 75 | { |
90 | u32 l; | 76 | u32 l; |
91 | 77 | ||
@@ -148,6 +134,8 @@ no_sleep: | |||
148 | 134 | ||
149 | /* Mask future PRCM-to-MPU interrupts */ | 135 | /* Mask future PRCM-to-MPU interrupts */ |
150 | omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); | 136 | omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
137 | |||
138 | return 0; | ||
151 | } | 139 | } |
152 | 140 | ||
153 | static int omap2_i2c_active(void) | 141 | static int omap2_i2c_active(void) |
@@ -244,77 +232,6 @@ out: | |||
244 | local_fiq_enable(); | 232 | local_fiq_enable(); |
245 | } | 233 | } |
246 | 234 | ||
247 | #ifdef CONFIG_SUSPEND | ||
248 | static int omap2_pm_begin(suspend_state_t state) | ||
249 | { | ||
250 | disable_hlt(); | ||
251 | suspend_state = state; | ||
252 | return 0; | ||
253 | } | ||
254 | |||
255 | static int omap2_pm_suspend(void) | ||
256 | { | ||
257 | u32 wken_wkup, mir1; | ||
258 | |||
259 | wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); | ||
260 | wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; | ||
261 | omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); | ||
262 | |||
263 | /* Mask GPT1 */ | ||
264 | mir1 = omap_readl(0x480fe0a4); | ||
265 | omap_writel(1 << 5, 0x480fe0ac); | ||
266 | |||
267 | omap2_enter_full_retention(); | ||
268 | |||
269 | omap_writel(mir1, 0x480fe0a4); | ||
270 | omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); | ||
271 | |||
272 | return 0; | ||
273 | } | ||
274 | |||
275 | static int omap2_pm_enter(suspend_state_t state) | ||
276 | { | ||
277 | int ret = 0; | ||
278 | |||
279 | switch (state) { | ||
280 | case PM_SUSPEND_STANDBY: | ||
281 | case PM_SUSPEND_MEM: | ||
282 | ret = omap2_pm_suspend(); | ||
283 | break; | ||
284 | default: | ||
285 | ret = -EINVAL; | ||
286 | } | ||
287 | |||
288 | return ret; | ||
289 | } | ||
290 | |||
291 | static void omap2_pm_end(void) | ||
292 | { | ||
293 | suspend_state = PM_SUSPEND_ON; | ||
294 | enable_hlt(); | ||
295 | } | ||
296 | |||
297 | static const struct platform_suspend_ops omap_pm_ops = { | ||
298 | .begin = omap2_pm_begin, | ||
299 | .enter = omap2_pm_enter, | ||
300 | .end = omap2_pm_end, | ||
301 | .valid = suspend_valid_only_mem, | ||
302 | }; | ||
303 | #else | ||
304 | static const struct platform_suspend_ops __initdata omap_pm_ops; | ||
305 | #endif /* CONFIG_SUSPEND */ | ||
306 | |||
307 | /* XXX This function should be shareable between OMAP2xxx and OMAP3 */ | ||
308 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) | ||
309 | { | ||
310 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | ||
311 | clkdm_allow_idle(clkdm); | ||
312 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | ||
313 | atomic_read(&clkdm->usecount) == 0) | ||
314 | clkdm_sleep(clkdm); | ||
315 | return 0; | ||
316 | } | ||
317 | |||
318 | static void __init prcm_setup_regs(void) | 235 | static void __init prcm_setup_regs(void) |
319 | { | 236 | { |
320 | int i, num_mem_banks; | 237 | int i, num_mem_banks; |
@@ -356,9 +273,13 @@ static void __init prcm_setup_regs(void) | |||
356 | clkdm_sleep(gfx_clkdm); | 273 | clkdm_sleep(gfx_clkdm); |
357 | 274 | ||
358 | /* Enable hardware-supervised idle for all clkdms */ | 275 | /* Enable hardware-supervised idle for all clkdms */ |
359 | clkdm_for_each(clkdms_setup, NULL); | 276 | clkdm_for_each(omap_pm_clkdms_setup, NULL); |
360 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); | 277 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); |
361 | 278 | ||
279 | #ifdef CONFIG_SUSPEND | ||
280 | omap_pm_suspend = omap2_enter_full_retention; | ||
281 | #endif | ||
282 | |||
362 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk | 283 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk |
363 | * stabilisation */ | 284 | * stabilisation */ |
364 | omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, | 285 | omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
@@ -459,7 +380,6 @@ static int __init omap2_pm_init(void) | |||
459 | omap24xx_cpu_suspend_sz); | 380 | omap24xx_cpu_suspend_sz); |
460 | } | 381 | } |
461 | 382 | ||
462 | suspend_set_ops(&omap_pm_ops); | ||
463 | arm_pm_idle = omap2_pm_idle; | 383 | arm_pm_idle = omap2_pm_idle; |
464 | 384 | ||
465 | return 0; | 385 | return 0; |