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-rw-r--r--arch/arm/mach-omap2/pm-domain.c299
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diff --git a/arch/arm/mach-omap2/pm-domain.c b/arch/arm/mach-omap2/pm-domain.c
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1/*
2 * linux/arch/arm/mach-omap2/pm-domain.c
3 *
4 * Power domain functions for OMAP2
5 *
6 * Copyright (C) 2006 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
8 *
9 * Some code based on earlier OMAP2 sample PM code
10 * Copyright (C) 2005 Texas Instruments, Inc.
11 * Richard Woodruff <r-woodruff2@ti.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/clk.h>
21
22#include <asm/io.h>
23
24#include "prcm-regs.h"
25
26/* Power domain offsets */
27#define PM_MPU_OFFSET 0x100
28#define PM_CORE_OFFSET 0x200
29#define PM_GFX_OFFSET 0x300
30#define PM_WKUP_OFFSET 0x400 /* Autoidle only */
31#define PM_PLL_OFFSET 0x500 /* Autoidle only */
32#define PM_DSP_OFFSET 0x800
33#define PM_MDM_OFFSET 0xc00
34
35/* Power domain wake-up dependency control register */
36#define PM_WKDEP_OFFSET 0xc8
37#define EN_MDM (1 << 5)
38#define EN_WKUP (1 << 4)
39#define EN_GFX (1 << 3)
40#define EN_DSP (1 << 2)
41#define EN_MPU (1 << 1)
42#define EN_CORE (1 << 0)
43
44/* Core power domain state transition control register */
45#define PM_PWSTCTRL_OFFSET 0xe0
46#define FORCESTATE (1 << 18) /* Only for DSP & GFX */
47#define MEM4RETSTATE (1 << 6)
48#define MEM3RETSTATE (1 << 5)
49#define MEM2RETSTATE (1 << 4)
50#define MEM1RETSTATE (1 << 3)
51#define LOGICRETSTATE (1 << 2) /* Logic is retained */
52#define POWERSTATE_OFF 0x3
53#define POWERSTATE_RETENTION 0x1
54#define POWERSTATE_ON 0x0
55
56/* Power domain state register */
57#define PM_PWSTST_OFFSET 0xe4
58
59/* Hardware supervised state transition control register */
60#define CM_CLKSTCTRL_OFFSET 0x48
61#define AUTOSTAT_MPU (1 << 0) /* MPU */
62#define AUTOSTAT_DSS (1 << 2) /* Core */
63#define AUTOSTAT_L4 (1 << 1) /* Core */
64#define AUTOSTAT_L3 (1 << 0) /* Core */
65#define AUTOSTAT_GFX (1 << 0) /* GFX */
66#define AUTOSTAT_IVA (1 << 8) /* 2420 IVA in DSP domain */
67#define AUTOSTAT_DSP (1 << 0) /* DSP */
68#define AUTOSTAT_MDM (1 << 0) /* MDM */
69
70/* Automatic control of interface clock idling */
71#define CM_AUTOIDLE1_OFFSET 0x30
72#define CM_AUTOIDLE2_OFFSET 0x34 /* Core only */
73#define CM_AUTOIDLE3_OFFSET 0x38 /* Core only */
74#define CM_AUTOIDLE4_OFFSET 0x3c /* Core only */
75#define AUTO_54M(x) (((x) & 0x3) << 6)
76#define AUTO_96M(x) (((x) & 0x3) << 2)
77#define AUTO_DPLL(x) (((x) & 0x3) << 0)
78#define AUTO_STOPPED 0x3
79#define AUTO_BYPASS_FAST 0x2 /* DPLL only */
80#define AUTO_BYPASS_LOW_POWER 0x1 /* DPLL only */
81#define AUTO_DISABLED 0x0
82
83/* Voltage control PRCM_VOLTCTRL bits */
84#define AUTO_EXTVOLT (1 << 15)
85#define FORCE_EXTVOLT (1 << 14)
86#define SETOFF_LEVEL(x) (((x) & 0x3) << 12)
87#define MEMRETCTRL (1 << 8)
88#define SETRET_LEVEL(x) (((x) & 0x3) << 6)
89#define VOLT_LEVEL(x) (((x) & 0x3) << 0)
90
91#define OMAP24XX_PRCM_VBASE IO_ADDRESS(OMAP24XX_PRCM_BASE)
92#define prcm_readl(r) __raw_readl(OMAP24XX_PRCM_VBASE + (r))
93#define prcm_writel(v, r) __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
94
95static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
96{
97 return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
98}
99
100static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
101{
102 prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
103}
104
105static u32 pmdomain_get_powerstate(int domain_offset)
106{
107 return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
108}
109
110static void pmdomain_set_powerstate(u32 state, int domain_offset)
111{
112 prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
113}
114
115static u32 pmdomain_get_clock_autocontrol(int domain_offset)
116{
117 return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
118}
119
120static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
121{
122 prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
123}
124
125static u32 pmdomain_get_clock_autoidle1(int domain_offset)
126{
127 return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
128}
129
130/* Core domain only */
131static u32 pmdomain_get_clock_autoidle2(int domain_offset)
132{
133 return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
134}
135
136/* Core domain only */
137static u32 pmdomain_get_clock_autoidle3(int domain_offset)
138{
139 return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
140}
141
142/* Core domain only */
143static u32 pmdomain_get_clock_autoidle4(int domain_offset)
144{
145 return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
146}
147
148static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
149{
150 prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
151}
152
153/* Core domain only */
154static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
155{
156 prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
157}
158
159/* Core domain only */
160static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
161{
162 prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
163}
164
165/* Core domain only */
166static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
167{
168 prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
169}
170
171/*
172 * Configures power management domains to idle clocks automatically.
173 */
174void pmdomain_set_autoidle(void)
175{
176 u32 val;
177
178 /* Set PLL auto stop for 54M, 96M & DPLL */
179 pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
180 AUTO_96M(AUTO_STOPPED) |
181 AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
182
183 /* External clock input control
184 * REVISIT: Should this be in clock framework?
185 */
186 PRCM_CLKSRC_CTRL |= (0x3 << 3);
187
188 /* Configure number of 32KHz clock cycles for sys_clk */
189 PRCM_CLKSSETUP = 0x00ff;
190
191 /* Configure automatic voltage transition */
192 PRCM_VOLTSETUP = 0;
193 val = PRCM_VOLTCTRL;
194 val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
195 val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
196 PRCM_VOLTCTRL = val;
197
198 /* Disable emulation tools functional clock */
199 PRCM_CLKEMUL_CTRL = 0x0;
200
201 /* Set core memory retention state */
202 val = pmdomain_get_powerstate(PM_CORE_OFFSET);
203 if (cpu_is_omap2420()) {
204 val &= ~(0x7 << 3);
205 val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
206 } else {
207 val &= ~(0xf << 3);
208 val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
209 MEM1RETSTATE);
210 }
211 pmdomain_set_powerstate(val, PM_CORE_OFFSET);
212
213 /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
214 val = SMS_SYSCONFIG;
215 val &= ~(0x3 << 3);
216 val |= (0x2 << 3) | (1 << 0);
217 SMS_SYSCONFIG |= val;
218
219 val = SDRC_SYSCONFIG;
220 val &= ~(0x3 << 3);
221 val |= (0x2 << 3);
222 SDRC_SYSCONFIG = val;
223
224 /* Configure L3 interface for smart idle.
225 * REVISIT: Enable autoidle bit0 ?
226 */
227 val = GPMC_SYSCONFIG;
228 val &= ~(0x3 << 3);
229 val |= (0x2 << 3) | (1 << 0);
230 GPMC_SYSCONFIG = val;
231
232 pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
233 PM_MPU_OFFSET);
234 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
235 if (!cpu_is_omap2420())
236 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
237
238 /* Assume suspend function has saved the state for DSP and GFX */
239 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
240 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
241
242#if 0
243 /* REVISIT: Internal USB needs special handling */
244 force_standby_usb();
245 if (cpu_is_omap2430())
246 force_hsmmc();
247 sdram_self_refresh_on_idle_req(1);
248#endif
249
250 /* Enable clock auto control for all domains.
251 * Note that CORE domain includes also DSS, L4 & L3.
252 */
253 pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
254 pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
255 pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
256 PM_CORE_OFFSET);
257 if (cpu_is_omap2420())
258 pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
259 PM_DSP_OFFSET);
260 else {
261 pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
262 pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
263 }
264
265 /* Enable clock autoidle for all domains */
266 pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
267 if (cpu_is_omap2420()) {
268 pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
269 pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
270 pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
271 } else {
272 pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
273 pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
274 pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
275 pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
276 }
277 pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
278 pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
279}
280
281/*
282 * Initializes power domains by removing wake-up dependencies and powering
283 * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
284 * must re-enable DSP and GFX when used.
285 */
286void __init pmdomain_init(void)
287{
288 /* Remove all domain wakeup dependencies */
289 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
290 pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
291 pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
292 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
293 if (cpu_is_omap2430())
294 pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
295
296 /* Power down DSP and GFX */
297 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
298 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
299}
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