1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 9120e70aa08a..74c16434f2bc 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -36,14 +36,14 @@
 #define L3_TARG_STDERRLOG_SLVOFSLSB     0x5c
 #define L3_FLAGMUX_REGERR0              0xc
-u32 l3_flagmux[L3_MODULES] = {
+static u32 l3_flagmux[L3_MODULES] = {
        0x500,
        0x1000,
        0X0200
 };
 /* L3 Target standard Error register offsets */
-u32 l3_targ_inst_clk1[] = {
+static u32 l3_targ_inst_clk1[] = {
        0x100, /* DMM1 */
        0x200, /* DMM2 */
        0x300, /* ABE */
@@ -51,7 +51,7 @@ u32 l3_targ_inst_clk1[] = {
        0x600  /* CLK2 PWR DISC */
 };
-u32 l3_targ_inst_clk2[] = {
+static u32 l3_targ_inst_clk2[] = {
        0x500, /* CORTEX M3 */
        0x300, /* DSS */
        0x100, /* GPMC */
@@ -72,11 +72,11 @@ u32 l3_targ_inst_clk2[] = {
        0xB00 /* L4 PER2*/
 };
-u32 l3_targ_inst_clk3[] = {
+static u32 l3_targ_inst_clk3[] = {
        0x0100  /* EMUSS */
 };
-char *l3_targ_inst_name[L3_MODULES][18] = {
+static char *l3_targ_inst_name[L3_MODULES][18] = {
        {
                "DMM1",
                "DMM2",
@@ -109,7 +109,7 @@ char *l3_targ_inst_name[L3_MODULES][18] = {
        },
 };
-u32 *l3_targ[L3_MODULES] = {
+static u32 *l3_targ[L3_MODULES] = {
        l3_targ_inst_clk1,
        l3_targ_inst_clk2,
        l3_targ_inst_clk3,

diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h index 9120e70aa08a..74c16434f2bc 100644 --- a/arch/arm/mach-omap2/omap_l3_noc.h +++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -36,14 +36,14 @@
36	#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c	36	#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
37	#define L3_FLAGMUX_REGERR0 0xc	37	#define L3_FLAGMUX_REGERR0 0xc
38		38
39	u32 l3_flagmux[L3_MODULES] = {	39	static u32 l3_flagmux[L3_MODULES] = {
40	0x500,	40	0x500,
41	0x1000,	41	0x1000,
42	0X0200	42	0X0200
43	};	43	};
44		44
45	/* L3 Target standard Error register offsets */	45	/* L3 Target standard Error register offsets */
46	u32 l3_targ_inst_clk1[] = {	46	static u32 l3_targ_inst_clk1[] = {
47	0x100, /* DMM1 */	47	0x100, /* DMM1 */
48	0x200, /* DMM2 */	48	0x200, /* DMM2 */
49	0x300, /* ABE */	49	0x300, /* ABE */
@@ -51,7 +51,7 @@ u32 l3_targ_inst_clk1[] = {
51	0x600 /* CLK2 PWR DISC */	51	0x600 /* CLK2 PWR DISC */
52	};	52	};
53		53
54	u32 l3_targ_inst_clk2[] = {	54	static u32 l3_targ_inst_clk2[] = {
55	0x500, /* CORTEX M3 */	55	0x500, /* CORTEX M3 */
56	0x300, /* DSS */	56	0x300, /* DSS */
57	0x100, /* GPMC */	57	0x100, /* GPMC */
@@ -72,11 +72,11 @@ u32 l3_targ_inst_clk2[] = {
72	0xB00 /* L4 PER2*/	72	0xB00 /* L4 PER2*/
73	};	73	};
74		74
75	u32 l3_targ_inst_clk3[] = {	75	static u32 l3_targ_inst_clk3[] = {
76	0x0100 /* EMUSS */	76	0x0100 /* EMUSS */
77	};	77	};
78		78
79	char *l3_targ_inst_name[L3_MODULES][18] = {	79	static char *l3_targ_inst_name[L3_MODULES][18] = {
80	{	80	{
81	"DMM1",	81	"DMM1",
82	"DMM2",	82	"DMM2",
@@ -109,7 +109,7 @@ char *l3_targ_inst_name[L3_MODULES][18] = {
109	},	109	},
110	};	110	};
111		111
112	u32 *l3_targ[L3_MODULES] = {	112	static u32 *l3_targ[L3_MODULES] = {
113	l3_targ_inst_clk1,	113	l3_targ_inst_clk1,
114	l3_targ_inst_clk2,	114	l3_targ_inst_clk2,
115	l3_targ_inst_clk3,	115	l3_targ_inst_clk3,