diff options
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_44xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 127 |
1 files changed, 65 insertions, 62 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 81fd313bb1ad..bbfc4db664b3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -115,6 +115,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { | |||
115 | 115 | ||
116 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | 116 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { |
117 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | 117 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, |
118 | { .irq = -1 } | ||
118 | }; | 119 | }; |
119 | 120 | ||
120 | static struct omap_hwmod omap44xx_dmm_hwmod = { | 121 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
@@ -123,7 +124,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = { | |||
123 | .slaves = omap44xx_dmm_slaves, | 124 | .slaves = omap44xx_dmm_slaves, |
124 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), | 125 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), |
125 | .mpu_irqs = omap44xx_dmm_irqs, | 126 | .mpu_irqs = omap44xx_dmm_irqs, |
126 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), | ||
127 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 127 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
128 | }; | 128 | }; |
129 | 129 | ||
@@ -268,6 +268,7 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |||
268 | static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = { | 268 | static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = { |
269 | { .irq = 9 + OMAP44XX_IRQ_GIC_START }, | 269 | { .irq = 9 + OMAP44XX_IRQ_GIC_START }, |
270 | { .irq = 10 + OMAP44XX_IRQ_GIC_START }, | 270 | { .irq = 10 + OMAP44XX_IRQ_GIC_START }, |
271 | { .irq = -1 } | ||
271 | }; | 272 | }; |
272 | 273 | ||
273 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | 274 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { |
@@ -303,7 +304,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | |||
303 | .name = "l3_main_1", | 304 | .name = "l3_main_1", |
304 | .class = &omap44xx_l3_hwmod_class, | 305 | .class = &omap44xx_l3_hwmod_class, |
305 | .mpu_irqs = omap44xx_l3_targ_irqs, | 306 | .mpu_irqs = omap44xx_l3_targ_irqs, |
306 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs), | ||
307 | .slaves = omap44xx_l3_main_1_slaves, | 307 | .slaves = omap44xx_l3_main_1_slaves, |
308 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), | 308 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), |
309 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 309 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
@@ -672,6 +672,7 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |||
672 | /* aess */ | 672 | /* aess */ |
673 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | 673 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { |
674 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | 674 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, |
675 | { .irq = -1 } | ||
675 | }; | 676 | }; |
676 | 677 | ||
677 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | 678 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { |
@@ -736,7 +737,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = { | |||
736 | .name = "aess", | 737 | .name = "aess", |
737 | .class = &omap44xx_aess_hwmod_class, | 738 | .class = &omap44xx_aess_hwmod_class, |
738 | .mpu_irqs = omap44xx_aess_irqs, | 739 | .mpu_irqs = omap44xx_aess_irqs, |
739 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs), | ||
740 | .sdma_reqs = omap44xx_aess_sdma_reqs, | 740 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
741 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs), | 741 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs), |
742 | .main_clk = "aess_fck", | 742 | .main_clk = "aess_fck", |
@@ -875,6 +875,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |||
875 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | 875 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, |
876 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | 876 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, |
877 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | 877 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, |
878 | { .irq = -1 } | ||
878 | }; | 879 | }; |
879 | 880 | ||
880 | /* dma_system master ports */ | 881 | /* dma_system master ports */ |
@@ -909,7 +910,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { | |||
909 | .name = "dma_system", | 910 | .name = "dma_system", |
910 | .class = &omap44xx_dma_hwmod_class, | 911 | .class = &omap44xx_dma_hwmod_class, |
911 | .mpu_irqs = omap44xx_dma_system_irqs, | 912 | .mpu_irqs = omap44xx_dma_system_irqs, |
912 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs), | ||
913 | .main_clk = "l3_div_ck", | 913 | .main_clk = "l3_div_ck", |
914 | .prcm = { | 914 | .prcm = { |
915 | .omap4 = { | 915 | .omap4 = { |
@@ -948,6 +948,7 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |||
948 | static struct omap_hwmod omap44xx_dmic_hwmod; | 948 | static struct omap_hwmod omap44xx_dmic_hwmod; |
949 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { | 949 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
950 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | 950 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, |
951 | { .irq = -1 } | ||
951 | }; | 952 | }; |
952 | 953 | ||
953 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | 954 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { |
@@ -1000,7 +1001,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { | |||
1000 | .name = "dmic", | 1001 | .name = "dmic", |
1001 | .class = &omap44xx_dmic_hwmod_class, | 1002 | .class = &omap44xx_dmic_hwmod_class, |
1002 | .mpu_irqs = omap44xx_dmic_irqs, | 1003 | .mpu_irqs = omap44xx_dmic_irqs, |
1003 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs), | ||
1004 | .sdma_reqs = omap44xx_dmic_sdma_reqs, | 1004 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
1005 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs), | 1005 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs), |
1006 | .main_clk = "dmic_fck", | 1006 | .main_clk = "dmic_fck", |
@@ -1026,6 +1026,7 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |||
1026 | /* dsp */ | 1026 | /* dsp */ |
1027 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | 1027 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { |
1028 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | 1028 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, |
1029 | { .irq = -1 } | ||
1029 | }; | 1030 | }; |
1030 | 1031 | ||
1031 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | 1032 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { |
@@ -1082,7 +1083,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { | |||
1082 | .name = "dsp", | 1083 | .name = "dsp", |
1083 | .class = &omap44xx_dsp_hwmod_class, | 1084 | .class = &omap44xx_dsp_hwmod_class, |
1084 | .mpu_irqs = omap44xx_dsp_irqs, | 1085 | .mpu_irqs = omap44xx_dsp_irqs, |
1085 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs), | ||
1086 | .rst_lines = omap44xx_dsp_resets, | 1086 | .rst_lines = omap44xx_dsp_resets, |
1087 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | 1087 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), |
1088 | .main_clk = "dsp_fck", | 1088 | .main_clk = "dsp_fck", |
@@ -1215,6 +1215,7 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |||
1215 | static struct omap_hwmod omap44xx_dss_dispc_hwmod; | 1215 | static struct omap_hwmod omap44xx_dss_dispc_hwmod; |
1216 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { | 1216 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
1217 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | 1217 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, |
1218 | { .irq = -1 } | ||
1218 | }; | 1219 | }; |
1219 | 1220 | ||
1220 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | 1221 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { |
@@ -1267,7 +1268,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { | |||
1267 | .name = "dss_dispc", | 1268 | .name = "dss_dispc", |
1268 | .class = &omap44xx_dispc_hwmod_class, | 1269 | .class = &omap44xx_dispc_hwmod_class, |
1269 | .mpu_irqs = omap44xx_dss_dispc_irqs, | 1270 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
1270 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs), | ||
1271 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, | 1271 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
1272 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs), | 1272 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs), |
1273 | .main_clk = "dss_fck", | 1273 | .main_clk = "dss_fck", |
@@ -1306,6 +1306,7 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |||
1306 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod; | 1306 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod; |
1307 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { | 1307 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
1308 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | 1308 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, |
1309 | { .irq = -1 } | ||
1309 | }; | 1310 | }; |
1310 | 1311 | ||
1311 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | 1312 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { |
@@ -1358,7 +1359,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { | |||
1358 | .name = "dss_dsi1", | 1359 | .name = "dss_dsi1", |
1359 | .class = &omap44xx_dsi_hwmod_class, | 1360 | .class = &omap44xx_dsi_hwmod_class, |
1360 | .mpu_irqs = omap44xx_dss_dsi1_irqs, | 1361 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
1361 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs), | ||
1362 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, | 1362 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
1363 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs), | 1363 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs), |
1364 | .main_clk = "dss_fck", | 1364 | .main_clk = "dss_fck", |
@@ -1376,6 +1376,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { | |||
1376 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod; | 1376 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod; |
1377 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { | 1377 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
1378 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | 1378 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, |
1379 | { .irq = -1 } | ||
1379 | }; | 1380 | }; |
1380 | 1381 | ||
1381 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | 1382 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { |
@@ -1428,7 +1429,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { | |||
1428 | .name = "dss_dsi2", | 1429 | .name = "dss_dsi2", |
1429 | .class = &omap44xx_dsi_hwmod_class, | 1430 | .class = &omap44xx_dsi_hwmod_class, |
1430 | .mpu_irqs = omap44xx_dss_dsi2_irqs, | 1431 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
1431 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs), | ||
1432 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, | 1432 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
1433 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs), | 1433 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs), |
1434 | .main_clk = "dss_fck", | 1434 | .main_clk = "dss_fck", |
@@ -1466,6 +1466,7 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |||
1466 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod; | 1466 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod; |
1467 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { | 1467 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
1468 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | 1468 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, |
1469 | { .irq = -1 } | ||
1469 | }; | 1470 | }; |
1470 | 1471 | ||
1471 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | 1472 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { |
@@ -1518,7 +1519,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { | |||
1518 | .name = "dss_hdmi", | 1519 | .name = "dss_hdmi", |
1519 | .class = &omap44xx_hdmi_hwmod_class, | 1520 | .class = &omap44xx_hdmi_hwmod_class, |
1520 | .mpu_irqs = omap44xx_dss_hdmi_irqs, | 1521 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
1521 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs), | ||
1522 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, | 1522 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
1523 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs), | 1523 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs), |
1524 | .main_clk = "dss_fck", | 1524 | .main_clk = "dss_fck", |
@@ -1716,6 +1716,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { | |||
1716 | static struct omap_hwmod omap44xx_gpio1_hwmod; | 1716 | static struct omap_hwmod omap44xx_gpio1_hwmod; |
1717 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { | 1717 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
1718 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | 1718 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, |
1719 | { .irq = -1 } | ||
1719 | }; | 1720 | }; |
1720 | 1721 | ||
1721 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { | 1722 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
@@ -1749,7 +1750,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { | |||
1749 | .name = "gpio1", | 1750 | .name = "gpio1", |
1750 | .class = &omap44xx_gpio_hwmod_class, | 1751 | .class = &omap44xx_gpio_hwmod_class, |
1751 | .mpu_irqs = omap44xx_gpio1_irqs, | 1752 | .mpu_irqs = omap44xx_gpio1_irqs, |
1752 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), | ||
1753 | .main_clk = "gpio1_ick", | 1753 | .main_clk = "gpio1_ick", |
1754 | .prcm = { | 1754 | .prcm = { |
1755 | .omap4 = { | 1755 | .omap4 = { |
@@ -1768,6 +1768,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { | |||
1768 | static struct omap_hwmod omap44xx_gpio2_hwmod; | 1768 | static struct omap_hwmod omap44xx_gpio2_hwmod; |
1769 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { | 1769 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
1770 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | 1770 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, |
1771 | { .irq = -1 } | ||
1771 | }; | 1772 | }; |
1772 | 1773 | ||
1773 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | 1774 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { |
@@ -1802,7 +1803,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { | |||
1802 | .class = &omap44xx_gpio_hwmod_class, | 1803 | .class = &omap44xx_gpio_hwmod_class, |
1803 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1804 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
1804 | .mpu_irqs = omap44xx_gpio2_irqs, | 1805 | .mpu_irqs = omap44xx_gpio2_irqs, |
1805 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), | ||
1806 | .main_clk = "gpio2_ick", | 1806 | .main_clk = "gpio2_ick", |
1807 | .prcm = { | 1807 | .prcm = { |
1808 | .omap4 = { | 1808 | .omap4 = { |
@@ -1821,6 +1821,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { | |||
1821 | static struct omap_hwmod omap44xx_gpio3_hwmod; | 1821 | static struct omap_hwmod omap44xx_gpio3_hwmod; |
1822 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { | 1822 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
1823 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | 1823 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, |
1824 | { .irq = -1 } | ||
1824 | }; | 1825 | }; |
1825 | 1826 | ||
1826 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | 1827 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { |
@@ -1855,7 +1856,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { | |||
1855 | .class = &omap44xx_gpio_hwmod_class, | 1856 | .class = &omap44xx_gpio_hwmod_class, |
1856 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1857 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
1857 | .mpu_irqs = omap44xx_gpio3_irqs, | 1858 | .mpu_irqs = omap44xx_gpio3_irqs, |
1858 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), | ||
1859 | .main_clk = "gpio3_ick", | 1859 | .main_clk = "gpio3_ick", |
1860 | .prcm = { | 1860 | .prcm = { |
1861 | .omap4 = { | 1861 | .omap4 = { |
@@ -1874,6 +1874,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { | |||
1874 | static struct omap_hwmod omap44xx_gpio4_hwmod; | 1874 | static struct omap_hwmod omap44xx_gpio4_hwmod; |
1875 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { | 1875 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
1876 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | 1876 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, |
1877 | { .irq = -1 } | ||
1877 | }; | 1878 | }; |
1878 | 1879 | ||
1879 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | 1880 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { |
@@ -1908,7 +1909,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { | |||
1908 | .class = &omap44xx_gpio_hwmod_class, | 1909 | .class = &omap44xx_gpio_hwmod_class, |
1909 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1910 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
1910 | .mpu_irqs = omap44xx_gpio4_irqs, | 1911 | .mpu_irqs = omap44xx_gpio4_irqs, |
1911 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), | ||
1912 | .main_clk = "gpio4_ick", | 1912 | .main_clk = "gpio4_ick", |
1913 | .prcm = { | 1913 | .prcm = { |
1914 | .omap4 = { | 1914 | .omap4 = { |
@@ -1927,6 +1927,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { | |||
1927 | static struct omap_hwmod omap44xx_gpio5_hwmod; | 1927 | static struct omap_hwmod omap44xx_gpio5_hwmod; |
1928 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { | 1928 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
1929 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | 1929 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, |
1930 | { .irq = -1 } | ||
1930 | }; | 1931 | }; |
1931 | 1932 | ||
1932 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | 1933 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { |
@@ -1961,7 +1962,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { | |||
1961 | .class = &omap44xx_gpio_hwmod_class, | 1962 | .class = &omap44xx_gpio_hwmod_class, |
1962 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1963 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
1963 | .mpu_irqs = omap44xx_gpio5_irqs, | 1964 | .mpu_irqs = omap44xx_gpio5_irqs, |
1964 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), | ||
1965 | .main_clk = "gpio5_ick", | 1965 | .main_clk = "gpio5_ick", |
1966 | .prcm = { | 1966 | .prcm = { |
1967 | .omap4 = { | 1967 | .omap4 = { |
@@ -1980,6 +1980,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { | |||
1980 | static struct omap_hwmod omap44xx_gpio6_hwmod; | 1980 | static struct omap_hwmod omap44xx_gpio6_hwmod; |
1981 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { | 1981 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
1982 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | 1982 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, |
1983 | { .irq = -1 } | ||
1983 | }; | 1984 | }; |
1984 | 1985 | ||
1985 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | 1986 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { |
@@ -2014,7 +2015,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { | |||
2014 | .class = &omap44xx_gpio_hwmod_class, | 2015 | .class = &omap44xx_gpio_hwmod_class, |
2015 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 2016 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
2016 | .mpu_irqs = omap44xx_gpio6_irqs, | 2017 | .mpu_irqs = omap44xx_gpio6_irqs, |
2017 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), | ||
2018 | .main_clk = "gpio6_ick", | 2018 | .main_clk = "gpio6_ick", |
2019 | .prcm = { | 2019 | .prcm = { |
2020 | .omap4 = { | 2020 | .omap4 = { |
@@ -2058,6 +2058,7 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |||
2058 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | 2058 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, |
2059 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | 2059 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, |
2060 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | 2060 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, |
2061 | { .irq = -1 } | ||
2061 | }; | 2062 | }; |
2062 | 2063 | ||
2063 | /* hsi master ports */ | 2064 | /* hsi master ports */ |
@@ -2092,7 +2093,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { | |||
2092 | .name = "hsi", | 2093 | .name = "hsi", |
2093 | .class = &omap44xx_hsi_hwmod_class, | 2094 | .class = &omap44xx_hsi_hwmod_class, |
2094 | .mpu_irqs = omap44xx_hsi_irqs, | 2095 | .mpu_irqs = omap44xx_hsi_irqs, |
2095 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs), | ||
2096 | .main_clk = "hsi_fck", | 2096 | .main_clk = "hsi_fck", |
2097 | .prcm = { | 2097 | .prcm = { |
2098 | .omap4 = { | 2098 | .omap4 = { |
@@ -2131,6 +2131,7 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { | |||
2131 | static struct omap_hwmod omap44xx_i2c1_hwmod; | 2131 | static struct omap_hwmod omap44xx_i2c1_hwmod; |
2132 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | 2132 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
2133 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | 2133 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, |
2134 | { .irq = -1 } | ||
2134 | }; | 2135 | }; |
2135 | 2136 | ||
2136 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { | 2137 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
@@ -2166,7 +2167,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { | |||
2166 | .class = &omap44xx_i2c_hwmod_class, | 2167 | .class = &omap44xx_i2c_hwmod_class, |
2167 | .flags = HWMOD_INIT_NO_RESET, | 2168 | .flags = HWMOD_INIT_NO_RESET, |
2168 | .mpu_irqs = omap44xx_i2c1_irqs, | 2169 | .mpu_irqs = omap44xx_i2c1_irqs, |
2169 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), | ||
2170 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, | 2170 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
2171 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), | 2171 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), |
2172 | .main_clk = "i2c1_fck", | 2172 | .main_clk = "i2c1_fck", |
@@ -2184,6 +2184,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { | |||
2184 | static struct omap_hwmod omap44xx_i2c2_hwmod; | 2184 | static struct omap_hwmod omap44xx_i2c2_hwmod; |
2185 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | 2185 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
2186 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | 2186 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, |
2187 | { .irq = -1 } | ||
2187 | }; | 2188 | }; |
2188 | 2189 | ||
2189 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { | 2190 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
@@ -2219,7 +2220,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { | |||
2219 | .class = &omap44xx_i2c_hwmod_class, | 2220 | .class = &omap44xx_i2c_hwmod_class, |
2220 | .flags = HWMOD_INIT_NO_RESET, | 2221 | .flags = HWMOD_INIT_NO_RESET, |
2221 | .mpu_irqs = omap44xx_i2c2_irqs, | 2222 | .mpu_irqs = omap44xx_i2c2_irqs, |
2222 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), | ||
2223 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, | 2223 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
2224 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), | 2224 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), |
2225 | .main_clk = "i2c2_fck", | 2225 | .main_clk = "i2c2_fck", |
@@ -2237,6 +2237,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { | |||
2237 | static struct omap_hwmod omap44xx_i2c3_hwmod; | 2237 | static struct omap_hwmod omap44xx_i2c3_hwmod; |
2238 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | 2238 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
2239 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | 2239 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, |
2240 | { .irq = -1 } | ||
2240 | }; | 2241 | }; |
2241 | 2242 | ||
2242 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { | 2243 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
@@ -2272,7 +2273,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { | |||
2272 | .class = &omap44xx_i2c_hwmod_class, | 2273 | .class = &omap44xx_i2c_hwmod_class, |
2273 | .flags = HWMOD_INIT_NO_RESET, | 2274 | .flags = HWMOD_INIT_NO_RESET, |
2274 | .mpu_irqs = omap44xx_i2c3_irqs, | 2275 | .mpu_irqs = omap44xx_i2c3_irqs, |
2275 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), | ||
2276 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, | 2276 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
2277 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), | 2277 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), |
2278 | .main_clk = "i2c3_fck", | 2278 | .main_clk = "i2c3_fck", |
@@ -2290,6 +2290,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { | |||
2290 | static struct omap_hwmod omap44xx_i2c4_hwmod; | 2290 | static struct omap_hwmod omap44xx_i2c4_hwmod; |
2291 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | 2291 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
2292 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | 2292 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, |
2293 | { .irq = -1 } | ||
2293 | }; | 2294 | }; |
2294 | 2295 | ||
2295 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { | 2296 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
@@ -2325,7 +2326,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { | |||
2325 | .class = &omap44xx_i2c_hwmod_class, | 2326 | .class = &omap44xx_i2c_hwmod_class, |
2326 | .flags = HWMOD_INIT_NO_RESET, | 2327 | .flags = HWMOD_INIT_NO_RESET, |
2327 | .mpu_irqs = omap44xx_i2c4_irqs, | 2328 | .mpu_irqs = omap44xx_i2c4_irqs, |
2328 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), | ||
2329 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, | 2329 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
2330 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), | 2330 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), |
2331 | .main_clk = "i2c4_fck", | 2331 | .main_clk = "i2c4_fck", |
@@ -2351,6 +2351,7 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |||
2351 | /* ipu */ | 2351 | /* ipu */ |
2352 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | 2352 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { |
2353 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | 2353 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, |
2354 | { .irq = -1 } | ||
2354 | }; | 2355 | }; |
2355 | 2356 | ||
2356 | static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { | 2357 | static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { |
@@ -2417,7 +2418,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { | |||
2417 | .name = "ipu", | 2418 | .name = "ipu", |
2418 | .class = &omap44xx_ipu_hwmod_class, | 2419 | .class = &omap44xx_ipu_hwmod_class, |
2419 | .mpu_irqs = omap44xx_ipu_irqs, | 2420 | .mpu_irqs = omap44xx_ipu_irqs, |
2420 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs), | ||
2421 | .rst_lines = omap44xx_ipu_resets, | 2421 | .rst_lines = omap44xx_ipu_resets, |
2422 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | 2422 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), |
2423 | .main_clk = "ipu_fck", | 2423 | .main_clk = "ipu_fck", |
@@ -2458,6 +2458,7 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |||
2458 | /* iss */ | 2458 | /* iss */ |
2459 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | 2459 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { |
2460 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | 2460 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, |
2461 | { .irq = -1 } | ||
2461 | }; | 2462 | }; |
2462 | 2463 | ||
2463 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | 2464 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { |
@@ -2503,7 +2504,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = { | |||
2503 | .name = "iss", | 2504 | .name = "iss", |
2504 | .class = &omap44xx_iss_hwmod_class, | 2505 | .class = &omap44xx_iss_hwmod_class, |
2505 | .mpu_irqs = omap44xx_iss_irqs, | 2506 | .mpu_irqs = omap44xx_iss_irqs, |
2506 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs), | ||
2507 | .sdma_reqs = omap44xx_iss_sdma_reqs, | 2507 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
2508 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs), | 2508 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs), |
2509 | .main_clk = "iss_fck", | 2509 | .main_clk = "iss_fck", |
@@ -2535,6 +2535,7 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |||
2535 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | 2535 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, |
2536 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | 2536 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, |
2537 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | 2537 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, |
2538 | { .irq = -1 } | ||
2538 | }; | 2539 | }; |
2539 | 2540 | ||
2540 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | 2541 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { |
@@ -2613,7 +2614,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = { | |||
2613 | .name = "iva", | 2614 | .name = "iva", |
2614 | .class = &omap44xx_iva_hwmod_class, | 2615 | .class = &omap44xx_iva_hwmod_class, |
2615 | .mpu_irqs = omap44xx_iva_irqs, | 2616 | .mpu_irqs = omap44xx_iva_irqs, |
2616 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs), | ||
2617 | .rst_lines = omap44xx_iva_resets, | 2617 | .rst_lines = omap44xx_iva_resets, |
2618 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | 2618 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), |
2619 | .main_clk = "iva_fck", | 2619 | .main_clk = "iva_fck", |
@@ -2656,6 +2656,7 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |||
2656 | static struct omap_hwmod omap44xx_kbd_hwmod; | 2656 | static struct omap_hwmod omap44xx_kbd_hwmod; |
2657 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { | 2657 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
2658 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | 2658 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, |
2659 | { .irq = -1 } | ||
2659 | }; | 2660 | }; |
2660 | 2661 | ||
2661 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | 2662 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { |
@@ -2685,7 +2686,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { | |||
2685 | .name = "kbd", | 2686 | .name = "kbd", |
2686 | .class = &omap44xx_kbd_hwmod_class, | 2687 | .class = &omap44xx_kbd_hwmod_class, |
2687 | .mpu_irqs = omap44xx_kbd_irqs, | 2688 | .mpu_irqs = omap44xx_kbd_irqs, |
2688 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs), | ||
2689 | .main_clk = "kbd_fck", | 2689 | .main_clk = "kbd_fck", |
2690 | .prcm = { | 2690 | .prcm = { |
2691 | .omap4 = { | 2691 | .omap4 = { |
@@ -2721,6 +2721,7 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |||
2721 | static struct omap_hwmod omap44xx_mailbox_hwmod; | 2721 | static struct omap_hwmod omap44xx_mailbox_hwmod; |
2722 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { | 2722 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
2723 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | 2723 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, |
2724 | { .irq = -1 } | ||
2724 | }; | 2725 | }; |
2725 | 2726 | ||
2726 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | 2727 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { |
@@ -2750,7 +2751,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { | |||
2750 | .name = "mailbox", | 2751 | .name = "mailbox", |
2751 | .class = &omap44xx_mailbox_hwmod_class, | 2752 | .class = &omap44xx_mailbox_hwmod_class, |
2752 | .mpu_irqs = omap44xx_mailbox_irqs, | 2753 | .mpu_irqs = omap44xx_mailbox_irqs, |
2753 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs), | ||
2754 | .prcm = { | 2754 | .prcm = { |
2755 | .omap4 = { | 2755 | .omap4 = { |
2756 | .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, | 2756 | .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, |
@@ -2784,6 +2784,7 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |||
2784 | static struct omap_hwmod omap44xx_mcbsp1_hwmod; | 2784 | static struct omap_hwmod omap44xx_mcbsp1_hwmod; |
2785 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { | 2785 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
2786 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, | 2786 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, |
2787 | { .irq = -1 } | ||
2787 | }; | 2788 | }; |
2788 | 2789 | ||
2789 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | 2790 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { |
@@ -2839,7 +2840,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { | |||
2839 | .name = "mcbsp1", | 2840 | .name = "mcbsp1", |
2840 | .class = &omap44xx_mcbsp_hwmod_class, | 2841 | .class = &omap44xx_mcbsp_hwmod_class, |
2841 | .mpu_irqs = omap44xx_mcbsp1_irqs, | 2842 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
2842 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs), | ||
2843 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, | 2843 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
2844 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs), | 2844 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs), |
2845 | .main_clk = "mcbsp1_fck", | 2845 | .main_clk = "mcbsp1_fck", |
@@ -2857,6 +2857,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { | |||
2857 | static struct omap_hwmod omap44xx_mcbsp2_hwmod; | 2857 | static struct omap_hwmod omap44xx_mcbsp2_hwmod; |
2858 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { | 2858 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
2859 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, | 2859 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, |
2860 | { .irq = -1 } | ||
2860 | }; | 2861 | }; |
2861 | 2862 | ||
2862 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | 2863 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { |
@@ -2912,7 +2913,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { | |||
2912 | .name = "mcbsp2", | 2913 | .name = "mcbsp2", |
2913 | .class = &omap44xx_mcbsp_hwmod_class, | 2914 | .class = &omap44xx_mcbsp_hwmod_class, |
2914 | .mpu_irqs = omap44xx_mcbsp2_irqs, | 2915 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
2915 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs), | ||
2916 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, | 2916 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
2917 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs), | 2917 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs), |
2918 | .main_clk = "mcbsp2_fck", | 2918 | .main_clk = "mcbsp2_fck", |
@@ -2930,6 +2930,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { | |||
2930 | static struct omap_hwmod omap44xx_mcbsp3_hwmod; | 2930 | static struct omap_hwmod omap44xx_mcbsp3_hwmod; |
2931 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { | 2931 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
2932 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, | 2932 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, |
2933 | { .irq = -1 } | ||
2933 | }; | 2934 | }; |
2934 | 2935 | ||
2935 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | 2936 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { |
@@ -2985,7 +2986,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { | |||
2985 | .name = "mcbsp3", | 2986 | .name = "mcbsp3", |
2986 | .class = &omap44xx_mcbsp_hwmod_class, | 2987 | .class = &omap44xx_mcbsp_hwmod_class, |
2987 | .mpu_irqs = omap44xx_mcbsp3_irqs, | 2988 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
2988 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs), | ||
2989 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, | 2989 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
2990 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs), | 2990 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs), |
2991 | .main_clk = "mcbsp3_fck", | 2991 | .main_clk = "mcbsp3_fck", |
@@ -3003,6 +3003,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { | |||
3003 | static struct omap_hwmod omap44xx_mcbsp4_hwmod; | 3003 | static struct omap_hwmod omap44xx_mcbsp4_hwmod; |
3004 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { | 3004 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
3005 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, | 3005 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, |
3006 | { .irq = -1 } | ||
3006 | }; | 3007 | }; |
3007 | 3008 | ||
3008 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | 3009 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { |
@@ -3037,7 +3038,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { | |||
3037 | .name = "mcbsp4", | 3038 | .name = "mcbsp4", |
3038 | .class = &omap44xx_mcbsp_hwmod_class, | 3039 | .class = &omap44xx_mcbsp_hwmod_class, |
3039 | .mpu_irqs = omap44xx_mcbsp4_irqs, | 3040 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
3040 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs), | ||
3041 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, | 3041 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
3042 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs), | 3042 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs), |
3043 | .main_clk = "mcbsp4_fck", | 3043 | .main_clk = "mcbsp4_fck", |
@@ -3076,6 +3076,7 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |||
3076 | static struct omap_hwmod omap44xx_mcpdm_hwmod; | 3076 | static struct omap_hwmod omap44xx_mcpdm_hwmod; |
3077 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { | 3077 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
3078 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | 3078 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, |
3079 | { .irq = -1 } | ||
3079 | }; | 3080 | }; |
3080 | 3081 | ||
3081 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | 3082 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { |
@@ -3129,7 +3130,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { | |||
3129 | .name = "mcpdm", | 3130 | .name = "mcpdm", |
3130 | .class = &omap44xx_mcpdm_hwmod_class, | 3131 | .class = &omap44xx_mcpdm_hwmod_class, |
3131 | .mpu_irqs = omap44xx_mcpdm_irqs, | 3132 | .mpu_irqs = omap44xx_mcpdm_irqs, |
3132 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs), | ||
3133 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, | 3133 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
3134 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs), | 3134 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs), |
3135 | .main_clk = "mcpdm_fck", | 3135 | .main_clk = "mcpdm_fck", |
@@ -3169,6 +3169,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |||
3169 | static struct omap_hwmod omap44xx_mcspi1_hwmod; | 3169 | static struct omap_hwmod omap44xx_mcspi1_hwmod; |
3170 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { | 3170 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
3171 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | 3171 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, |
3172 | { .irq = -1 } | ||
3172 | }; | 3173 | }; |
3173 | 3174 | ||
3174 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | 3175 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { |
@@ -3214,7 +3215,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { | |||
3214 | .name = "mcspi1", | 3215 | .name = "mcspi1", |
3215 | .class = &omap44xx_mcspi_hwmod_class, | 3216 | .class = &omap44xx_mcspi_hwmod_class, |
3216 | .mpu_irqs = omap44xx_mcspi1_irqs, | 3217 | .mpu_irqs = omap44xx_mcspi1_irqs, |
3217 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs), | ||
3218 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, | 3218 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
3219 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs), | 3219 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs), |
3220 | .main_clk = "mcspi1_fck", | 3220 | .main_clk = "mcspi1_fck", |
@@ -3233,6 +3233,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { | |||
3233 | static struct omap_hwmod omap44xx_mcspi2_hwmod; | 3233 | static struct omap_hwmod omap44xx_mcspi2_hwmod; |
3234 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { | 3234 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
3235 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | 3235 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, |
3236 | { .irq = -1 } | ||
3236 | }; | 3237 | }; |
3237 | 3238 | ||
3238 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | 3239 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { |
@@ -3274,7 +3275,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { | |||
3274 | .name = "mcspi2", | 3275 | .name = "mcspi2", |
3275 | .class = &omap44xx_mcspi_hwmod_class, | 3276 | .class = &omap44xx_mcspi_hwmod_class, |
3276 | .mpu_irqs = omap44xx_mcspi2_irqs, | 3277 | .mpu_irqs = omap44xx_mcspi2_irqs, |
3277 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs), | ||
3278 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, | 3278 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
3279 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs), | 3279 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs), |
3280 | .main_clk = "mcspi2_fck", | 3280 | .main_clk = "mcspi2_fck", |
@@ -3293,6 +3293,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { | |||
3293 | static struct omap_hwmod omap44xx_mcspi3_hwmod; | 3293 | static struct omap_hwmod omap44xx_mcspi3_hwmod; |
3294 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { | 3294 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
3295 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | 3295 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, |
3296 | { .irq = -1 } | ||
3296 | }; | 3297 | }; |
3297 | 3298 | ||
3298 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | 3299 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { |
@@ -3334,7 +3335,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { | |||
3334 | .name = "mcspi3", | 3335 | .name = "mcspi3", |
3335 | .class = &omap44xx_mcspi_hwmod_class, | 3336 | .class = &omap44xx_mcspi_hwmod_class, |
3336 | .mpu_irqs = omap44xx_mcspi3_irqs, | 3337 | .mpu_irqs = omap44xx_mcspi3_irqs, |
3337 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs), | ||
3338 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, | 3338 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
3339 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs), | 3339 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs), |
3340 | .main_clk = "mcspi3_fck", | 3340 | .main_clk = "mcspi3_fck", |
@@ -3353,6 +3353,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { | |||
3353 | static struct omap_hwmod omap44xx_mcspi4_hwmod; | 3353 | static struct omap_hwmod omap44xx_mcspi4_hwmod; |
3354 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { | 3354 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
3355 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | 3355 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, |
3356 | { .irq = -1 } | ||
3356 | }; | 3357 | }; |
3357 | 3358 | ||
3358 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | 3359 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { |
@@ -3392,7 +3393,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { | |||
3392 | .name = "mcspi4", | 3393 | .name = "mcspi4", |
3393 | .class = &omap44xx_mcspi_hwmod_class, | 3394 | .class = &omap44xx_mcspi_hwmod_class, |
3394 | .mpu_irqs = omap44xx_mcspi4_irqs, | 3395 | .mpu_irqs = omap44xx_mcspi4_irqs, |
3395 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs), | ||
3396 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, | 3396 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
3397 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs), | 3397 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs), |
3398 | .main_clk = "mcspi4_fck", | 3398 | .main_clk = "mcspi4_fck", |
@@ -3433,6 +3433,7 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |||
3433 | 3433 | ||
3434 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | 3434 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { |
3435 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | 3435 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, |
3436 | { .irq = -1 } | ||
3436 | }; | 3437 | }; |
3437 | 3438 | ||
3438 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | 3439 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { |
@@ -3477,7 +3478,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { | |||
3477 | .name = "mmc1", | 3478 | .name = "mmc1", |
3478 | .class = &omap44xx_mmc_hwmod_class, | 3479 | .class = &omap44xx_mmc_hwmod_class, |
3479 | .mpu_irqs = omap44xx_mmc1_irqs, | 3480 | .mpu_irqs = omap44xx_mmc1_irqs, |
3480 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs), | ||
3481 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, | 3481 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
3482 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs), | 3482 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs), |
3483 | .main_clk = "mmc1_fck", | 3483 | .main_clk = "mmc1_fck", |
@@ -3497,6 +3497,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { | |||
3497 | /* mmc2 */ | 3497 | /* mmc2 */ |
3498 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | 3498 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { |
3499 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | 3499 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, |
3500 | { .irq = -1 } | ||
3500 | }; | 3501 | }; |
3501 | 3502 | ||
3502 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | 3503 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { |
@@ -3536,7 +3537,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { | |||
3536 | .name = "mmc2", | 3537 | .name = "mmc2", |
3537 | .class = &omap44xx_mmc_hwmod_class, | 3538 | .class = &omap44xx_mmc_hwmod_class, |
3538 | .mpu_irqs = omap44xx_mmc2_irqs, | 3539 | .mpu_irqs = omap44xx_mmc2_irqs, |
3539 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs), | ||
3540 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, | 3540 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
3541 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs), | 3541 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs), |
3542 | .main_clk = "mmc2_fck", | 3542 | .main_clk = "mmc2_fck", |
@@ -3556,6 +3556,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { | |||
3556 | static struct omap_hwmod omap44xx_mmc3_hwmod; | 3556 | static struct omap_hwmod omap44xx_mmc3_hwmod; |
3557 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { | 3557 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
3558 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | 3558 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, |
3559 | { .irq = -1 } | ||
3559 | }; | 3560 | }; |
3560 | 3561 | ||
3561 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | 3562 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { |
@@ -3590,7 +3591,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { | |||
3590 | .name = "mmc3", | 3591 | .name = "mmc3", |
3591 | .class = &omap44xx_mmc_hwmod_class, | 3592 | .class = &omap44xx_mmc_hwmod_class, |
3592 | .mpu_irqs = omap44xx_mmc3_irqs, | 3593 | .mpu_irqs = omap44xx_mmc3_irqs, |
3593 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs), | ||
3594 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, | 3594 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
3595 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs), | 3595 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs), |
3596 | .main_clk = "mmc3_fck", | 3596 | .main_clk = "mmc3_fck", |
@@ -3608,6 +3608,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { | |||
3608 | static struct omap_hwmod omap44xx_mmc4_hwmod; | 3608 | static struct omap_hwmod omap44xx_mmc4_hwmod; |
3609 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { | 3609 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
3610 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | 3610 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, |
3611 | { .irq = -1 } | ||
3611 | }; | 3612 | }; |
3612 | 3613 | ||
3613 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | 3614 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { |
@@ -3642,7 +3643,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { | |||
3642 | .name = "mmc4", | 3643 | .name = "mmc4", |
3643 | .class = &omap44xx_mmc_hwmod_class, | 3644 | .class = &omap44xx_mmc_hwmod_class, |
3644 | .mpu_irqs = omap44xx_mmc4_irqs, | 3645 | .mpu_irqs = omap44xx_mmc4_irqs, |
3645 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs), | 3646 | |
3646 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, | 3647 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
3647 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs), | 3648 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs), |
3648 | .main_clk = "mmc4_fck", | 3649 | .main_clk = "mmc4_fck", |
@@ -3660,6 +3661,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { | |||
3660 | static struct omap_hwmod omap44xx_mmc5_hwmod; | 3661 | static struct omap_hwmod omap44xx_mmc5_hwmod; |
3661 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { | 3662 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
3662 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | 3663 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, |
3664 | { .irq = -1 } | ||
3663 | }; | 3665 | }; |
3664 | 3666 | ||
3665 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | 3667 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { |
@@ -3694,7 +3696,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { | |||
3694 | .name = "mmc5", | 3696 | .name = "mmc5", |
3695 | .class = &omap44xx_mmc_hwmod_class, | 3697 | .class = &omap44xx_mmc_hwmod_class, |
3696 | .mpu_irqs = omap44xx_mmc5_irqs, | 3698 | .mpu_irqs = omap44xx_mmc5_irqs, |
3697 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs), | ||
3698 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, | 3699 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
3699 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs), | 3700 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs), |
3700 | .main_clk = "mmc5_fck", | 3701 | .main_clk = "mmc5_fck", |
@@ -3722,6 +3723,7 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |||
3722 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | 3723 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, |
3723 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | 3724 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, |
3724 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | 3725 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, |
3726 | { .irq = -1 } | ||
3725 | }; | 3727 | }; |
3726 | 3728 | ||
3727 | /* mpu master ports */ | 3729 | /* mpu master ports */ |
@@ -3736,7 +3738,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { | |||
3736 | .class = &omap44xx_mpu_hwmod_class, | 3738 | .class = &omap44xx_mpu_hwmod_class, |
3737 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 3739 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
3738 | .mpu_irqs = omap44xx_mpu_irqs, | 3740 | .mpu_irqs = omap44xx_mpu_irqs, |
3739 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), | ||
3740 | .main_clk = "dpll_mpu_m2_ck", | 3741 | .main_clk = "dpll_mpu_m2_ck", |
3741 | .prcm = { | 3742 | .prcm = { |
3742 | .omap4 = { | 3743 | .omap4 = { |
@@ -3778,6 +3779,7 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |||
3778 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod; | 3779 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod; |
3779 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { | 3780 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
3780 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | 3781 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, |
3782 | { .irq = -1 } | ||
3781 | }; | 3783 | }; |
3782 | 3784 | ||
3783 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { | 3785 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
@@ -3807,7 +3809,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { | |||
3807 | .name = "smartreflex_core", | 3809 | .name = "smartreflex_core", |
3808 | .class = &omap44xx_smartreflex_hwmod_class, | 3810 | .class = &omap44xx_smartreflex_hwmod_class, |
3809 | .mpu_irqs = omap44xx_smartreflex_core_irqs, | 3811 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
3810 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), | 3812 | |
3811 | .main_clk = "smartreflex_core_fck", | 3813 | .main_clk = "smartreflex_core_fck", |
3812 | .vdd_name = "core", | 3814 | .vdd_name = "core", |
3813 | .prcm = { | 3815 | .prcm = { |
@@ -3824,6 +3826,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { | |||
3824 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; | 3826 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; |
3825 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { | 3827 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
3826 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | 3828 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, |
3829 | { .irq = -1 } | ||
3827 | }; | 3830 | }; |
3828 | 3831 | ||
3829 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | 3832 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { |
@@ -3853,7 +3856,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { | |||
3853 | .name = "smartreflex_iva", | 3856 | .name = "smartreflex_iva", |
3854 | .class = &omap44xx_smartreflex_hwmod_class, | 3857 | .class = &omap44xx_smartreflex_hwmod_class, |
3855 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, | 3858 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
3856 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs), | ||
3857 | .main_clk = "smartreflex_iva_fck", | 3859 | .main_clk = "smartreflex_iva_fck", |
3858 | .vdd_name = "iva", | 3860 | .vdd_name = "iva", |
3859 | .prcm = { | 3861 | .prcm = { |
@@ -3870,6 +3872,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { | |||
3870 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; | 3872 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; |
3871 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { | 3873 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
3872 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | 3874 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, |
3875 | { .irq = -1 } | ||
3873 | }; | 3876 | }; |
3874 | 3877 | ||
3875 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | 3878 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { |
@@ -3899,7 +3902,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { | |||
3899 | .name = "smartreflex_mpu", | 3902 | .name = "smartreflex_mpu", |
3900 | .class = &omap44xx_smartreflex_hwmod_class, | 3903 | .class = &omap44xx_smartreflex_hwmod_class, |
3901 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, | 3904 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
3902 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs), | ||
3903 | .main_clk = "smartreflex_mpu_fck", | 3905 | .main_clk = "smartreflex_mpu_fck", |
3904 | .vdd_name = "mpu", | 3906 | .vdd_name = "mpu", |
3905 | .prcm = { | 3907 | .prcm = { |
@@ -4015,6 +4017,7 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |||
4015 | static struct omap_hwmod omap44xx_timer1_hwmod; | 4017 | static struct omap_hwmod omap44xx_timer1_hwmod; |
4016 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { | 4018 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
4017 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | 4019 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, |
4020 | { .irq = -1 } | ||
4018 | }; | 4021 | }; |
4019 | 4022 | ||
4020 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | 4023 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { |
@@ -4044,7 +4047,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { | |||
4044 | .name = "timer1", | 4047 | .name = "timer1", |
4045 | .class = &omap44xx_timer_1ms_hwmod_class, | 4048 | .class = &omap44xx_timer_1ms_hwmod_class, |
4046 | .mpu_irqs = omap44xx_timer1_irqs, | 4049 | .mpu_irqs = omap44xx_timer1_irqs, |
4047 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), | ||
4048 | .main_clk = "timer1_fck", | 4050 | .main_clk = "timer1_fck", |
4049 | .prcm = { | 4051 | .prcm = { |
4050 | .omap4 = { | 4052 | .omap4 = { |
@@ -4060,6 +4062,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { | |||
4060 | static struct omap_hwmod omap44xx_timer2_hwmod; | 4062 | static struct omap_hwmod omap44xx_timer2_hwmod; |
4061 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { | 4063 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
4062 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | 4064 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, |
4065 | { .irq = -1 } | ||
4063 | }; | 4066 | }; |
4064 | 4067 | ||
4065 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | 4068 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { |
@@ -4089,7 +4092,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { | |||
4089 | .name = "timer2", | 4092 | .name = "timer2", |
4090 | .class = &omap44xx_timer_1ms_hwmod_class, | 4093 | .class = &omap44xx_timer_1ms_hwmod_class, |
4091 | .mpu_irqs = omap44xx_timer2_irqs, | 4094 | .mpu_irqs = omap44xx_timer2_irqs, |
4092 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs), | ||
4093 | .main_clk = "timer2_fck", | 4095 | .main_clk = "timer2_fck", |
4094 | .prcm = { | 4096 | .prcm = { |
4095 | .omap4 = { | 4097 | .omap4 = { |
@@ -4105,6 +4107,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { | |||
4105 | static struct omap_hwmod omap44xx_timer3_hwmod; | 4107 | static struct omap_hwmod omap44xx_timer3_hwmod; |
4106 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { | 4108 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
4107 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | 4109 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, |
4110 | { .irq = -1 } | ||
4108 | }; | 4111 | }; |
4109 | 4112 | ||
4110 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | 4113 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { |
@@ -4134,7 +4137,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { | |||
4134 | .name = "timer3", | 4137 | .name = "timer3", |
4135 | .class = &omap44xx_timer_hwmod_class, | 4138 | .class = &omap44xx_timer_hwmod_class, |
4136 | .mpu_irqs = omap44xx_timer3_irqs, | 4139 | .mpu_irqs = omap44xx_timer3_irqs, |
4137 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs), | ||
4138 | .main_clk = "timer3_fck", | 4140 | .main_clk = "timer3_fck", |
4139 | .prcm = { | 4141 | .prcm = { |
4140 | .omap4 = { | 4142 | .omap4 = { |
@@ -4150,6 +4152,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { | |||
4150 | static struct omap_hwmod omap44xx_timer4_hwmod; | 4152 | static struct omap_hwmod omap44xx_timer4_hwmod; |
4151 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { | 4153 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
4152 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | 4154 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, |
4155 | { .irq = -1 } | ||
4153 | }; | 4156 | }; |
4154 | 4157 | ||
4155 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | 4158 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { |
@@ -4179,7 +4182,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { | |||
4179 | .name = "timer4", | 4182 | .name = "timer4", |
4180 | .class = &omap44xx_timer_hwmod_class, | 4183 | .class = &omap44xx_timer_hwmod_class, |
4181 | .mpu_irqs = omap44xx_timer4_irqs, | 4184 | .mpu_irqs = omap44xx_timer4_irqs, |
4182 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs), | ||
4183 | .main_clk = "timer4_fck", | 4185 | .main_clk = "timer4_fck", |
4184 | .prcm = { | 4186 | .prcm = { |
4185 | .omap4 = { | 4187 | .omap4 = { |
@@ -4195,6 +4197,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { | |||
4195 | static struct omap_hwmod omap44xx_timer5_hwmod; | 4197 | static struct omap_hwmod omap44xx_timer5_hwmod; |
4196 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { | 4198 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
4197 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | 4199 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, |
4200 | { .irq = -1 } | ||
4198 | }; | 4201 | }; |
4199 | 4202 | ||
4200 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | 4203 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { |
@@ -4243,7 +4246,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { | |||
4243 | .name = "timer5", | 4246 | .name = "timer5", |
4244 | .class = &omap44xx_timer_hwmod_class, | 4247 | .class = &omap44xx_timer_hwmod_class, |
4245 | .mpu_irqs = omap44xx_timer5_irqs, | 4248 | .mpu_irqs = omap44xx_timer5_irqs, |
4246 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs), | ||
4247 | .main_clk = "timer5_fck", | 4249 | .main_clk = "timer5_fck", |
4248 | .prcm = { | 4250 | .prcm = { |
4249 | .omap4 = { | 4251 | .omap4 = { |
@@ -4259,6 +4261,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { | |||
4259 | static struct omap_hwmod omap44xx_timer6_hwmod; | 4261 | static struct omap_hwmod omap44xx_timer6_hwmod; |
4260 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { | 4262 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
4261 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | 4263 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, |
4264 | { .irq = -1 } | ||
4262 | }; | 4265 | }; |
4263 | 4266 | ||
4264 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | 4267 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { |
@@ -4307,7 +4310,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { | |||
4307 | .name = "timer6", | 4310 | .name = "timer6", |
4308 | .class = &omap44xx_timer_hwmod_class, | 4311 | .class = &omap44xx_timer_hwmod_class, |
4309 | .mpu_irqs = omap44xx_timer6_irqs, | 4312 | .mpu_irqs = omap44xx_timer6_irqs, |
4310 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs), | 4313 | |
4311 | .main_clk = "timer6_fck", | 4314 | .main_clk = "timer6_fck", |
4312 | .prcm = { | 4315 | .prcm = { |
4313 | .omap4 = { | 4316 | .omap4 = { |
@@ -4323,6 +4326,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { | |||
4323 | static struct omap_hwmod omap44xx_timer7_hwmod; | 4326 | static struct omap_hwmod omap44xx_timer7_hwmod; |
4324 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { | 4327 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
4325 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | 4328 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, |
4329 | { .irq = -1 } | ||
4326 | }; | 4330 | }; |
4327 | 4331 | ||
4328 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | 4332 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { |
@@ -4371,7 +4375,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { | |||
4371 | .name = "timer7", | 4375 | .name = "timer7", |
4372 | .class = &omap44xx_timer_hwmod_class, | 4376 | .class = &omap44xx_timer_hwmod_class, |
4373 | .mpu_irqs = omap44xx_timer7_irqs, | 4377 | .mpu_irqs = omap44xx_timer7_irqs, |
4374 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs), | ||
4375 | .main_clk = "timer7_fck", | 4378 | .main_clk = "timer7_fck", |
4376 | .prcm = { | 4379 | .prcm = { |
4377 | .omap4 = { | 4380 | .omap4 = { |
@@ -4387,6 +4390,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { | |||
4387 | static struct omap_hwmod omap44xx_timer8_hwmod; | 4390 | static struct omap_hwmod omap44xx_timer8_hwmod; |
4388 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { | 4391 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
4389 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | 4392 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, |
4393 | { .irq = -1 } | ||
4390 | }; | 4394 | }; |
4391 | 4395 | ||
4392 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | 4396 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { |
@@ -4435,7 +4439,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { | |||
4435 | .name = "timer8", | 4439 | .name = "timer8", |
4436 | .class = &omap44xx_timer_hwmod_class, | 4440 | .class = &omap44xx_timer_hwmod_class, |
4437 | .mpu_irqs = omap44xx_timer8_irqs, | 4441 | .mpu_irqs = omap44xx_timer8_irqs, |
4438 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs), | ||
4439 | .main_clk = "timer8_fck", | 4442 | .main_clk = "timer8_fck", |
4440 | .prcm = { | 4443 | .prcm = { |
4441 | .omap4 = { | 4444 | .omap4 = { |
@@ -4451,6 +4454,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { | |||
4451 | static struct omap_hwmod omap44xx_timer9_hwmod; | 4454 | static struct omap_hwmod omap44xx_timer9_hwmod; |
4452 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { | 4455 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
4453 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | 4456 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, |
4457 | { .irq = -1 } | ||
4454 | }; | 4458 | }; |
4455 | 4459 | ||
4456 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | 4460 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { |
@@ -4480,7 +4484,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { | |||
4480 | .name = "timer9", | 4484 | .name = "timer9", |
4481 | .class = &omap44xx_timer_hwmod_class, | 4485 | .class = &omap44xx_timer_hwmod_class, |
4482 | .mpu_irqs = omap44xx_timer9_irqs, | 4486 | .mpu_irqs = omap44xx_timer9_irqs, |
4483 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs), | ||
4484 | .main_clk = "timer9_fck", | 4487 | .main_clk = "timer9_fck", |
4485 | .prcm = { | 4488 | .prcm = { |
4486 | .omap4 = { | 4489 | .omap4 = { |
@@ -4496,6 +4499,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { | |||
4496 | static struct omap_hwmod omap44xx_timer10_hwmod; | 4499 | static struct omap_hwmod omap44xx_timer10_hwmod; |
4497 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { | 4500 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
4498 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | 4501 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, |
4502 | { .irq = -1 } | ||
4499 | }; | 4503 | }; |
4500 | 4504 | ||
4501 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | 4505 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { |
@@ -4525,7 +4529,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { | |||
4525 | .name = "timer10", | 4529 | .name = "timer10", |
4526 | .class = &omap44xx_timer_1ms_hwmod_class, | 4530 | .class = &omap44xx_timer_1ms_hwmod_class, |
4527 | .mpu_irqs = omap44xx_timer10_irqs, | 4531 | .mpu_irqs = omap44xx_timer10_irqs, |
4528 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs), | ||
4529 | .main_clk = "timer10_fck", | 4532 | .main_clk = "timer10_fck", |
4530 | .prcm = { | 4533 | .prcm = { |
4531 | .omap4 = { | 4534 | .omap4 = { |
@@ -4541,6 +4544,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { | |||
4541 | static struct omap_hwmod omap44xx_timer11_hwmod; | 4544 | static struct omap_hwmod omap44xx_timer11_hwmod; |
4542 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { | 4545 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
4543 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | 4546 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, |
4547 | { .irq = -1 } | ||
4544 | }; | 4548 | }; |
4545 | 4549 | ||
4546 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | 4550 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { |
@@ -4570,7 +4574,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { | |||
4570 | .name = "timer11", | 4574 | .name = "timer11", |
4571 | .class = &omap44xx_timer_hwmod_class, | 4575 | .class = &omap44xx_timer_hwmod_class, |
4572 | .mpu_irqs = omap44xx_timer11_irqs, | 4576 | .mpu_irqs = omap44xx_timer11_irqs, |
4573 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs), | ||
4574 | .main_clk = "timer11_fck", | 4577 | .main_clk = "timer11_fck", |
4575 | .prcm = { | 4578 | .prcm = { |
4576 | .omap4 = { | 4579 | .omap4 = { |
@@ -4608,6 +4611,7 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = { | |||
4608 | static struct omap_hwmod omap44xx_uart1_hwmod; | 4611 | static struct omap_hwmod omap44xx_uart1_hwmod; |
4609 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { | 4612 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
4610 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | 4613 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, |
4614 | { .irq = -1 } | ||
4611 | }; | 4615 | }; |
4612 | 4616 | ||
4613 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { | 4617 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
@@ -4642,7 +4646,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { | |||
4642 | .name = "uart1", | 4646 | .name = "uart1", |
4643 | .class = &omap44xx_uart_hwmod_class, | 4647 | .class = &omap44xx_uart_hwmod_class, |
4644 | .mpu_irqs = omap44xx_uart1_irqs, | 4648 | .mpu_irqs = omap44xx_uart1_irqs, |
4645 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), | ||
4646 | .sdma_reqs = omap44xx_uart1_sdma_reqs, | 4649 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
4647 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), | 4650 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), |
4648 | .main_clk = "uart1_fck", | 4651 | .main_clk = "uart1_fck", |
@@ -4660,6 +4663,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { | |||
4660 | static struct omap_hwmod omap44xx_uart2_hwmod; | 4663 | static struct omap_hwmod omap44xx_uart2_hwmod; |
4661 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { | 4664 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
4662 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | 4665 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, |
4666 | { .irq = -1 } | ||
4663 | }; | 4667 | }; |
4664 | 4668 | ||
4665 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { | 4669 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
@@ -4694,7 +4698,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { | |||
4694 | .name = "uart2", | 4698 | .name = "uart2", |
4695 | .class = &omap44xx_uart_hwmod_class, | 4699 | .class = &omap44xx_uart_hwmod_class, |
4696 | .mpu_irqs = omap44xx_uart2_irqs, | 4700 | .mpu_irqs = omap44xx_uart2_irqs, |
4697 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), | ||
4698 | .sdma_reqs = omap44xx_uart2_sdma_reqs, | 4701 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
4699 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), | 4702 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), |
4700 | .main_clk = "uart2_fck", | 4703 | .main_clk = "uart2_fck", |
@@ -4712,6 +4715,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { | |||
4712 | static struct omap_hwmod omap44xx_uart3_hwmod; | 4715 | static struct omap_hwmod omap44xx_uart3_hwmod; |
4713 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { | 4716 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
4714 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | 4717 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, |
4718 | { .irq = -1 } | ||
4715 | }; | 4719 | }; |
4716 | 4720 | ||
4717 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { | 4721 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
@@ -4747,7 +4751,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { | |||
4747 | .class = &omap44xx_uart_hwmod_class, | 4751 | .class = &omap44xx_uart_hwmod_class, |
4748 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 4752 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
4749 | .mpu_irqs = omap44xx_uart3_irqs, | 4753 | .mpu_irqs = omap44xx_uart3_irqs, |
4750 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), | ||
4751 | .sdma_reqs = omap44xx_uart3_sdma_reqs, | 4754 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
4752 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), | 4755 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), |
4753 | .main_clk = "uart3_fck", | 4756 | .main_clk = "uart3_fck", |
@@ -4765,6 +4768,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { | |||
4765 | static struct omap_hwmod omap44xx_uart4_hwmod; | 4768 | static struct omap_hwmod omap44xx_uart4_hwmod; |
4766 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { | 4769 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
4767 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | 4770 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, |
4771 | { .irq = -1 } | ||
4768 | }; | 4772 | }; |
4769 | 4773 | ||
4770 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { | 4774 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
@@ -4799,7 +4803,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { | |||
4799 | .name = "uart4", | 4803 | .name = "uart4", |
4800 | .class = &omap44xx_uart_hwmod_class, | 4804 | .class = &omap44xx_uart_hwmod_class, |
4801 | .mpu_irqs = omap44xx_uart4_irqs, | 4805 | .mpu_irqs = omap44xx_uart4_irqs, |
4802 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), | ||
4803 | .sdma_reqs = omap44xx_uart4_sdma_reqs, | 4806 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
4804 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), | 4807 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), |
4805 | .main_clk = "uart4_fck", | 4808 | .main_clk = "uart4_fck", |
@@ -4840,6 +4843,7 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |||
4840 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | 4843 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { |
4841 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | 4844 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, |
4842 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | 4845 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, |
4846 | { .irq = -1 } | ||
4843 | }; | 4847 | }; |
4844 | 4848 | ||
4845 | /* usb_otg_hs master ports */ | 4849 | /* usb_otg_hs master ports */ |
@@ -4879,7 +4883,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |||
4879 | .class = &omap44xx_usb_otg_hs_hwmod_class, | 4883 | .class = &omap44xx_usb_otg_hs_hwmod_class, |
4880 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | 4884 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
4881 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | 4885 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, |
4882 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs), | ||
4883 | .main_clk = "usb_otg_hs_ick", | 4886 | .main_clk = "usb_otg_hs_ick", |
4884 | .prcm = { | 4887 | .prcm = { |
4885 | .omap4 = { | 4888 | .omap4 = { |
@@ -4922,6 +4925,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { | |||
4922 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; | 4925 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; |
4923 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | 4926 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
4924 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | 4927 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, |
4928 | { .irq = -1 } | ||
4925 | }; | 4929 | }; |
4926 | 4930 | ||
4927 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | 4931 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
@@ -4951,7 +4955,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { | |||
4951 | .name = "wd_timer2", | 4955 | .name = "wd_timer2", |
4952 | .class = &omap44xx_wd_timer_hwmod_class, | 4956 | .class = &omap44xx_wd_timer_hwmod_class, |
4953 | .mpu_irqs = omap44xx_wd_timer2_irqs, | 4957 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
4954 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), | ||
4955 | .main_clk = "wd_timer2_fck", | 4958 | .main_clk = "wd_timer2_fck", |
4956 | .prcm = { | 4959 | .prcm = { |
4957 | .omap4 = { | 4960 | .omap4 = { |
@@ -4967,6 +4970,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { | |||
4967 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; | 4970 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; |
4968 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | 4971 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
4969 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | 4972 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, |
4973 | { .irq = -1 } | ||
4970 | }; | 4974 | }; |
4971 | 4975 | ||
4972 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | 4976 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
@@ -5015,7 +5019,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |||
5015 | .name = "wd_timer3", | 5019 | .name = "wd_timer3", |
5016 | .class = &omap44xx_wd_timer_hwmod_class, | 5020 | .class = &omap44xx_wd_timer_hwmod_class, |
5017 | .mpu_irqs = omap44xx_wd_timer3_irqs, | 5021 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
5018 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), | ||
5019 | .main_clk = "wd_timer3_fck", | 5022 | .main_clk = "wd_timer3_fck", |
5020 | .prcm = { | 5023 | .prcm = { |
5021 | .omap4 = { | 5024 | .omap4 = { |