1 files changed, 92 insertions, 2 deletions

diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index beecfdd56ea3..bc16c818c6b7 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -15,18 +15,73 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/memblock.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/map.h>
 
 #include <plat/irqs.h>
+#include <plat/sram.h>
 
 #include <mach/hardware.h>
+#include <mach/omap-wakeupgen.h>
 
 #include "common.h"
+#include "omap4-sar-layout.h"
 
 #ifdef CONFIG_CACHE_L2X0
-void __iomem *l2cache_base;
+static void __iomem *l2cache_base;
+#endif
+
+static void __iomem *sar_ram_base;
+
+#ifdef CONFIG_OMAP4_ERRATA_I688
+/* Used to implement memory barrier on DRAM path */
+#define OMAP4_DRAM_BARRIER_VA                   0xfe600000
+
+void __iomem *dram_sync, *sram_sync;
+
+void omap_bus_sync(void)
+{
+        if (dram_sync && sram_sync) {
+                writel_relaxed(readl_relaxed(dram_sync), dram_sync);
+                writel_relaxed(readl_relaxed(sram_sync), sram_sync);
+                isb();
+        }
+}
+
+static int __init omap_barriers_init(void)
+{
+        struct map_desc dram_io_desc[1];
+        phys_addr_t paddr;
+        u32 size;
+
+        if (!cpu_is_omap44xx())
+                return -ENODEV;
+
+        size = ALIGN(PAGE_SIZE, SZ_1M);
+        paddr = memblock_alloc(size, SZ_1M);
+        if (!paddr) {
+                pr_err("%s: failed to reserve 4 Kbytes\n", __func__);
+                return -ENOMEM;
+        }
+        memblock_free(paddr, size);
+        memblock_remove(paddr, size);
+        dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
+        dram_io_desc[0].pfn = __phys_to_pfn(paddr);
+        dram_io_desc[0].length = size;
+        dram_io_desc[0].type = MT_MEMORY_SO;
+        iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
+        dram_sync = (void __iomem *) dram_io_desc[0].virtual;
+        sram_sync = (void __iomem *) OMAP4_SRAM_VA;
+
+        pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
+                (long long) paddr, dram_io_desc[0].virtual);
+
+        return 0;
+}
+core_initcall(omap_barriers_init);
 #endif
 
 void __init gic_init_irq(void)
@@ -42,11 +97,18 @@ void __init gic_init_irq(void)
         omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
         BUG_ON(!omap_irq_base);
 
+        omap_wakeupgen_init();
+
         gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
 }
 
 #ifdef CONFIG_CACHE_L2X0
 
+void __iomem *omap4_get_l2cache_base(void)
+{
+        return l2cache_base;
+}
+
 static void omap4_l2x0_disable(void)
 {
         /* Disable PL310 L2 Cache controller */
@@ -72,7 +134,8 @@ static int __init omap_l2_cache_init(void)
 
         /* Static mapping, never released */
         l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
-        BUG_ON(!l2cache_base);
+        if (WARN_ON(!l2cache_base))
+                return -ENOMEM;
 
         /*
          * 16-way associativity, parity disabled
@@ -112,3 +175,30 @@ static int __init omap_l2_cache_init(void)
 }
 early_initcall(omap_l2_cache_init);
 #endif
+
+void __iomem *omap4_get_sar_ram_base(void)
+{
+        return sar_ram_base;
+}
+
+/*
+ * SAR RAM used to save and restore the HW
+ * context in low power modes
+ */
+static int __init omap4_sar_ram_init(void)
+{
+        /*
+         * To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!cpu_is_omap44xx())
+                return -ENOMEM;
+
+        /* Static mapping, never released */
+        sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
+        if (WARN_ON(!sar_ram_base))
+                return -ENOMEM;
+
+        return 0;
+}
+early_initcall(omap4_sar_ram_init);