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-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 503ac777a2ba..502e3135aad3 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -19,6 +19,27 @@
19#include <linux/init.h> 19#include <linux/init.h>
20 20
21 __CPUINIT 21 __CPUINIT
22
23/* Physical address needed since MMU not enabled yet on secondary core */
24#define AUX_CORE_BOOT0_PA 0x48281800
25
26/*
27 * OMAP5 specific entry point for secondary CPU to jump from ROM
28 * code. This routine also provides a holding flag into which
29 * secondary core is held until we're ready for it to initialise.
30 * The primary core will update this flag using a hardware
31+ * register AuxCoreBoot0.
32 */
33ENTRY(omap5_secondary_startup)
34wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
35 ldr r0, [r2]
36 mov r0, r0, lsr #5
37 mrc p15, 0, r4, c0, c0, 5
38 and r4, r4, #0x0f
39 cmp r0, r4
40 bne wait
41 b secondary_startup
42END(omap5_secondary_startup)
22/* 43/*
23 * OMAP4 specific entry point for secondary CPU to jump from ROM 44 * OMAP4 specific entry point for secondary CPU to jump from ROM
24 * code. This routine also provides a holding flag into which 45 * code. This routine also provides a holding flag into which