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-rw-r--r--arch/arm/mach-omap2/mux.c338
1 files changed, 25 insertions, 313 deletions
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 8b3d26935a39..ab403b2ed26b 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -37,12 +37,12 @@
37#include <asm/system.h> 37#include <asm/system.h>
38 38
39#include <plat/control.h> 39#include <plat/control.h>
40#include <plat/mux.h>
41 40
42#include "mux.h" 41#include "mux.h"
43 42
44#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ 43#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
45#define OMAP_MUX_BASE_SZ 0x5ca 44#define OMAP_MUX_BASE_SZ 0x5ca
45#define MUXABLE_GPIO_MODE3 BIT(0)
46 46
47struct omap_mux_entry { 47struct omap_mux_entry {
48 struct omap_mux mux; 48 struct omap_mux mux;
@@ -51,6 +51,7 @@ struct omap_mux_entry {
51 51
52static unsigned long mux_phys; 52static unsigned long mux_phys;
53static void __iomem *mux_base; 53static void __iomem *mux_base;
54static u8 omap_mux_flags;
54 55
55u16 omap_mux_read(u16 reg) 56u16 omap_mux_read(u16 reg)
56{ 57{
@@ -76,301 +77,6 @@ void omap_mux_write_array(struct omap_board_mux *board_mux)
76 } 77 }
77} 78}
78 79
79#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX)
80
81static struct omap_mux_cfg arch_mux_cfg;
82
83/* NOTE: See mux.h for the enumeration */
84
85static struct pin_config __initdata_or_module omap24xx_pins[] = {
86/*
87 * description mux mux pull pull debug
88 * offset mode ena type
89 */
90
91/* 24xx I2C */
92MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1)
93MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1)
94MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 1, 1)
95MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1)
96
97/* Menelaus interrupt */
98MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
99
100/* 24xx clocks */
101MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1)
102
103/* 24xx GPMC chipselects, wait pin monitoring */
104MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1)
105MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1)
106MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1)
107MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1)
108MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1)
109MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1)
110
111/* 24xx McBSP */
112MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1)
113MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1)
114MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1)
115MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1)
116
117/* 24xx GPIO */
118MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1)
119MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1)
120MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1)
121MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1)
122MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1)
123MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1)
124MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1)
125MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
126MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
127MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
128MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1)
129MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
130MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1)
131MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1)
132MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1)
133MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1)
134MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1)
135MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
136MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1)
137
138/* 242x DBG GPIO */
139MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1)
140MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1)
141MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1)
142MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1)
143MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1)
144MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1)
145MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1)
146MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1)
147MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1)
148MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1)
149
150/* 24xx external DMA requests */
151MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1)
152MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1)
153MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1)
154MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1)
155MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
156MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
157
158/* UART3 */
159MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
160MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
161
162/* MMC/SDIO */
163MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1)
164MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1)
165MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1)
166MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1)
167MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1)
168MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1)
169MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1)
170MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1)
171MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1)
172MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1)
173MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1)
174MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1)
175
176/* Full speed USB */
177MUX_CFG_24XX("J20_24XX_USB0_PUEN", 0x11d, 0, 0, 0, 1)
178MUX_CFG_24XX("J19_24XX_USB0_VP", 0x11e, 0, 0, 0, 1)
179MUX_CFG_24XX("K20_24XX_USB0_VM", 0x11f, 0, 0, 0, 1)
180MUX_CFG_24XX("J18_24XX_USB0_RCV", 0x120, 0, 0, 0, 1)
181MUX_CFG_24XX("K19_24XX_USB0_TXEN", 0x121, 0, 0, 0, 1)
182MUX_CFG_24XX("J14_24XX_USB0_SE0", 0x122, 0, 0, 0, 1)
183MUX_CFG_24XX("K18_24XX_USB0_DAT", 0x123, 0, 0, 0, 1)
184
185MUX_CFG_24XX("N14_24XX_USB1_SE0", 0x0ed, 2, 0, 0, 1)
186MUX_CFG_24XX("W12_24XX_USB1_SE0", 0x0dd, 3, 0, 0, 1)
187MUX_CFG_24XX("P15_24XX_USB1_DAT", 0x0ee, 2, 0, 0, 1)
188MUX_CFG_24XX("R13_24XX_USB1_DAT", 0x0e0, 3, 0, 0, 1)
189MUX_CFG_24XX("W20_24XX_USB1_TXEN", 0x0ec, 2, 0, 0, 1)
190MUX_CFG_24XX("P13_24XX_USB1_TXEN", 0x0df, 3, 0, 0, 1)
191MUX_CFG_24XX("V19_24XX_USB1_RCV", 0x0eb, 2, 0, 0, 1)
192MUX_CFG_24XX("V12_24XX_USB1_RCV", 0x0de, 3, 0, 0, 1)
193
194MUX_CFG_24XX("AA10_24XX_USB2_SE0", 0x0e5, 2, 0, 0, 1)
195MUX_CFG_24XX("Y11_24XX_USB2_DAT", 0x0e8, 2, 0, 0, 1)
196MUX_CFG_24XX("AA12_24XX_USB2_TXEN", 0x0e9, 2, 0, 0, 1)
197MUX_CFG_24XX("AA6_24XX_USB2_RCV", 0x0e6, 2, 0, 0, 1)
198MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0", 0x0e7, 2, 0, 0, 1)
199
200/* Keypad GPIO*/
201MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1)
202MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1)
203MUX_CFG_24XX("V18_24XX_KBR2", 0x139, 3, 1, 1, 1)
204MUX_CFG_24XX("M21_24XX_KBR3", 0xc9, 3, 1, 1, 1)
205MUX_CFG_24XX("E5__24XX_KBR4", 0x138, 3, 1, 1, 1)
206MUX_CFG_24XX("M18_24XX_KBR5", 0x10e, 3, 1, 1, 1)
207MUX_CFG_24XX("R20_24XX_KBC0", 0x108, 3, 0, 0, 1)
208MUX_CFG_24XX("M14_24XX_KBC1", 0x109, 3, 0, 0, 1)
209MUX_CFG_24XX("H19_24XX_KBC2", 0x114, 3, 0, 0, 1)
210MUX_CFG_24XX("V17_24XX_KBC3", 0x135, 3, 0, 0, 1)
211MUX_CFG_24XX("P21_24XX_KBC4", 0xca, 3, 0, 0, 1)
212MUX_CFG_24XX("L14_24XX_KBC5", 0x10f, 3, 0, 0, 1)
213MUX_CFG_24XX("N19_24XX_KBC6", 0x110, 3, 0, 0, 1)
214
215/* 24xx Menelaus Keypad GPIO */
216MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1)
217MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1)
218MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
219
220/* 2430 USB */
221MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1)
222MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1)
223MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1)
224MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1)
225MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1)
226MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1)
227MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1)
228MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1)
229MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1)
230MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1)
231MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1)
232
233/* 2430 HS-USB */
234MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1)
235MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1)
236MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1)
237MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1)
238MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1)
239MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1)
240MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1)
241MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1)
242MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1)
243MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1)
244MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1)
245MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1)
246
247/* 2430 McBSP */
248MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1)
249
250MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1)
251MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1)
252MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1)
253MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1)
254MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1)
255MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1)
256
257MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1)
258MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1)
259MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1)
260MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1)
261MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1)
262MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1)
263MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1)
264MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
265
266MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1)
267MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1)
268MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1)
269MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1)
270
271MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1)
272MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1)
273MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1)
274MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1)
275
276MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1)
277MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1)
278MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1)
279MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1)
280
281/* 2430 MCSPI1 */
282MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1)
283MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1)
284MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1)
285MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1)
286
287/* Touchscreen GPIO */
288MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1)
289
290};
291
292#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins)
293
294#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
295
296static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
297{
298 u16 orig;
299 u8 warn = 0, debug = 0;
300
301 orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
302
303#ifdef CONFIG_OMAP_MUX_DEBUG
304 debug = cfg->debug;
305#endif
306 warn = (orig != reg);
307 if (debug || warn)
308 printk(KERN_WARNING
309 "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
310 cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
311 orig, reg);
312}
313#else
314#define omap2_cfg_debug(x, y) do {} while (0)
315#endif
316
317static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
318{
319 static DEFINE_SPINLOCK(mux_spin_lock);
320 unsigned long flags;
321 u8 reg = 0;
322
323 spin_lock_irqsave(&mux_spin_lock, flags);
324 reg |= cfg->mask & 0x7;
325 if (cfg->pull_val)
326 reg |= OMAP2_PULL_ENA;
327 if (cfg->pu_pd_val)
328 reg |= OMAP2_PULL_UP;
329 omap2_cfg_debug(cfg, reg);
330 omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
331 spin_unlock_irqrestore(&mux_spin_lock, flags);
332
333 return 0;
334}
335
336int __init omap2_mux_init(void)
337{
338 u32 mux_pbase;
339
340 if (cpu_is_omap2420())
341 mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
342 else if (cpu_is_omap2430())
343 mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
344 else
345 return -ENODEV;
346
347 mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
348 if (!mux_base) {
349 printk(KERN_ERR "mux: Could not ioremap\n");
350 return -ENODEV;
351 }
352
353 if (cpu_is_omap24xx()) {
354 arch_mux_cfg.pins = omap24xx_pins;
355 arch_mux_cfg.size = OMAP24XX_PINS_SZ;
356 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
357
358 return omap_mux_register(&arch_mux_cfg);
359 }
360
361 return 0;
362}
363
364#else
365int __init omap2_mux_init(void)
366{
367 return 0;
368}
369#endif /* CONFIG_OMAP_MUX */
370
371/*----------------------------------------------------------------------------*/
372
373#ifdef CONFIG_ARCH_OMAP3
374static LIST_HEAD(muxmodes); 80static LIST_HEAD(muxmodes);
375static DEFINE_MUTEX(muxmode_mutex); 81static DEFINE_MUTEX(muxmode_mutex);
376 82
@@ -381,6 +87,9 @@ static char *omap_mux_options;
381int __init omap_mux_init_gpio(int gpio, int val) 87int __init omap_mux_init_gpio(int gpio, int val)
382{ 88{
383 struct omap_mux_entry *e; 89 struct omap_mux_entry *e;
90 struct omap_mux *gpio_mux;
91 u16 old_mode;
92 u16 mux_mode;
384 int found = 0; 93 int found = 0;
385 94
386 if (!gpio) 95 if (!gpio)
@@ -389,31 +98,33 @@ int __init omap_mux_init_gpio(int gpio, int val)
389 list_for_each_entry(e, &muxmodes, node) { 98 list_for_each_entry(e, &muxmodes, node) {
390 struct omap_mux *m = &e->mux; 99 struct omap_mux *m = &e->mux;
391 if (gpio == m->gpio) { 100 if (gpio == m->gpio) {
392 u16 old_mode; 101 gpio_mux = m;
393 u16 mux_mode;
394
395 old_mode = omap_mux_read(m->reg_offset);
396 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
397 mux_mode |= OMAP_MUX_MODE4;
398 printk(KERN_DEBUG "mux: Setting signal "
399 "%s.gpio%i 0x%04x -> 0x%04x\n",
400 m->muxnames[0], gpio, old_mode, mux_mode);
401 omap_mux_write(mux_mode, m->reg_offset);
402 found++; 102 found++;
403 } 103 }
404 } 104 }
405 105
406 if (found == 1) 106 if (found == 0) {
407 return 0; 107 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
108 return -ENODEV;
109 }
408 110
409 if (found > 1) { 111 if (found > 1) {
410 printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio); 112 printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n",
113 found, gpio);
411 return -EINVAL; 114 return -EINVAL;
412 } 115 }
413 116
414 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); 117 old_mode = omap_mux_read(gpio_mux->reg_offset);
118 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
119 if (omap_mux_flags & MUXABLE_GPIO_MODE3)
120 mux_mode |= OMAP_MUX_MODE3;
121 else
122 mux_mode |= OMAP_MUX_MODE4;
123 printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n",
124 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
125 omap_mux_write(mux_mode, gpio_mux->reg_offset);
415 126
416 return -ENODEV; 127 return 0;
417} 128}
418 129
419int __init omap_mux_init_signal(char *muxname, int val) 130int __init omap_mux_init_signal(char *muxname, int val)
@@ -1032,6 +743,9 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
1032 return -ENODEV; 743 return -ENODEV;
1033 } 744 }
1034 745
746 if (cpu_is_omap24xx())
747 omap_mux_flags = MUXABLE_GPIO_MODE3;
748
1035 omap_mux_init_package(superset, package_subset, package_balls); 749 omap_mux_init_package(superset, package_subset, package_balls);
1036 omap_mux_init_list(superset); 750 omap_mux_init_list(superset);
1037 omap_mux_init_signals(board_mux); 751 omap_mux_init_signals(board_mux);
@@ -1039,5 +753,3 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
1039 return 0; 753 return 0;
1040} 754}
1041 755
1042#endif /* CONFIG_ARCH_OMAP3 */
1043
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 07:14:38 -0500