1 files changed, 48 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 85cbc2a2e663..f173aa8d896f 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -30,6 +30,38 @@
 #include "prcm-regs.h"
 #include "memory.h"
 
+#define SMS_BASE                0x68008000
+#define SMS_SYSCONFIG           0x010
+
+#define SDRC_BASE               0x68009000
+#define SDRC_SYSCONFIG          0x010
+#define SDRC_SYSSTATUS          0x014
+
+static const u32 sms_base = IO_ADDRESS(SMS_BASE);
+static const u32 sdrc_base = IO_ADDRESS(SDRC_BASE);
+
+
+static inline void sms_write_reg(int idx, u32 val)
+{
+        __raw_writel(val, sms_base + idx);
+}
+
+static inline u32 sms_read_reg(int idx)
+{
+        return __raw_readl(sms_base + idx);
+}
+
+static inline void sdrc_write_reg(int idx, u32 val)
+{
+        __raw_writel(val, sdrc_base + idx);
+}
+
+static inline u32 sdrc_read_reg(int idx)
+{
+        return __raw_readl(sdrc_base + idx);
+}
+
+
 static struct memory_timings mem_timings;
 
 u32 omap2_memory_get_slow_dll_ctrl(void)
@@ -99,3 +131,19 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
         /* 90 degree phase for anything below 133Mhz + disable DLL filter */
         mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 }
+
+void __init omap2_init_memory(void)
+{
+        u32 l;
+
+        l = sms_read_reg(SMS_SYSCONFIG);
+        l &= ~(0x3 << 3);
+        l |= (0x2 << 3);
+        sms_write_reg(SMS_SYSCONFIG, l);
+
+        l = sdrc_read_reg(SDRC_SYSCONFIG);
+        l &= ~(0x3 << 3);
+        l |= (0x2 << 3);
+        sdrc_write_reg(SDRC_SYSCONFIG, l);
+
+}