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-rw-r--r--arch/arm/mach-omap2/io.c107
1 files changed, 59 insertions, 48 deletions
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5a7996402c53..402e8f0d0f21 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -35,7 +35,9 @@
35#include <plat/serial.h> 35#include <plat/serial.h>
36#include <plat/vram.h> 36#include <plat/vram.h>
37 37
38#include "clock.h" 38#include "clock2xxx.h"
39#include "clock3xxx.h"
40#include "clock44xx.h"
39 41
40#include <plat/omap-pm.h> 42#include <plat/omap-pm.h>
41#include <plat/powerdomain.h> 43#include <plat/powerdomain.h>
@@ -44,16 +46,13 @@
44#include <plat/clockdomain.h> 46#include <plat/clockdomain.h>
45#include "clockdomains.h" 47#include "clockdomains.h"
46#include <plat/omap_hwmod.h> 48#include <plat/omap_hwmod.h>
47#include "omap_hwmod_2420.h"
48#include "omap_hwmod_2430.h"
49#include "omap_hwmod_34xx.h"
50 49
51/* 50/*
52 * The machine specific code may provide the extra mapping besides the 51 * The machine specific code may provide the extra mapping besides the
53 * default mapping provided here. 52 * default mapping provided here.
54 */ 53 */
55 54
56#ifdef CONFIG_ARCH_OMAP24XX 55#ifdef CONFIG_ARCH_OMAP2
57static struct map_desc omap24xx_io_desc[] __initdata = { 56static struct map_desc omap24xx_io_desc[] __initdata = {
58 { 57 {
59 .virtual = L3_24XX_VIRT, 58 .virtual = L3_24XX_VIRT,
@@ -123,7 +122,7 @@ static struct map_desc omap243x_io_desc[] __initdata = {
123#endif 122#endif
124#endif 123#endif
125 124
126#ifdef CONFIG_ARCH_OMAP34XX 125#ifdef CONFIG_ARCH_OMAP3
127static struct map_desc omap34xx_io_desc[] __initdata = { 126static struct map_desc omap34xx_io_desc[] __initdata = {
128 { 127 {
129 .virtual = L3_34XX_VIRT, 128 .virtual = L3_34XX_VIRT,
@@ -138,12 +137,6 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
138 .type = MT_DEVICE 137 .type = MT_DEVICE
139 }, 138 },
140 { 139 {
141 .virtual = L4_WK_34XX_VIRT,
142 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
143 .length = L4_WK_34XX_SIZE,
144 .type = MT_DEVICE
145 },
146 {
147 .virtual = OMAP34XX_GPMC_VIRT, 140 .virtual = OMAP34XX_GPMC_VIRT,
148 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 141 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
149 .length = OMAP34XX_GPMC_SIZE, 142 .length = OMAP34XX_GPMC_SIZE,
@@ -190,12 +183,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
190 .type = MT_DEVICE, 183 .type = MT_DEVICE,
191 }, 184 },
192 { 185 {
193 .virtual = L4_WK_44XX_VIRT,
194 .pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
195 .length = L4_WK_44XX_SIZE,
196 .type = MT_DEVICE,
197 },
198 {
199 .virtual = OMAP44XX_GPMC_VIRT, 186 .virtual = OMAP44XX_GPMC_VIRT,
200 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), 187 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
201 .length = OMAP44XX_GPMC_SIZE, 188 .length = OMAP44XX_GPMC_SIZE,
@@ -234,37 +221,54 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
234}; 221};
235#endif 222#endif
236 223
237void __init omap2_map_common_io(void) 224static void __init _omap2_map_common_io(void)
225{
226 /* Normally devicemaps_init() would flush caches and tlb after
227 * mdesc->map_io(), but we must also do it here because of the CPU
228 * revision check below.
229 */
230 local_flush_tlb_all();
231 flush_cache_all();
232
233 omap2_check_revision();
234 omap_sram_init();
235 omapfb_reserve_sdram();
236 omap_vram_reserve_sdram();
237}
238
239#ifdef CONFIG_ARCH_OMAP2420
240void __init omap242x_map_common_io()
238{ 241{
239#if defined(CONFIG_ARCH_OMAP2420)
240 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 242 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
241 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 243 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
244 _omap2_map_common_io();
245}
242#endif 246#endif
243 247
244#if defined(CONFIG_ARCH_OMAP2430) 248#ifdef CONFIG_ARCH_OMAP2430
249void __init omap243x_map_common_io()
250{
245 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 251 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
246 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 252 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
253 _omap2_map_common_io();
254}
247#endif 255#endif
248 256
249#if defined(CONFIG_ARCH_OMAP34XX) 257#ifdef CONFIG_ARCH_OMAP3
258void __init omap34xx_map_common_io()
259{
250 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 260 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
261 _omap2_map_common_io();
262}
251#endif 263#endif
252 264
253#if defined(CONFIG_ARCH_OMAP4) 265#ifdef CONFIG_ARCH_OMAP4
266void __init omap44xx_map_common_io()
267{
254 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 268 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
255#endif 269 _omap2_map_common_io();
256 /* Normally devicemaps_init() would flush caches and tlb after
257 * mdesc->map_io(), but we must also do it here because of the CPU
258 * revision check below.
259 */
260 local_flush_tlb_all();
261 flush_cache_all();
262
263 omap2_check_revision();
264 omap_sram_init();
265 omapfb_reserve_sdram();
266 omap_vram_reserve_sdram();
267} 270}
271#endif
268 272
269/* 273/*
270 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 274 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
@@ -303,24 +307,31 @@ static int __init _omap2_init_reprogram_sdrc(void)
303void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, 307void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
304 struct omap_sdrc_params *sdrc_cs1) 308 struct omap_sdrc_params *sdrc_cs1)
305{ 309{
306 struct omap_hwmod **hwmods = NULL; 310 pwrdm_init(powerdomains_omap);
311 clkdm_init(clockdomains_omap, clkdm_autodeps);
312#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
313 if (cpu_is_omap242x())
314 omap2420_hwmod_init();
315 else if (cpu_is_omap243x())
316 omap2430_hwmod_init();
317 else if (cpu_is_omap34xx())
318 omap3xxx_hwmod_init();
319 omap2_mux_init();
320 /* The OPP tables have to be registered before a clk init */
321 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
322#endif
307 323
308 if (cpu_is_omap2420()) 324 if (cpu_is_omap2420())
309 hwmods = omap2420_hwmods; 325 omap2420_clk_init();
310 else if (cpu_is_omap2430()) 326 else if (cpu_is_omap2430())
311 hwmods = omap2430_hwmods; 327 omap2430_clk_init();
312 else if (cpu_is_omap34xx()) 328 else if (cpu_is_omap34xx())
313 hwmods = omap34xx_hwmods; 329 omap3xxx_clk_init();
330 else if (cpu_is_omap44xx())
331 omap4xxx_clk_init();
332 else
333 pr_err("Could not init clock framework - unknown CPU\n");
314 334
315#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
316 /* The OPP tables have to be registered before a clk init */
317 omap_hwmod_init(hwmods);
318 omap2_mux_init();
319 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
320 pwrdm_init(powerdomains_omap);
321 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
322#endif
323 omap2_clk_init();
324 omap_serial_early_init(); 335 omap_serial_early_init();
325#ifndef CONFIG_ARCH_OMAP4 336#ifndef CONFIG_ARCH_OMAP4
326 omap_hwmod_late_init(); 337 omap_hwmod_late_init();