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-rw-r--r--arch/arm/mach-omap2/id.c34
1 files changed, 30 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41d4749..2dc62a25f2c3 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -55,7 +55,7 @@ int omap_type(void)
55 55
56 if (cpu_is_omap24xx()) { 56 if (cpu_is_omap24xx()) {
57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
58 } else if (soc_is_am33xx()) { 58 } else if (soc_is_am33xx() || soc_is_am43xx()) {
59 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); 59 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
60 } else if (cpu_is_omap34xx()) { 60 } else if (cpu_is_omap34xx()) {
61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
@@ -209,6 +209,8 @@ static void __init omap3_cpuinfo(void)
209 cpu_name = "TI816X"; 209 cpu_name = "TI816X";
210 } else if (soc_is_am335x()) { 210 } else if (soc_is_am335x()) {
211 cpu_name = "AM335X"; 211 cpu_name = "AM335X";
212 } else if (soc_is_am437x()) {
213 cpu_name = "AM437x";
212 } else if (cpu_is_ti814x()) { 214 } else if (cpu_is_ti814x()) {
213 cpu_name = "TI814X"; 215 cpu_name = "TI814X";
214 } else if (omap3_has_iva() && omap3_has_sgx()) { 216 } else if (omap3_has_iva() && omap3_has_sgx()) {
@@ -302,6 +304,19 @@ void __init ti81xx_check_features(void)
302 omap3_cpuinfo(); 304 omap3_cpuinfo();
303} 305}
304 306
307void __init am33xx_check_features(void)
308{
309 u32 status;
310
311 omap_features = OMAP3_HAS_NEON;
312
313 status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
314 if (status & AM33XX_SGX_MASK)
315 omap_features |= OMAP3_HAS_SGX;
316
317 omap3_cpuinfo();
318}
319
305void __init omap3xxx_check_revision(void) 320void __init omap3xxx_check_revision(void)
306{ 321{
307 const char *cpu_rev; 322 const char *cpu_rev;
@@ -405,11 +420,18 @@ void __init omap3xxx_check_revision(void)
405 cpu_rev = "1.0"; 420 cpu_rev = "1.0";
406 break; 421 break;
407 case 1: 422 case 1:
408 /* FALLTHROUGH */
409 default:
410 omap_revision = TI8168_REV_ES1_1; 423 omap_revision = TI8168_REV_ES1_1;
411 cpu_rev = "1.1"; 424 cpu_rev = "1.1";
412 break; 425 break;
426 case 2:
427 omap_revision = TI8168_REV_ES2_0;
428 cpu_rev = "2.0";
429 break;
430 case 3:
431 /* FALLTHROUGH */
432 default:
433 omap_revision = TI8168_REV_ES2_1;
434 cpu_rev = "2.1";
413 } 435 }
414 break; 436 break;
415 case 0xb944: 437 case 0xb944:
@@ -430,6 +452,10 @@ void __init omap3xxx_check_revision(void)
430 break; 452 break;
431 } 453 }
432 break; 454 break;
455 case 0xb98c:
456 omap_revision = AM437X_REV_ES1_0;
457 cpu_rev = "1.0";
458 break;
433 case 0xb8f2: 459 case 0xb8f2:
434 switch (rev) { 460 switch (rev) {
435 case 0: 461 case 0:
@@ -601,7 +627,7 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
601 627
602#ifdef CONFIG_SOC_BUS 628#ifdef CONFIG_SOC_BUS
603 629
604static const char const *omap_types[] = { 630static const char * const omap_types[] = {
605 [OMAP2_DEVICE_TYPE_TEST] = "TST", 631 [OMAP2_DEVICE_TYPE_TEST] = "TST",
606 [OMAP2_DEVICE_TYPE_EMU] = "EMU", 632 [OMAP2_DEVICE_TYPE_EMU] = "EMU",
607 [OMAP2_DEVICE_TYPE_SEC] = "HS", 633 [OMAP2_DEVICE_TYPE_SEC] = "HS",