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-rw-r--r--arch/arm/mach-omap2/hsmmc.c92
1 files changed, 54 insertions, 38 deletions
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index c8f647b6205e..34272e4863fd 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -14,11 +14,11 @@
14#include <linux/string.h> 14#include <linux/string.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <plat/control.h>
18#include <plat/mmc.h> 17#include <plat/mmc.h>
19#include <plat/omap-pm.h> 18#include <plat/omap-pm.h>
20 19
21#include "hsmmc.h" 20#include "hsmmc.h"
21#include "control.h"
22 22
23#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) 23#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
24 24
@@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
135 * 135 *
136 * FIXME handle VMMC1A as needed ... 136 * FIXME handle VMMC1A as needed ...
137 */ 137 */
138 reg = omap_ctrl_readl(control_pbias_offset); 138 reg = omap4_ctrl_pad_readl(control_pbias_offset);
139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | 139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
140 OMAP4_USBC1_ICUSB_PWRDNZ); 140 OMAP4_MMC1_PWRDNZ_MASK |
141 omap_ctrl_writel(reg, control_pbias_offset); 141 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
142 omap4_ctrl_pad_writel(reg, control_pbias_offset);
142} 143}
143 144
144static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, 145static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
@@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
147 u32 reg; 148 u32 reg;
148 149
149 if (power_on) { 150 if (power_on) {
150 reg = omap_ctrl_readl(control_pbias_offset); 151 reg = omap4_ctrl_pad_readl(control_pbias_offset);
151 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; 152 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
152 if ((1 << vdd) <= MMC_VDD_165_195) 153 if ((1 << vdd) <= MMC_VDD_165_195)
153 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; 154 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
154 else 155 else
155 reg |= OMAP4_MMC1_PBIASLITE_VMODE; 156 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
156 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | 157 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
157 OMAP4_USBC1_ICUSB_PWRDNZ); 158 OMAP4_MMC1_PWRDNZ_MASK |
158 omap_ctrl_writel(reg, control_pbias_offset); 159 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
160 omap4_ctrl_pad_writel(reg, control_pbias_offset);
159 /* 4 microsec delay for comparator to generate an error*/ 161 /* 4 microsec delay for comparator to generate an error*/
160 udelay(4); 162 udelay(4);
161 reg = omap_ctrl_readl(control_pbias_offset); 163 reg = omap4_ctrl_pad_readl(control_pbias_offset);
162 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) { 164 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
163 pr_err("Pbias Voltage is not same as LDO\n"); 165 pr_err("Pbias Voltage is not same as LDO\n");
164 /* Caution : On VMODE_ERROR Power Down MMC IO */ 166 /* Caution : On VMODE_ERROR Power Down MMC IO */
165 reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ); 167 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
166 omap_ctrl_writel(reg, control_pbias_offset); 168 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
169 omap4_ctrl_pad_writel(reg, control_pbias_offset);
167 } 170 }
168 } else { 171 } else {
169 reg = omap_ctrl_readl(control_pbias_offset); 172 reg = omap4_ctrl_pad_readl(control_pbias_offset);
170 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | 173 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
171 OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ | 174 OMAP4_MMC1_PWRDNZ_MASK |
172 OMAP4_USBC1_ICUSB_PWRDNZ); 175 OMAP4_MMC1_PBIASLITE_VMODE_MASK |
173 omap_ctrl_writel(reg, control_pbias_offset); 176 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
177 omap4_ctrl_pad_writel(reg, control_pbias_offset);
174 } 178 }
175} 179}
176 180
@@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
218 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; 222 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
219 } 223 }
220 } else { 224 } else {
221 control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; 225 control_pbias_offset =
222 control_mmc1 = OMAP44XX_CONTROL_MMC1; 226 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
223 reg = omap_ctrl_readl(control_mmc1); 227 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
224 reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | 228 reg = omap4_ctrl_pad_readl(control_mmc1);
225 OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); 229 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
226 reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | 230 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
227 OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); 231 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
228 reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | 232 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
229 OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | 233 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
230 OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); 234 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
231 omap_ctrl_writel(reg, control_mmc1); 235 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
236 omap4_ctrl_pad_writel(reg, control_mmc1);
232 } 237 }
233 238
234 for (c = controllers; c->mmc; c++) { 239 for (c = controllers; c->mmc; c++) {
@@ -258,9 +263,13 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
258 "mmc%islot%i", c->mmc, 1); 263 "mmc%islot%i", c->mmc, 1);
259 mmc->slots[0].name = hc->name; 264 mmc->slots[0].name = hc->name;
260 mmc->nr_slots = 1; 265 mmc->nr_slots = 1;
261 mmc->slots[0].wires = c->wires; 266 mmc->slots[0].caps = c->caps;
262 mmc->slots[0].internal_clock = !c->ext_clock; 267 mmc->slots[0].internal_clock = !c->ext_clock;
263 mmc->dma_mask = 0xffffffff; 268 mmc->dma_mask = 0xffffffff;
269 if (cpu_is_omap44xx())
270 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
271 else
272 mmc->reg_offset = 0;
264 273
265 mmc->get_context_loss_count = hsmmc_get_context_loss; 274 mmc->get_context_loss_count = hsmmc_get_context_loss;
266 275
@@ -298,6 +307,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
298 else 307 else
299 mmc->slots[0].features |= HSMMC_HAS_PBIAS; 308 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
300 309
310 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
311 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
312
301 switch (c->mmc) { 313 switch (c->mmc) {
302 case 1: 314 case 1:
303 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 315 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
@@ -316,16 +328,20 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
316 } 328 }
317 329
318 /* Omap3630 HSMMC1 supports only 4-bit */ 330 /* Omap3630 HSMMC1 supports only 4-bit */
319 if (cpu_is_omap3630() && c->wires > 4) { 331 if (cpu_is_omap3630() &&
320 c->wires = 4; 332 (c->caps & MMC_CAP_8_BIT_DATA)) {
321 mmc->slots[0].wires = c->wires; 333 c->caps &= ~MMC_CAP_8_BIT_DATA;
334 c->caps |= MMC_CAP_4_BIT_DATA;
335 mmc->slots[0].caps = c->caps;
322 } 336 }
323 break; 337 break;
324 case 2: 338 case 2:
325 if (c->ext_clock) 339 if (c->ext_clock)
326 c->transceiver = 1; 340 c->transceiver = 1;
327 if (c->transceiver && c->wires > 4) 341 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
328 c->wires = 4; 342 c->caps &= ~MMC_CAP_8_BIT_DATA;
343 c->caps |= MMC_CAP_4_BIT_DATA;
344 }
329 /* FALLTHROUGH */ 345 /* FALLTHROUGH */
330 case 3: 346 case 3:
331 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 347 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {