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-rw-r--r--arch/arm/mach-omap2/hsmmc.c421
1 files changed, 279 insertions, 142 deletions
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 34272e4863fd..137e1a5f3d85 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -16,7 +16,10 @@
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <plat/mmc.h> 17#include <plat/mmc.h>
18#include <plat/omap-pm.h> 18#include <plat/omap-pm.h>
19#include <plat/mux.h>
20#include <plat/omap_device.h>
19 21
22#include "mux.h"
20#include "hsmmc.h" 23#include "hsmmc.h"
21#include "control.h" 24#include "control.h"
22 25
@@ -28,10 +31,6 @@ static u16 control_mmc1;
28 31
29#define HSMMC_NAME_LEN 9 32#define HSMMC_NAME_LEN 9
30 33
31static struct hsmmc_controller {
32 char name[HSMMC_NAME_LEN + 1];
33} hsmmc[OMAP34XX_NR_MMC];
34
35#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 34#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
36 35
37static int hsmmc_get_context_loss(struct device *dev) 36static int hsmmc_get_context_loss(struct device *dev)
@@ -204,174 +203,312 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
204 return 0; 203 return 0;
205} 204}
206 205
207static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; 206static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
208 207 int controller_nr)
209void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
210{ 208{
211 struct omap2_hsmmc_info *c; 209 if ((mmc_controller->slots[0].switch_pin > 0) && \
212 int nr_hsmmc = ARRAY_SIZE(hsmmc_data); 210 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
213 int i; 211 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
214 u32 reg; 212 OMAP_PIN_INPUT_PULLUP);
215 213 if ((mmc_controller->slots[0].gpio_wp > 0) && \
216 if (!cpu_is_omap44xx()) { 214 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
217 if (cpu_is_omap2430()) { 215 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
218 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 216 OMAP_PIN_INPUT_PULLUP);
219 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; 217 if (cpu_is_omap34xx()) {
220 } else { 218 if (controller_nr == 0) {
221 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; 219 omap_mux_init_signal("sdmmc1_clk",
222 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; 220 OMAP_PIN_INPUT_PULLUP);
223 } 221 omap_mux_init_signal("sdmmc1_cmd",
224 } else { 222 OMAP_PIN_INPUT_PULLUP);
225 control_pbias_offset = 223 omap_mux_init_signal("sdmmc1_dat0",
226 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; 224 OMAP_PIN_INPUT_PULLUP);
227 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; 225 if (mmc_controller->slots[0].caps &
228 reg = omap4_ctrl_pad_readl(control_mmc1); 226 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
229 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | 227 omap_mux_init_signal("sdmmc1_dat1",
230 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); 228 OMAP_PIN_INPUT_PULLUP);
231 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | 229 omap_mux_init_signal("sdmmc1_dat2",
232 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); 230 OMAP_PIN_INPUT_PULLUP);
233 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| 231 omap_mux_init_signal("sdmmc1_dat3",
234 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | 232 OMAP_PIN_INPUT_PULLUP);
235 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); 233 }
236 omap4_ctrl_pad_writel(reg, control_mmc1); 234 if (mmc_controller->slots[0].caps &
237 } 235 MMC_CAP_8_BIT_DATA) {
238 236 omap_mux_init_signal("sdmmc1_dat4",
239 for (c = controllers; c->mmc; c++) { 237 OMAP_PIN_INPUT_PULLUP);
240 struct hsmmc_controller *hc = hsmmc + c->mmc - 1; 238 omap_mux_init_signal("sdmmc1_dat5",
241 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; 239 OMAP_PIN_INPUT_PULLUP);
242 240 omap_mux_init_signal("sdmmc1_dat6",
243 if (!c->mmc || c->mmc > nr_hsmmc) { 241 OMAP_PIN_INPUT_PULLUP);
244 pr_debug("MMC%d: no such controller\n", c->mmc); 242 omap_mux_init_signal("sdmmc1_dat7",
245 continue; 243 OMAP_PIN_INPUT_PULLUP);
246 } 244 }
247 if (mmc) {
248 pr_debug("MMC%d: already configured\n", c->mmc);
249 continue;
250 } 245 }
251 246 if (controller_nr == 1) {
252 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), 247 /* MMC2 */
253 GFP_KERNEL); 248 omap_mux_init_signal("sdmmc2_clk",
254 if (!mmc) { 249 OMAP_PIN_INPUT_PULLUP);
255 pr_err("Cannot allocate memory for mmc device!\n"); 250 omap_mux_init_signal("sdmmc2_cmd",
256 goto done; 251 OMAP_PIN_INPUT_PULLUP);
252 omap_mux_init_signal("sdmmc2_dat0",
253 OMAP_PIN_INPUT_PULLUP);
254
255 /*
256 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
257 * need to be muxed in the board-*.c files
258 */
259 if (mmc_controller->slots[0].caps &
260 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
261 omap_mux_init_signal("sdmmc2_dat1",
262 OMAP_PIN_INPUT_PULLUP);
263 omap_mux_init_signal("sdmmc2_dat2",
264 OMAP_PIN_INPUT_PULLUP);
265 omap_mux_init_signal("sdmmc2_dat3",
266 OMAP_PIN_INPUT_PULLUP);
267 }
268 if (mmc_controller->slots[0].caps &
269 MMC_CAP_8_BIT_DATA) {
270 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
271 OMAP_PIN_INPUT_PULLUP);
272 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
273 OMAP_PIN_INPUT_PULLUP);
274 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
275 OMAP_PIN_INPUT_PULLUP);
276 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
277 OMAP_PIN_INPUT_PULLUP);
278 }
257 } 279 }
258 280
259 if (c->name) 281 /*
260 strncpy(hc->name, c->name, HSMMC_NAME_LEN); 282 * For MMC3 the pins need to be muxed in the board-*.c files
261 else 283 */
262 snprintf(hc->name, ARRAY_SIZE(hc->name), 284 }
263 "mmc%islot%i", c->mmc, 1); 285}
264 mmc->slots[0].name = hc->name;
265 mmc->nr_slots = 1;
266 mmc->slots[0].caps = c->caps;
267 mmc->slots[0].internal_clock = !c->ext_clock;
268 mmc->dma_mask = 0xffffffff;
269 if (cpu_is_omap44xx())
270 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
271 else
272 mmc->reg_offset = 0;
273 286
274 mmc->get_context_loss_count = hsmmc_get_context_loss; 287static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
288 struct omap_mmc_platform_data *mmc)
289{
290 char *hc_name;
275 291
276 mmc->slots[0].switch_pin = c->gpio_cd; 292 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
277 mmc->slots[0].gpio_wp = c->gpio_wp; 293 if (!hc_name) {
294 pr_err("Cannot allocate memory for controller slot name\n");
295 kfree(hc_name);
296 return -ENOMEM;
297 }
278 298
279 mmc->slots[0].remux = c->remux; 299 if (c->name)
280 mmc->slots[0].init_card = c->init_card; 300 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
301 else
302 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
303 c->mmc, 1);
304 mmc->slots[0].name = hc_name;
305 mmc->nr_slots = 1;
306 mmc->slots[0].caps = c->caps;
307 mmc->slots[0].internal_clock = !c->ext_clock;
308 mmc->dma_mask = 0xffffffff;
309 if (cpu_is_omap44xx())
310 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
311 else
312 mmc->reg_offset = 0;
281 313
282 if (c->cover_only) 314 mmc->get_context_loss_count = hsmmc_get_context_loss;
283 mmc->slots[0].cover = 1;
284 315
285 if (c->nonremovable) 316 mmc->slots[0].switch_pin = c->gpio_cd;
286 mmc->slots[0].nonremovable = 1; 317 mmc->slots[0].gpio_wp = c->gpio_wp;
287 318
288 if (c->power_saving) 319 mmc->slots[0].remux = c->remux;
289 mmc->slots[0].power_saving = 1; 320 mmc->slots[0].init_card = c->init_card;
290 321
291 if (c->no_off) 322 if (c->cover_only)
292 mmc->slots[0].no_off = 1; 323 mmc->slots[0].cover = 1;
293 324
294 if (c->vcc_aux_disable_is_sleep) 325 if (c->nonremovable)
295 mmc->slots[0].vcc_aux_disable_is_sleep = 1; 326 mmc->slots[0].nonremovable = 1;
296 327
297 /* NOTE: MMC slots should have a Vcc regulator set up. 328 if (c->power_saving)
298 * This may be from a TWL4030-family chip, another 329 mmc->slots[0].power_saving = 1;
299 * controllable regulator, or a fixed supply.
300 *
301 * temporary HACK: ocr_mask instead of fixed supply
302 */
303 mmc->slots[0].ocr_mask = c->ocr_mask;
304 330
305 if (cpu_is_omap3517() || cpu_is_omap3505()) 331 if (c->no_off)
306 mmc->slots[0].set_power = nop_mmc_set_power; 332 mmc->slots[0].no_off = 1;
307 else
308 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
309 333
310 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) 334 if (c->vcc_aux_disable_is_sleep)
311 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 335 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
312 336
313 switch (c->mmc) { 337 /*
314 case 1: 338 * NOTE: MMC slots should have a Vcc regulator set up.
315 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 339 * This may be from a TWL4030-family chip, another
316 /* on-chip level shifting via PBIAS0/PBIAS1 */ 340 * controllable regulator, or a fixed supply.
317 if (cpu_is_omap44xx()) { 341 *
318 mmc->slots[0].before_set_reg = 342 * temporary HACK: ocr_mask instead of fixed supply
343 */
344 mmc->slots[0].ocr_mask = c->ocr_mask;
345
346 if (cpu_is_omap3517() || cpu_is_omap3505())
347 mmc->slots[0].set_power = nop_mmc_set_power;
348 else
349 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
350
351 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
352 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
353
354 switch (c->mmc) {
355 case 1:
356 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
357 /* on-chip level shifting via PBIAS0/PBIAS1 */
358 if (cpu_is_omap44xx()) {
359 mmc->slots[0].before_set_reg =
319 omap4_hsmmc1_before_set_reg; 360 omap4_hsmmc1_before_set_reg;
320 mmc->slots[0].after_set_reg = 361 mmc->slots[0].after_set_reg =
321 omap4_hsmmc1_after_set_reg; 362 omap4_hsmmc1_after_set_reg;
322 } else { 363 } else {
323 mmc->slots[0].before_set_reg = 364 mmc->slots[0].before_set_reg =
324 omap_hsmmc1_before_set_reg; 365 omap_hsmmc1_before_set_reg;
325 mmc->slots[0].after_set_reg = 366 mmc->slots[0].after_set_reg =
326 omap_hsmmc1_after_set_reg; 367 omap_hsmmc1_after_set_reg;
327 }
328 } 368 }
369 }
329 370
330 /* Omap3630 HSMMC1 supports only 4-bit */ 371 /* OMAP3630 HSMMC1 supports only 4-bit */
331 if (cpu_is_omap3630() && 372 if (cpu_is_omap3630() &&
332 (c->caps & MMC_CAP_8_BIT_DATA)) { 373 (c->caps & MMC_CAP_8_BIT_DATA)) {
333 c->caps &= ~MMC_CAP_8_BIT_DATA; 374 c->caps &= ~MMC_CAP_8_BIT_DATA;
334 c->caps |= MMC_CAP_4_BIT_DATA; 375 c->caps |= MMC_CAP_4_BIT_DATA;
335 mmc->slots[0].caps = c->caps; 376 mmc->slots[0].caps = c->caps;
336 } 377 }
337 break; 378 break;
338 case 2: 379 case 2:
339 if (c->ext_clock) 380 if (c->ext_clock)
340 c->transceiver = 1; 381 c->transceiver = 1;
341 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { 382 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
342 c->caps &= ~MMC_CAP_8_BIT_DATA; 383 c->caps &= ~MMC_CAP_8_BIT_DATA;
343 c->caps |= MMC_CAP_4_BIT_DATA; 384 c->caps |= MMC_CAP_4_BIT_DATA;
344 }
345 /* FALLTHROUGH */
346 case 3:
347 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
348 /* off-chip level shifting, or none */
349 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
350 mmc->slots[0].after_set_reg = NULL;
351 }
352 break;
353 default:
354 pr_err("MMC%d configuration not supported!\n", c->mmc);
355 kfree(mmc);
356 continue;
357 } 385 }
358 hsmmc_data[c->mmc - 1] = mmc; 386 /* FALLTHROUGH */
387 case 3:
388 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
389 /* off-chip level shifting, or none */
390 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
391 mmc->slots[0].after_set_reg = NULL;
392 }
393 break;
394 case 4:
395 case 5:
396 mmc->slots[0].before_set_reg = NULL;
397 mmc->slots[0].after_set_reg = NULL;
398 break;
399 default:
400 pr_err("MMC%d configuration not supported!\n", c->mmc);
401 kfree(hc_name);
402 return -ENODEV;
403 }
404 return 0;
405}
406
407static struct omap_device_pm_latency omap_hsmmc_latency[] = {
408 [0] = {
409 .deactivate_func = omap_device_idle_hwmods,
410 .activate_func = omap_device_enable_hwmods,
411 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
412 },
413 /*
414 * XXX There should also be an entry here to power off/on the
415 * MMC regulators/PBIAS cells, etc.
416 */
417};
418
419#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
420
421void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
422{
423 struct omap_hwmod *oh;
424 struct omap_device *od;
425 struct omap_device_pm_latency *ohl;
426 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
427 struct omap_mmc_platform_data *mmc_data;
428 struct omap_mmc_dev_attr *mmc_dev_attr;
429 char *name;
430 int l;
431 int ohl_cnt = 0;
432
433 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
434 if (!mmc_data) {
435 pr_err("Cannot allocate memory for mmc device!\n");
436 goto done;
359 } 437 }
360 438
361 omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); 439 if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
440 pr_err("%s fails!\n", __func__);
441 goto done;
442 }
443 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
444
445 name = "omap_hsmmc";
446 ohl = omap_hsmmc_latency;
447 ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
448
449 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
450 "mmc%d", ctrl_nr);
451 WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
452 "String buffer overflow in MMC%d device setup\n", ctrl_nr);
453 oh = omap_hwmod_lookup(oh_name);
454 if (!oh) {
455 pr_err("Could not look up %s\n", oh_name);
456 kfree(mmc_data->slots[0].name);
457 goto done;
458 }
362 459
363 /* pass the device nodes back to board setup code */ 460 if (oh->dev_attr != NULL) {
364 for (c = controllers; c->mmc; c++) { 461 mmc_dev_attr = oh->dev_attr;
365 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; 462 mmc_data->controller_flags = mmc_dev_attr->flags;
463 }
366 464
367 if (!c->mmc || c->mmc > nr_hsmmc) 465 od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
368 continue; 466 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
369 c->dev = mmc->dev; 467 if (IS_ERR(od)) {
468 WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name);
469 kfree(mmc_data->slots[0].name);
470 goto done;
370 } 471 }
472 /*
473 * return device handle to board setup code
474 * required to populate for regulator framework structure
475 */
476 hsmmcinfo->dev = &od->pdev.dev;
371 477
372done: 478done:
373 for (i = 0; i < nr_hsmmc; i++) 479 kfree(mmc_data);
374 kfree(hsmmc_data[i]); 480}
481
482void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
483{
484 u32 reg;
485
486 if (!cpu_is_omap44xx()) {
487 if (cpu_is_omap2430()) {
488 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
489 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
490 } else {
491 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
492 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
493 }
494 } else {
495 control_pbias_offset =
496 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
497 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
498 reg = omap4_ctrl_pad_readl(control_mmc1);
499 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
500 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
501 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
502 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
503 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
504 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
505 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
506 omap4_ctrl_pad_writel(reg, control_mmc1);
507 }
508
509 for (; controllers->mmc; controllers++)
510 omap_init_hsmmc(controllers, controllers->mmc);
511
375} 512}
376 513
377#endif 514#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 18:51:32 -0500