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-rw-r--r--arch/arm/mach-omap2/gpmc.h43
1 files changed, 29 insertions, 14 deletions
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index fe0a844d5007..707f6d58edd5 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -58,7 +58,7 @@
58#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 58#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
59#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) 59#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
60#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 60#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
61#define GPMC_CONFIG1_MUXADDDATA (1 << 9) 61#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
62#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 62#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
63#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) 63#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
64#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 64#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
@@ -73,6 +73,13 @@
73#define GPMC_IRQ_FIFOEVENTENABLE 0x01 73#define GPMC_IRQ_FIFOEVENTENABLE 0x01
74#define GPMC_IRQ_COUNT_EVENT 0x02 74#define GPMC_IRQ_COUNT_EVENT 0x02
75 75
76#define GPMC_BURST_4 4 /* 4 word burst */
77#define GPMC_BURST_8 8 /* 8 word burst */
78#define GPMC_BURST_16 16 /* 16 word burst */
79#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
80#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
81#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
82#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
76 83
77/* bool type time settings */ 84/* bool type time settings */
78struct gpmc_bool_timings { 85struct gpmc_bool_timings {
@@ -178,10 +185,6 @@ struct gpmc_device_timings {
178 u8 cyc_wpl; /* write deassertion time in cycles */ 185 u8 cyc_wpl; /* write deassertion time in cycles */
179 u32 cyc_iaa; /* initial access time in cycles */ 186 u32 cyc_iaa; /* initial access time in cycles */
180 187
181 bool mux; /* address & data muxed */
182 bool sync_write;/* synchronous write */
183 bool sync_read; /* synchronous read */
184
185 /* extra delays */ 188 /* extra delays */
186 bool ce_xdelay; 189 bool ce_xdelay;
187 bool avd_xdelay; 190 bool avd_xdelay;
@@ -189,28 +192,40 @@ struct gpmc_device_timings {
189 bool we_xdelay; 192 bool we_xdelay;
190}; 193};
191 194
195struct gpmc_settings {
196 bool burst_wrap; /* enables wrap bursting */
197 bool burst_read; /* enables read page/burst mode */
198 bool burst_write; /* enables write page/burst mode */
199 bool device_nand; /* device is NAND */
200 bool sync_read; /* enables synchronous reads */
201 bool sync_write; /* enables synchronous writes */
202 bool wait_on_read; /* monitor wait on reads */
203 bool wait_on_write; /* monitor wait on writes */
204 u32 burst_len; /* page/burst length */
205 u32 device_width; /* device bus width (8 or 16 bit) */
206 u32 mux_add_data; /* multiplex address & data */
207 u32 wait_pin; /* wait-pin to be used */
208};
209
192extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t, 210extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
193 struct gpmc_device_timings *dev_t); 211 struct gpmc_settings *gpmc_s,
212 struct gpmc_device_timings *dev_t);
194 213
195extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); 214extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
196extern int gpmc_get_client_irq(unsigned irq_config); 215extern int gpmc_get_client_irq(unsigned irq_config);
197 216
198extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
199extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
200extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); 217extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
201extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
202extern unsigned long gpmc_get_fclk_period(void);
203 218
204extern void gpmc_cs_write_reg(int cs, int idx, u32 val); 219extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
205extern u32 gpmc_cs_read_reg(int cs, int idx);
206extern int gpmc_calc_divider(unsigned int sync_clk); 220extern int gpmc_calc_divider(unsigned int sync_clk);
207extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); 221extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
222extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
208extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); 223extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
209extern void gpmc_cs_free(int cs); 224extern void gpmc_cs_free(int cs);
210extern int gpmc_cs_set_reserved(int cs, int reserved);
211extern int gpmc_cs_reserved(int cs);
212extern void omap3_gpmc_save_context(void); 225extern void omap3_gpmc_save_context(void);
213extern void omap3_gpmc_restore_context(void); 226extern void omap3_gpmc_restore_context(void);
214extern int gpmc_cs_configure(int cs, int cmd, int wval); 227extern int gpmc_configure(int cmd, int wval);
228extern void gpmc_read_settings_dt(struct device_node *np,
229 struct gpmc_settings *p);
215 230
216#endif 231#endif