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1/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14#include <linux/platform_data/mtd-nand-omap2.h>
15
16/* Maximum Number of Chip Selects */
17#define GPMC_CS_NUM 8
18
19#define GPMC_CS_CONFIG1 0x00
20#define GPMC_CS_CONFIG2 0x04
21#define GPMC_CS_CONFIG3 0x08
22#define GPMC_CS_CONFIG4 0x0c
23#define GPMC_CS_CONFIG5 0x10
24#define GPMC_CS_CONFIG6 0x14
25#define GPMC_CS_CONFIG7 0x18
26#define GPMC_CS_NAND_COMMAND 0x1c
27#define GPMC_CS_NAND_ADDRESS 0x20
28#define GPMC_CS_NAND_DATA 0x24
29
30/* Control Commands */
31#define GPMC_CONFIG_RDY_BSY 0x00000001
32#define GPMC_CONFIG_DEV_SIZE 0x00000002
33#define GPMC_CONFIG_DEV_TYPE 0x00000003
34#define GPMC_SET_IRQ_STATUS 0x00000004
35#define GPMC_CONFIG_WP 0x00000005
36
37#define GPMC_ENABLE_IRQ 0x0000000d
38
39/* ECC commands */
40#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
41#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
42#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
43
44#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
45#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
46#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
47#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
48#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
49#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
50#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
51#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
52#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
53#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
54#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
55#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
56#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
57#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
58#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
59#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
60#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
61#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
62#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
63#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
64#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
65#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
66#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
67#define GPMC_CONFIG7_CSVALID (1 << 6)
68
69#define GPMC_DEVICETYPE_NOR 0
70#define GPMC_DEVICETYPE_NAND 2
71#define GPMC_CONFIG_WRITEPROTECT 0x00000010
72#define WR_RD_PIN_MONITORING 0x00600000
73#define GPMC_IRQ_FIFOEVENTENABLE 0x01
74#define GPMC_IRQ_COUNT_EVENT 0x02
75
76
77/*
78 * Note that all values in this struct are in nanoseconds except sync_clk
79 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
80 */
81struct gpmc_timings {
82 /* Minimum clock period for synchronous mode (in picoseconds) */
83 u32 sync_clk;
84
85 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
86 u16 cs_on; /* Assertion time */
87 u16 cs_rd_off; /* Read deassertion time */
88 u16 cs_wr_off; /* Write deassertion time */
89
90 /* ADV signal timings corresponding to GPMC_CONFIG3 */
91 u16 adv_on; /* Assertion time */
92 u16 adv_rd_off; /* Read deassertion time */
93 u16 adv_wr_off; /* Write deassertion time */
94
95 /* WE signals timings corresponding to GPMC_CONFIG4 */
96 u16 we_on; /* WE assertion time */
97 u16 we_off; /* WE deassertion time */
98
99 /* OE signals timings corresponding to GPMC_CONFIG4 */
100 u16 oe_on; /* OE assertion time */
101 u16 oe_off; /* OE deassertion time */
102
103 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
104 u16 page_burst_access; /* Multiple access word delay */
105 u16 access; /* Start-cycle to first data valid delay */
106 u16 rd_cycle; /* Total read cycle time */
107 u16 wr_cycle; /* Total write cycle time */
108
109 /* The following are only on OMAP3430 */
110 u16 wr_access; /* WRACCESSTIME */
111 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
112};
113
114extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
115extern int gpmc_get_client_irq(unsigned irq_config);
116
117extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
118extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
119extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
120extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
121extern unsigned long gpmc_get_fclk_period(void);
122
123extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
124extern u32 gpmc_cs_read_reg(int cs, int idx);
125extern int gpmc_calc_divider(unsigned int sync_clk);
126extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
127extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
128extern void gpmc_cs_free(int cs);
129extern int gpmc_cs_set_reserved(int cs, int reserved);
130extern int gpmc_cs_reserved(int cs);
131extern void omap3_gpmc_save_context(void);
132extern void omap3_gpmc_restore_context(void);
133extern int gpmc_cs_configure(int cs, int cmd, int wval);
134
135#endif
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