diff options
Diffstat (limited to 'arch/arm/mach-omap2/gpmc-onenand.c')
-rw-r--r-- | arch/arm/mach-omap2/gpmc-onenand.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 7bb69220adfa..3a7d25fb00ef 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c | |||
@@ -173,8 +173,17 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
173 | } | 173 | } |
174 | 174 | ||
175 | switch (freq) { | 175 | switch (freq) { |
176 | case 104: | ||
177 | min_gpmc_clk_period = 9600; /* 104 MHz */ | ||
178 | t_ces = 3; | ||
179 | t_avds = 4; | ||
180 | t_avdh = 2; | ||
181 | t_ach = 3; | ||
182 | t_aavdh = 6; | ||
183 | t_rdyo = 9; | ||
184 | break; | ||
176 | case 83: | 185 | case 83: |
177 | min_gpmc_clk_period = 12; /* 83 MHz */ | 186 | min_gpmc_clk_period = 12000; /* 83 MHz */ |
178 | t_ces = 5; | 187 | t_ces = 5; |
179 | t_avds = 4; | 188 | t_avds = 4; |
180 | t_avdh = 2; | 189 | t_avdh = 2; |
@@ -183,7 +192,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
183 | t_rdyo = 9; | 192 | t_rdyo = 9; |
184 | break; | 193 | break; |
185 | case 66: | 194 | case 66: |
186 | min_gpmc_clk_period = 15; /* 66 MHz */ | 195 | min_gpmc_clk_period = 15000; /* 66 MHz */ |
187 | t_ces = 6; | 196 | t_ces = 6; |
188 | t_avds = 5; | 197 | t_avds = 5; |
189 | t_avdh = 2; | 198 | t_avdh = 2; |
@@ -192,7 +201,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
192 | t_rdyo = 11; | 201 | t_rdyo = 11; |
193 | break; | 202 | break; |
194 | default: | 203 | default: |
195 | min_gpmc_clk_period = 18; /* 54 MHz */ | 204 | min_gpmc_clk_period = 18500; /* 54 MHz */ |
196 | t_ces = 7; | 205 | t_ces = 7; |
197 | t_avds = 7; | 206 | t_avds = 7; |
198 | t_avdh = 7; | 207 | t_avdh = 7; |
@@ -271,8 +280,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
271 | t.wr_cycle = t.rd_cycle; | 280 | t.wr_cycle = t.rd_cycle; |
272 | if (cpu_is_omap34xx()) { | 281 | if (cpu_is_omap34xx()) { |
273 | t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset + | 282 | t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset + |
274 | gpmc_ns_to_ticks(min_gpmc_clk_period + | 283 | gpmc_ps_to_ticks(min_gpmc_clk_period + |
275 | t_rdyo)); | 284 | t_rdyo * 1000)); |
276 | t.wr_access = t.access; | 285 | t.wr_access = t.access; |
277 | } | 286 | } |
278 | } else { | 287 | } else { |