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Diffstat (limited to 'arch/arm/mach-omap2/gpmc-nand.c')
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c44
1 files changed, 3 insertions, 41 deletions
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index d9c27195caf0..662c7fd633cc 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = {
43 .resource = gpmc_nand_resource, 43 .resource = gpmc_nand_resource,
44}; 44};
45 45
46static int omap2_nand_gpmc_retime(
47 struct omap_nand_platform_data *gpmc_nand_data,
48 struct gpmc_timings *gpmc_t)
49{
50 struct gpmc_timings t;
51 int err;
52
53 memset(&t, 0, sizeof(t));
54 t.sync_clk = gpmc_t->sync_clk;
55 t.cs_on = gpmc_t->cs_on;
56 t.adv_on = gpmc_t->adv_on;
57
58 /* Read */
59 t.adv_rd_off = gpmc_t->adv_rd_off;
60 t.oe_on = t.adv_on;
61 t.access = gpmc_t->access;
62 t.oe_off = gpmc_t->oe_off;
63 t.cs_rd_off = gpmc_t->cs_rd_off;
64 t.rd_cycle = gpmc_t->rd_cycle;
65
66 /* Write */
67 t.adv_wr_off = gpmc_t->adv_wr_off;
68 t.we_on = t.oe_on;
69 if (cpu_is_omap34xx()) {
70 t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
71 t.wr_access = gpmc_t->wr_access;
72 }
73 t.we_off = gpmc_t->we_off;
74 t.cs_wr_off = gpmc_t->cs_wr_off;
75 t.wr_cycle = gpmc_t->wr_cycle;
76
77 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
78 if (err)
79 return err;
80
81 return 0;
82}
83
84static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) 46static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
85{ 47{
86 /* support only OMAP3 class */ 48 /* support only OMAP3 class */
@@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
131 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); 93 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
132 94
133 if (gpmc_t) { 95 if (gpmc_t) {
134 err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); 96 err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
135 if (err < 0) { 97 if (err < 0) {
136 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 98 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
137 return err; 99 return err;
@@ -140,8 +102,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
140 if (gpmc_nand_data->of_node) { 102 if (gpmc_nand_data->of_node) {
141 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); 103 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
142 } else { 104 } else {
143 s.device_nand = true;
144
145 /* Enable RD PIN Monitoring Reg */ 105 /* Enable RD PIN Monitoring Reg */
146 if (gpmc_nand_data->dev_ready) { 106 if (gpmc_nand_data->dev_ready) {
147 s.wait_on_read = true; 107 s.wait_on_read = true;
@@ -149,6 +109,8 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
149 } 109 }
150 } 110 }
151 111
112 s.device_nand = true;
113
152 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) 114 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
153 s.device_width = GPMC_DEVWIDTH_16BIT; 115 s.device_width = GPMC_DEVWIDTH_16BIT;
154 else 116 else