diff options
Diffstat (limited to 'arch/arm/mach-omap2/dpll44xx.c')
-rw-r--r-- | arch/arm/mach-omap2/dpll44xx.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index d28b0f726715..52f9438b92f2 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c | |||
@@ -42,7 +42,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) | |||
42 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | 42 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : |
43 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | 43 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; |
44 | 44 | ||
45 | v = __raw_readl(clk->clksel_reg); | 45 | v = omap2_clk_readl(clk, clk->clksel_reg); |
46 | v &= mask; | 46 | v &= mask; |
47 | v >>= __ffs(mask); | 47 | v >>= __ffs(mask); |
48 | 48 | ||
@@ -61,10 +61,10 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) | |||
61 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | 61 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : |
62 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | 62 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; |
63 | 63 | ||
64 | v = __raw_readl(clk->clksel_reg); | 64 | v = omap2_clk_readl(clk, clk->clksel_reg); |
65 | /* Clear the bit to allow gatectrl */ | 65 | /* Clear the bit to allow gatectrl */ |
66 | v &= ~mask; | 66 | v &= ~mask; |
67 | __raw_writel(v, clk->clksel_reg); | 67 | omap2_clk_writel(v, clk, clk->clksel_reg); |
68 | } | 68 | } |
69 | 69 | ||
70 | void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) | 70 | void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) |
@@ -79,10 +79,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) | |||
79 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | 79 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : |
80 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | 80 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; |
81 | 81 | ||
82 | v = __raw_readl(clk->clksel_reg); | 82 | v = omap2_clk_readl(clk, clk->clksel_reg); |
83 | /* Set the bit to deny gatectrl */ | 83 | /* Set the bit to deny gatectrl */ |
84 | v |= mask; | 84 | v |= mask; |
85 | __raw_writel(v, clk->clksel_reg); | 85 | omap2_clk_writel(v, clk, clk->clksel_reg); |
86 | } | 86 | } |
87 | 87 | ||
88 | const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { | 88 | const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { |
@@ -140,7 +140,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, | |||
140 | rate = omap2_get_dpll_rate(clk); | 140 | rate = omap2_get_dpll_rate(clk); |
141 | 141 | ||
142 | /* regm4xen adds a multiplier of 4 to DPLL calculations */ | 142 | /* regm4xen adds a multiplier of 4 to DPLL calculations */ |
143 | v = __raw_readl(dd->control_reg); | 143 | v = omap2_clk_readl(clk, dd->control_reg); |
144 | if (v & OMAP4430_DPLL_REGM4XEN_MASK) | 144 | if (v & OMAP4430_DPLL_REGM4XEN_MASK) |
145 | rate *= OMAP4430_REGM4XEN_MULT; | 145 | rate *= OMAP4430_REGM4XEN_MULT; |
146 | 146 | ||