1 files changed, 169 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 90af2ac469aa..9d7216ff6c9f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -14,16 +14,19 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
+#include <mach/control.h>
 #include <mach/tc.h>
 #include <mach/board.h>
 #include <mach/mux.h>
 #include <mach/gpio.h>
 #include <mach/eac.h>
+#include <mach/mmc.h>
 
 #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 #define OMAP2_MBOX_BASE         IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
@@ -295,6 +298,171 @@ static void omap_init_sha1_md5(void)
 static inline void omap_init_sha1_md5(void) { }
 #endif
 
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_ARCH_OMAP3
+
+#define MMCHS_SYSCONFIG                 0x0010
+#define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
+#define MMCHS_SYSSTATUS                 0x0014
+#define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
+
+static struct platform_device dummy_pdev = {
+        .dev = {
+                .bus = &platform_bus_type,
+        },
+};
+
+/**
+ * omap_hsmmc_reset() - Full reset of each HS-MMC controller
+ *
+ * Ensure that each MMC controller is fully reset.  Controllers
+ * left in an unknown state (by bootloader) may prevent retention
+ * or OFF-mode.  This is especially important in cases where the
+ * MMC driver is not enabled, _or_ built as a module.
+ *
+ * In order for reset to work, interface, functional and debounce
+ * clocks must be enabled.  The debounce clock comes from func_32k_clk
+ * and is not under SW control, so we only enable i- and f-clocks.
+ **/
+static void __init omap_hsmmc_reset(void)
+{
+        u32 i, nr_controllers = cpu_is_omap34xx() ? OMAP34XX_NR_MMC :
+                OMAP24XX_NR_MMC;
+
+        for (i = 0; i < nr_controllers; i++) {
+                u32 v, base = 0;
+                struct clk *iclk, *fclk;
+                struct device *dev = &dummy_pdev.dev;
+
+                switch (i) {
+                case 0:
+                        base = OMAP2_MMC1_BASE;
+                        break;
+                case 1:
+                        base = OMAP2_MMC2_BASE;
+                        break;
+                case 2:
+                        base = OMAP3_MMC3_BASE;
+                        break;
+                }
+
+                dummy_pdev.id = i;
+                iclk = clk_get(dev, "mmchs_ick");
+                if (iclk && clk_enable(iclk))
+                        iclk = NULL;
+
+                fclk = clk_get(dev, "mmchs_fck");
+                if (fclk && clk_enable(fclk))
+                        fclk = NULL;
+
+                if (!iclk || !fclk) {
+                        printk(KERN_WARNING
+                               "%s: Unable to enable clocks for MMC%d, "
+                               "cannot reset.\n",  __func__, i);
+                        break;
+                }
+
+                omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
+                v = omap_readl(base + MMCHS_SYSSTATUS);
+                while (!(omap_readl(base + MMCHS_SYSSTATUS) &
+                         MMCHS_SYSSTATUS_RESETDONE))
+                        cpu_relax();
+
+                if (fclk) {
+                        clk_disable(fclk);
+                        clk_put(fclk);
+                }
+                if (iclk) {
+                        clk_disable(iclk);
+                        clk_put(iclk);
+                }
+        }
+}
+#else
+static inline void omap_hsmmc_reset(void) {}
+#endif
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
+        defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+
+static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
+                        int controller_nr)
+{
+        if (cpu_is_omap2420() && controller_nr == 0) {
+                omap_cfg_reg(H18_24XX_MMC_CMD);
+                omap_cfg_reg(H15_24XX_MMC_CLKI);
+                omap_cfg_reg(G19_24XX_MMC_CLKO);
+                omap_cfg_reg(F20_24XX_MMC_DAT0);
+                omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
+                omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
+                if (mmc_controller->slots[0].wires == 4) {
+                        omap_cfg_reg(H14_24XX_MMC_DAT1);
+                        omap_cfg_reg(E19_24XX_MMC_DAT2);
+                        omap_cfg_reg(D19_24XX_MMC_DAT3);
+                        omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
+                        omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
+                        omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
+                }
+
+                /*
+                 * Use internal loop-back in MMC/SDIO Module Input Clock
+                 * selection
+                 */
+                if (mmc_controller->slots[0].internal_clock) {
+                        u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+                        v |= (1 << 24);
+                        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
+                }
+        }
+}
+
+void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+                        int nr_controllers)
+{
+        int i;
+
+        for (i = 0; i < nr_controllers; i++) {
+                unsigned long base, size;
+                unsigned int irq = 0;
+
+                if (!mmc_data[i])
+                        continue;
+
+                omap2_mmc_mux(mmc_data[i], i);
+
+                switch (i) {
+                case 0:
+                        base = OMAP2_MMC1_BASE;
+                        irq = INT_24XX_MMC_IRQ;
+                        break;
+                case 1:
+                        base = OMAP2_MMC2_BASE;
+                        irq = INT_24XX_MMC2_IRQ;
+                        break;
+                case 2:
+                        if (!cpu_is_omap34xx())
+                                return;
+                        base = OMAP3_MMC3_BASE;
+                        irq = INT_34XX_MMC3_IRQ;
+                        break;
+                default:
+                        continue;
+                }
+
+                if (cpu_is_omap2420())
+                        size = OMAP2420_MMC_SIZE;
+                else
+                        size = HSMMC_SIZE;
+
+                omap_mmc_add(i, base, size, irq, mmc_data[i]);
+        };
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
 #define OMAP_HDQ_BASE   0x480B2000
@@ -334,6 +502,7 @@ static int __init omap2_init_devices(void)
         /* please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
+        omap_hsmmc_reset();
         omap_init_mbox();
         omap_init_mcspi();
         omap_hdq_init();