1 files changed, 26 insertions, 82 deletions

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 5a0c148e23bc..381f4eb92352 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -638,6 +638,7 @@ static struct platform_device dummy_pdev = {
 static void __init omap_hsmmc_reset(void)
 {
         u32 i, nr_controllers;
+        struct clk *iclk, *fclk;
 
         if (cpu_is_omap242x())
                 return;
@@ -647,7 +648,6 @@ static void __init omap_hsmmc_reset(void)
 
         for (i = 0; i < nr_controllers; i++) {
                 u32 v, base = 0;
-                struct clk *iclk, *fclk;
                 struct device *dev = &dummy_pdev.dev;
 
                 switch (i) {
@@ -678,19 +678,16 @@ static void __init omap_hsmmc_reset(void)
                 dummy_pdev.id = i;
                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
                 iclk = clk_get(dev, "ick");
-                if (iclk && clk_enable(iclk))
-                        iclk = NULL;
+                if (IS_ERR(iclk))
+                        goto err1;
+                if (clk_enable(iclk))
+                        goto err2;
 
                 fclk = clk_get(dev, "fck");
-                if (fclk && clk_enable(fclk))
-                        fclk = NULL;
-
-                if (!iclk || !fclk) {
-                        printk(KERN_WARNING
-                               "%s: Unable to enable clocks for MMC%d, "
-                               "cannot reset.\n",  __func__, i);
-                        break;
-                }
+                if (IS_ERR(fclk))
+                        goto err3;
+                if (clk_enable(fclk))
+                        goto err4;
 
                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
                 v = omap_readl(base + MMCHS_SYSSTATUS);
@@ -698,15 +695,22 @@ static void __init omap_hsmmc_reset(void)
                          MMCHS_SYSSTATUS_RESETDONE))
                         cpu_relax();
 
-                if (fclk) {
-                        clk_disable(fclk);
-                        clk_put(fclk);
-                }
-                if (iclk) {
-                        clk_disable(iclk);
-                        clk_put(iclk);
-                }
+                clk_disable(fclk);
+                clk_put(fclk);
+                clk_disable(iclk);
+                clk_put(iclk);
         }
+        return;
+
+err4:
+        clk_put(fclk);
+err3:
+        clk_disable(iclk);
+err2:
+        clk_put(iclk);
+err1:
+        printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
+                            "cannot reset.\n",  __func__, i);
 }
 #else
 static inline void omap_hsmmc_reset(void) {}
@@ -951,72 +955,12 @@ static inline void omap_init_vout(void) {}
 
 /*-------------------------------------------------------------------------*/
 
-/*
- * Inorder to avoid any assumptions from bootloader regarding WDT
- * settings, WDT module is reset during init. This enables the watchdog
- * timer. Hence it is required to disable the watchdog after the WDT reset
- * during init. Otherwise the system would reboot as per the default
- * watchdog timer registers settings.
- */
-#define OMAP_WDT_WPS    (0x34)
-#define OMAP_WDT_SPR    (0x48)
-
-static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
-{
-        void __iomem *base;
-        int ret;
-
-        if (!oh) {
-                pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
-                return -EINVAL;
-        }
-
-        base = omap_hwmod_get_mpu_rt_va(oh);
-        if (!base) {
-                pr_err("%s: Could not get the base address for %s\n",
-                                oh->name, __func__);
-                return -EINVAL;
-        }
-
-        /* Enable the clocks before accessing the WDT registers */
-        ret = omap_hwmod_enable(oh);
-        if (ret) {
-                pr_err("%s: Could not enable clocks for %s\n",
-                                oh->name, __func__);
-                return ret;
-        }
-
-        /* sequence required to disable watchdog */
-        __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
-        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
-                cpu_relax();
-
-        __raw_writel(0x5555, base + OMAP_WDT_SPR);
-        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
-                cpu_relax();
-
-        ret = omap_hwmod_idle(oh);
-        if (ret)
-                pr_err("%s: Could not disable clocks for %s\n",
-                                oh->name, __func__);
-
-        return ret;
-}
-
-static void __init omap_disable_wdt(void)
-{
-        if (cpu_class_is_omap2())
-                omap_hwmod_for_each_by_class("wd_timer",
-                                                omap2_disable_wdt, NULL);
-        return;
-}
-
 static int __init omap2_init_devices(void)
 {
-        /* please keep these calls, and their implementations above,
+        /*
+         * please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
-        omap_disable_wdt();
         omap_hsmmc_reset();
         omap_init_audio();
         omap_init_camera();