1 files changed, 27 insertions, 1 deletions

diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6923deb98a28..a3a3ca07e383 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -55,7 +55,7 @@
 /* Bits specific to each register */
 
 /* CM_FCLKEN_IVA2 */
-#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2                 (1 << 0)
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK            (1 << 0)
 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT           0
 
 /* CM_CLKEN_PLL_IVA2 */
@@ -168,6 +168,12 @@
 #define OMAP3430_EN_SDRC                                (1 << 1)
 #define OMAP3430_EN_SDRC_SHIFT                          1
 
+/* AM35XX specific CM_ICLKEN1_CORE bits */
+#define AM35XX_EN_IPSS_MASK                             (1 << 4)
+#define AM35XX_EN_IPSS_SHIFT                            4
+#define AM35XX_EN_UART4_MASK                    (1 << 23)
+#define AM35XX_EN_UART4_SHIFT                           23
+
 /* CM_ICLKEN2_CORE */
 #define OMAP3430_EN_PKA                                 (1 << 4)
 #define OMAP3430_EN_PKA_SHIFT                           4
@@ -220,6 +226,10 @@
 #define OMAP3430_ST_SSI_STDBY_SHIFT                     0
 #define OMAP3430_ST_SSI_STDBY_MASK                      (1 << 0)
 
+/* AM35xx specific CM_IDLEST1_CORE bits */
+#define AM35XX_ST_IPSS_SHIFT                            5
+#define AM35XX_ST_IPSS_MASK                             (1 << 5)
+
 /* CM_IDLEST2_CORE */
 #define OMAP3430_ST_PKA_SHIFT                           4
 #define OMAP3430_ST_PKA_MASK                            (1 << 4)
@@ -336,6 +346,8 @@
 #define OMAP3430_CLKSEL_L4_MASK                         (0x3 << 2)
 #define OMAP3430_CLKSEL_L3_SHIFT                        0
 #define OMAP3430_CLKSEL_L3_MASK                         (0x3 << 0)
+#define OMAP3630_CLKSEL_96M_SHIFT                       12
+#define OMAP3630_CLKSEL_96M_MASK                        (0x3 << 12)
 
 /* CM_CLKSTCTRL_CORE */
 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT                 4
@@ -379,6 +391,10 @@
 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT          1
 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK           (1 << 1)
 
+/* CM_IDLEST_SGX */
+#define OMAP3430ES2_ST_SGX_SHIFT                        1
+#define OMAP3430ES2_ST_SGX_MASK                         (1 << 1)
+
 /* CM_ICLKEN_SGX */
 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT          0
 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK           (1 << 0)
@@ -517,12 +533,18 @@
 /* CM_CLKSEL2_PLL */
 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT                 8
 #define OMAP3430_PERIPH_DPLL_MULT_MASK                  (0x7ff << 8)
+#define OMAP3630_PERIPH_DPLL_MULT_MASK                  (0xfff << 8)
 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT                  0
 #define OMAP3430_PERIPH_DPLL_DIV_MASK                   (0x7f << 0)
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT              21
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK               (0x7 << 21)
+#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT               24
+#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK                (0xff << 24)
 
 /* CM_CLKSEL3_PLL */
 #define OMAP3430_DIV_96M_SHIFT                          0
 #define OMAP3430_DIV_96M_MASK                           (0x1f << 0)
+#define OMAP3630_DIV_96M_MASK                           (0x3f << 0)
 
 /* CM_CLKSEL4_PLL */
 #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT             8
@@ -569,8 +591,10 @@
 /* CM_CLKSEL_DSS */
 #define OMAP3430_CLKSEL_TV_SHIFT                        8
 #define OMAP3430_CLKSEL_TV_MASK                         (0x1f << 8)
+#define OMAP3630_CLKSEL_TV_MASK                         (0x3f << 8)
 #define OMAP3430_CLKSEL_DSS1_SHIFT                      0
 #define OMAP3430_CLKSEL_DSS1_MASK                       (0x1f << 0)
+#define OMAP3630_CLKSEL_DSS1_MASK                       (0x3f << 0)
 
 /* CM_SLEEPDEP_DSS specific bits */
 
@@ -598,6 +622,7 @@
 /* CM_CLKSEL_CAM */
 #define OMAP3430_CLKSEL_CAM_SHIFT                       0
 #define OMAP3430_CLKSEL_CAM_MASK                        (0x1f << 0)
+#define OMAP3630_CLKSEL_CAM_MASK                        (0x3f << 0)
 
 /* CM_SLEEPDEP_CAM specific bits */
 
@@ -693,6 +718,7 @@
 /* CM_CLKSEL1_EMU */
 #define OMAP3430_DIV_DPLL4_SHIFT                        24
 #define OMAP3430_DIV_DPLL4_MASK                         (0x1f << 24)
+#define OMAP3630_DIV_DPLL4_MASK                         (0x3f << 24)
 #define OMAP3430_DIV_DPLL3_SHIFT                        16
 #define OMAP3430_DIV_DPLL3_MASK                         (0x1f << 16)
 #define OMAP3430_CLKSEL_TRACECLK_SHIFT                  11