diff options
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 3c38395f6442..ee4c0ca1a708 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -72,7 +72,8 @@ | |||
| 72 | #define OMAP3430_ST_IVA2 (1 << 0) | 72 | #define OMAP3430_ST_IVA2 (1 << 0) |
| 73 | 73 | ||
| 74 | /* CM_IDLEST_PLL_IVA2 */ | 74 | /* CM_IDLEST_PLL_IVA2 */ |
| 75 | #define OMAP3430_ST_IVA2_CLK (1 << 0) | 75 | #define OMAP3430_ST_IVA2_CLK_SHIFT 0 |
| 76 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) | ||
| 76 | 77 | ||
| 77 | /* CM_AUTOIDLE_PLL_IVA2 */ | 78 | /* CM_AUTOIDLE_PLL_IVA2 */ |
| 78 | #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 | 79 | #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 |
| @@ -115,10 +116,7 @@ | |||
| 115 | #define OMAP3430_ST_MPU (1 << 0) | 116 | #define OMAP3430_ST_MPU (1 << 0) |
| 116 | 117 | ||
| 117 | /* CM_IDLEST_PLL_MPU */ | 118 | /* CM_IDLEST_PLL_MPU */ |
| 118 | #define OMAP3430_ST_MPU_CLK (1 << 0) | 119 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 |
| 119 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) | ||
| 120 | |||
| 121 | /* CM_IDLEST_PLL_MPU */ | ||
| 122 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) | 120 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) |
| 123 | 121 | ||
| 124 | /* CM_AUTOIDLE_PLL_MPU */ | 122 | /* CM_AUTOIDLE_PLL_MPU */ |
| @@ -408,8 +406,10 @@ | |||
| 408 | #define OMAP3430_ST_12M_CLK (1 << 4) | 406 | #define OMAP3430_ST_12M_CLK (1 << 4) |
| 409 | #define OMAP3430_ST_48M_CLK (1 << 3) | 407 | #define OMAP3430_ST_48M_CLK (1 << 3) |
| 410 | #define OMAP3430_ST_96M_CLK (1 << 2) | 408 | #define OMAP3430_ST_96M_CLK (1 << 2) |
| 411 | #define OMAP3430_ST_PERIPH_CLK (1 << 1) | 409 | #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 |
| 412 | #define OMAP3430_ST_CORE_CLK (1 << 0) | 410 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) |
| 411 | #define OMAP3430_ST_CORE_CLK_SHIFT 0 | ||
| 412 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | ||
| 413 | 413 | ||
| 414 | /* CM_IDLEST2_CKGEN */ | 414 | /* CM_IDLEST2_CKGEN */ |
| 415 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 | 415 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 |
| @@ -423,6 +423,10 @@ | |||
| 423 | #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 | 423 | #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 |
| 424 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) | 424 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) |
| 425 | 425 | ||
| 426 | /* CM_AUTOIDLE2_PLL */ | ||
| 427 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 | ||
| 428 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) | ||
| 429 | |||
| 426 | /* CM_CLKSEL1_PLL */ | 430 | /* CM_CLKSEL1_PLL */ |
| 427 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ | 431 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ |
| 428 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 | 432 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 |