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-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 29cd13b838ca..e6a724cc63f1 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -542,6 +542,7 @@
542/* CM_CLKSEL3_PLL */ 542/* CM_CLKSEL3_PLL */
543#define OMAP3430_DIV_96M_SHIFT 0 543#define OMAP3430_DIV_96M_SHIFT 0
544#define OMAP3430_DIV_96M_MASK (0x1f << 0) 544#define OMAP3430_DIV_96M_MASK (0x1f << 0)
545#define OMAP3630_DIV_96M_MASK (0x3f << 0)
545 546
546/* CM_CLKSEL4_PLL */ 547/* CM_CLKSEL4_PLL */
547#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 548#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
@@ -588,8 +589,10 @@
588/* CM_CLKSEL_DSS */ 589/* CM_CLKSEL_DSS */
589#define OMAP3430_CLKSEL_TV_SHIFT 8 590#define OMAP3430_CLKSEL_TV_SHIFT 8
590#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 591#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
592#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
591#define OMAP3430_CLKSEL_DSS1_SHIFT 0 593#define OMAP3430_CLKSEL_DSS1_SHIFT 0
592#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 594#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
595#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
593 596
594/* CM_SLEEPDEP_DSS specific bits */ 597/* CM_SLEEPDEP_DSS specific bits */
595 598
@@ -617,6 +620,7 @@
617/* CM_CLKSEL_CAM */ 620/* CM_CLKSEL_CAM */
618#define OMAP3430_CLKSEL_CAM_SHIFT 0 621#define OMAP3430_CLKSEL_CAM_SHIFT 0
619#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 622#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
623#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
620 624
621/* CM_SLEEPDEP_CAM specific bits */ 625/* CM_SLEEPDEP_CAM specific bits */
622 626
@@ -712,6 +716,7 @@
712/* CM_CLKSEL1_EMU */ 716/* CM_CLKSEL1_EMU */
713#define OMAP3430_DIV_DPLL4_SHIFT 24 717#define OMAP3430_DIV_DPLL4_SHIFT 24
714#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 718#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
719#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
715#define OMAP3430_DIV_DPLL3_SHIFT 16 720#define OMAP3430_DIV_DPLL3_SHIFT 16
716#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 721#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
717#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 722#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11