diff options
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-24xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-24xx.h | 236 |
1 files changed, 118 insertions, 118 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 297a2fe634ea..da51cc3ed7eb 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
| @@ -20,43 +20,43 @@ | |||
| 20 | 20 | ||
| 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ |
| 22 | #define OMAP24XX_EN_CAM_SHIFT 31 | 22 | #define OMAP24XX_EN_CAM_SHIFT 31 |
| 23 | #define OMAP24XX_EN_CAM (1 << 31) | 23 | #define OMAP24XX_EN_CAM_MASK (1 << 31) |
| 24 | #define OMAP24XX_EN_WDT4_SHIFT 29 | 24 | #define OMAP24XX_EN_WDT4_SHIFT 29 |
| 25 | #define OMAP24XX_EN_WDT4 (1 << 29) | 25 | #define OMAP24XX_EN_WDT4_MASK (1 << 29) |
| 26 | #define OMAP2420_EN_WDT3_SHIFT 28 | 26 | #define OMAP2420_EN_WDT3_SHIFT 28 |
| 27 | #define OMAP2420_EN_WDT3 (1 << 28) | 27 | #define OMAP2420_EN_WDT3_MASK (1 << 28) |
| 28 | #define OMAP24XX_EN_MSPRO_SHIFT 27 | 28 | #define OMAP24XX_EN_MSPRO_SHIFT 27 |
| 29 | #define OMAP24XX_EN_MSPRO (1 << 27) | 29 | #define OMAP24XX_EN_MSPRO_MASK (1 << 27) |
| 30 | #define OMAP24XX_EN_FAC_SHIFT 25 | 30 | #define OMAP24XX_EN_FAC_SHIFT 25 |
| 31 | #define OMAP24XX_EN_FAC (1 << 25) | 31 | #define OMAP24XX_EN_FAC_MASK (1 << 25) |
| 32 | #define OMAP2420_EN_EAC_SHIFT 24 | 32 | #define OMAP2420_EN_EAC_SHIFT 24 |
| 33 | #define OMAP2420_EN_EAC (1 << 24) | 33 | #define OMAP2420_EN_EAC_MASK (1 << 24) |
| 34 | #define OMAP24XX_EN_HDQ_SHIFT 23 | 34 | #define OMAP24XX_EN_HDQ_SHIFT 23 |
| 35 | #define OMAP24XX_EN_HDQ (1 << 23) | 35 | #define OMAP24XX_EN_HDQ_MASK (1 << 23) |
| 36 | #define OMAP2420_EN_I2C2_SHIFT 20 | 36 | #define OMAP2420_EN_I2C2_SHIFT 20 |
| 37 | #define OMAP2420_EN_I2C2 (1 << 20) | 37 | #define OMAP2420_EN_I2C2_MASK (1 << 20) |
| 38 | #define OMAP2420_EN_I2C1_SHIFT 19 | 38 | #define OMAP2420_EN_I2C1_SHIFT 19 |
| 39 | #define OMAP2420_EN_I2C1 (1 << 19) | 39 | #define OMAP2420_EN_I2C1_MASK (1 << 19) |
| 40 | 40 | ||
| 41 | /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ | 41 | /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ |
| 42 | #define OMAP2430_EN_MCBSP5_SHIFT 5 | 42 | #define OMAP2430_EN_MCBSP5_SHIFT 5 |
| 43 | #define OMAP2430_EN_MCBSP5 (1 << 5) | 43 | #define OMAP2430_EN_MCBSP5_MASK (1 << 5) |
| 44 | #define OMAP2430_EN_MCBSP4_SHIFT 4 | 44 | #define OMAP2430_EN_MCBSP4_SHIFT 4 |
| 45 | #define OMAP2430_EN_MCBSP4 (1 << 4) | 45 | #define OMAP2430_EN_MCBSP4_MASK (1 << 4) |
| 46 | #define OMAP2430_EN_MCBSP3_SHIFT 3 | 46 | #define OMAP2430_EN_MCBSP3_SHIFT 3 |
| 47 | #define OMAP2430_EN_MCBSP3 (1 << 3) | 47 | #define OMAP2430_EN_MCBSP3_MASK (1 << 3) |
| 48 | #define OMAP24XX_EN_SSI_SHIFT 1 | 48 | #define OMAP24XX_EN_SSI_SHIFT 1 |
| 49 | #define OMAP24XX_EN_SSI (1 << 1) | 49 | #define OMAP24XX_EN_SSI_MASK (1 << 1) |
| 50 | 50 | ||
| 51 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | 51 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ |
| 52 | #define OMAP24XX_EN_MPU_WDT_SHIFT 3 | 52 | #define OMAP24XX_EN_MPU_WDT_SHIFT 3 |
| 53 | #define OMAP24XX_EN_MPU_WDT (1 << 3) | 53 | #define OMAP24XX_EN_MPU_WDT_MASK (1 << 3) |
| 54 | 54 | ||
| 55 | /* Bits specific to each register */ | 55 | /* Bits specific to each register */ |
| 56 | 56 | ||
| 57 | /* CM_IDLEST_MPU */ | 57 | /* CM_IDLEST_MPU */ |
| 58 | /* 2430 only */ | 58 | /* 2430 only */ |
| 59 | #define OMAP2430_ST_MPU (1 << 0) | 59 | #define OMAP2430_ST_MPU_MASK (1 << 0) |
| 60 | 60 | ||
| 61 | /* CM_CLKSEL_MPU */ | 61 | /* CM_CLKSEL_MPU */ |
| 62 | #define OMAP24XX_CLKSEL_MPU_SHIFT 0 | 62 | #define OMAP24XX_CLKSEL_MPU_SHIFT 0 |
| @@ -68,46 +68,46 @@ | |||
| 68 | 68 | ||
| 69 | /* CM_FCLKEN1_CORE specific bits*/ | 69 | /* CM_FCLKEN1_CORE specific bits*/ |
| 70 | #define OMAP24XX_EN_TV_SHIFT 2 | 70 | #define OMAP24XX_EN_TV_SHIFT 2 |
| 71 | #define OMAP24XX_EN_TV (1 << 2) | 71 | #define OMAP24XX_EN_TV_MASK (1 << 2) |
| 72 | #define OMAP24XX_EN_DSS2_SHIFT 1 | 72 | #define OMAP24XX_EN_DSS2_SHIFT 1 |
| 73 | #define OMAP24XX_EN_DSS2 (1 << 1) | 73 | #define OMAP24XX_EN_DSS2_MASK (1 << 1) |
| 74 | #define OMAP24XX_EN_DSS1_SHIFT 0 | 74 | #define OMAP24XX_EN_DSS1_SHIFT 0 |
| 75 | #define OMAP24XX_EN_DSS1 (1 << 0) | 75 | #define OMAP24XX_EN_DSS1_MASK (1 << 0) |
| 76 | 76 | ||
| 77 | /* CM_FCLKEN2_CORE specific bits */ | 77 | /* CM_FCLKEN2_CORE specific bits */ |
| 78 | #define OMAP2430_EN_I2CHS2_SHIFT 20 | 78 | #define OMAP2430_EN_I2CHS2_SHIFT 20 |
| 79 | #define OMAP2430_EN_I2CHS2 (1 << 20) | 79 | #define OMAP2430_EN_I2CHS2_MASK (1 << 20) |
| 80 | #define OMAP2430_EN_I2CHS1_SHIFT 19 | 80 | #define OMAP2430_EN_I2CHS1_SHIFT 19 |
| 81 | #define OMAP2430_EN_I2CHS1 (1 << 19) | 81 | #define OMAP2430_EN_I2CHS1_MASK (1 << 19) |
| 82 | #define OMAP2430_EN_MMCHSDB2_SHIFT 17 | 82 | #define OMAP2430_EN_MMCHSDB2_SHIFT 17 |
| 83 | #define OMAP2430_EN_MMCHSDB2 (1 << 17) | 83 | #define OMAP2430_EN_MMCHSDB2_MASK (1 << 17) |
| 84 | #define OMAP2430_EN_MMCHSDB1_SHIFT 16 | 84 | #define OMAP2430_EN_MMCHSDB1_SHIFT 16 |
| 85 | #define OMAP2430_EN_MMCHSDB1 (1 << 16) | 85 | #define OMAP2430_EN_MMCHSDB1_MASK (1 << 16) |
| 86 | 86 | ||
| 87 | /* CM_ICLKEN1_CORE specific bits */ | 87 | /* CM_ICLKEN1_CORE specific bits */ |
| 88 | #define OMAP24XX_EN_MAILBOXES_SHIFT 30 | 88 | #define OMAP24XX_EN_MAILBOXES_SHIFT 30 |
| 89 | #define OMAP24XX_EN_MAILBOXES (1 << 30) | 89 | #define OMAP24XX_EN_MAILBOXES_MASK (1 << 30) |
| 90 | #define OMAP24XX_EN_DSS_SHIFT 0 | 90 | #define OMAP24XX_EN_DSS_SHIFT 0 |
| 91 | #define OMAP24XX_EN_DSS (1 << 0) | 91 | #define OMAP24XX_EN_DSS_MASK (1 << 0) |
| 92 | 92 | ||
| 93 | /* CM_ICLKEN2_CORE specific bits */ | 93 | /* CM_ICLKEN2_CORE specific bits */ |
| 94 | 94 | ||
| 95 | /* CM_ICLKEN3_CORE */ | 95 | /* CM_ICLKEN3_CORE */ |
| 96 | /* 2430 only */ | 96 | /* 2430 only */ |
| 97 | #define OMAP2430_EN_SDRC_SHIFT 2 | 97 | #define OMAP2430_EN_SDRC_SHIFT 2 |
| 98 | #define OMAP2430_EN_SDRC (1 << 2) | 98 | #define OMAP2430_EN_SDRC_MASK (1 << 2) |
| 99 | 99 | ||
| 100 | /* CM_ICLKEN4_CORE */ | 100 | /* CM_ICLKEN4_CORE */ |
| 101 | #define OMAP24XX_EN_PKA_SHIFT 4 | 101 | #define OMAP24XX_EN_PKA_SHIFT 4 |
| 102 | #define OMAP24XX_EN_PKA (1 << 4) | 102 | #define OMAP24XX_EN_PKA_MASK (1 << 4) |
| 103 | #define OMAP24XX_EN_AES_SHIFT 3 | 103 | #define OMAP24XX_EN_AES_SHIFT 3 |
| 104 | #define OMAP24XX_EN_AES (1 << 3) | 104 | #define OMAP24XX_EN_AES_MASK (1 << 3) |
| 105 | #define OMAP24XX_EN_RNG_SHIFT 2 | 105 | #define OMAP24XX_EN_RNG_SHIFT 2 |
| 106 | #define OMAP24XX_EN_RNG (1 << 2) | 106 | #define OMAP24XX_EN_RNG_MASK (1 << 2) |
| 107 | #define OMAP24XX_EN_SHA_SHIFT 1 | 107 | #define OMAP24XX_EN_SHA_SHIFT 1 |
| 108 | #define OMAP24XX_EN_SHA (1 << 1) | 108 | #define OMAP24XX_EN_SHA_MASK (1 << 1) |
| 109 | #define OMAP24XX_EN_DES_SHIFT 0 | 109 | #define OMAP24XX_EN_DES_SHIFT 0 |
| 110 | #define OMAP24XX_EN_DES (1 << 0) | 110 | #define OMAP24XX_EN_DES_MASK (1 << 0) |
| 111 | 111 | ||
| 112 | /* CM_IDLEST1_CORE specific bits */ | 112 | /* CM_IDLEST1_CORE specific bits */ |
| 113 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 | 113 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 |
| @@ -138,9 +138,9 @@ | |||
| 138 | /* CM_IDLEST2_CORE */ | 138 | /* CM_IDLEST2_CORE */ |
| 139 | #define OMAP2430_ST_MCBSP5_SHIFT 5 | 139 | #define OMAP2430_ST_MCBSP5_SHIFT 5 |
| 140 | #define OMAP2430_ST_MCBSP5_MASK (1 << 5) | 140 | #define OMAP2430_ST_MCBSP5_MASK (1 << 5) |
| 141 | #define OMAP2430_ST_MCBSP4_SHIFT 4 | 141 | #define OMAP2430_ST_MCBSP4_SHIFT 4 |
| 142 | #define OMAP2430_ST_MCBSP4_MASK (1 << 4) | 142 | #define OMAP2430_ST_MCBSP4_MASK (1 << 4) |
| 143 | #define OMAP2430_ST_MCBSP3_SHIFT 3 | 143 | #define OMAP2430_ST_MCBSP3_SHIFT 3 |
| 144 | #define OMAP2430_ST_MCBSP3_MASK (1 << 3) | 144 | #define OMAP2430_ST_MCBSP3_MASK (1 << 3) |
| 145 | #define OMAP24XX_ST_SSI_SHIFT 1 | 145 | #define OMAP24XX_ST_SSI_SHIFT 1 |
| 146 | #define OMAP24XX_ST_SSI_MASK (1 << 1) | 146 | #define OMAP24XX_ST_SSI_MASK (1 << 1) |
| @@ -162,62 +162,62 @@ | |||
| 162 | #define OMAP24XX_ST_DES_MASK (1 << 0) | 162 | #define OMAP24XX_ST_DES_MASK (1 << 0) |
| 163 | 163 | ||
| 164 | /* CM_AUTOIDLE1_CORE */ | 164 | /* CM_AUTOIDLE1_CORE */ |
| 165 | #define OMAP24XX_AUTO_CAM (1 << 31) | 165 | #define OMAP24XX_AUTO_CAM_MASK (1 << 31) |
| 166 | #define OMAP24XX_AUTO_MAILBOXES (1 << 30) | 166 | #define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30) |
| 167 | #define OMAP24XX_AUTO_WDT4 (1 << 29) | 167 | #define OMAP24XX_AUTO_WDT4_MASK (1 << 29) |
| 168 | #define OMAP2420_AUTO_WDT3 (1 << 28) | 168 | #define OMAP2420_AUTO_WDT3_MASK (1 << 28) |
| 169 | #define OMAP24XX_AUTO_MSPRO (1 << 27) | 169 | #define OMAP24XX_AUTO_MSPRO_MASK (1 << 27) |
| 170 | #define OMAP2420_AUTO_MMC (1 << 26) | 170 | #define OMAP2420_AUTO_MMC_MASK (1 << 26) |
| 171 | #define OMAP24XX_AUTO_FAC (1 << 25) | 171 | #define OMAP24XX_AUTO_FAC_MASK (1 << 25) |
| 172 | #define OMAP2420_AUTO_EAC (1 << 24) | 172 | #define OMAP2420_AUTO_EAC_MASK (1 << 24) |
| 173 | #define OMAP24XX_AUTO_HDQ (1 << 23) | 173 | #define OMAP24XX_AUTO_HDQ_MASK (1 << 23) |
| 174 | #define OMAP24XX_AUTO_UART2 (1 << 22) | 174 | #define OMAP24XX_AUTO_UART2_MASK (1 << 22) |
| 175 | #define OMAP24XX_AUTO_UART1 (1 << 21) | 175 | #define OMAP24XX_AUTO_UART1_MASK (1 << 21) |
| 176 | #define OMAP24XX_AUTO_I2C2 (1 << 20) | 176 | #define OMAP24XX_AUTO_I2C2_MASK (1 << 20) |
| 177 | #define OMAP24XX_AUTO_I2C1 (1 << 19) | 177 | #define OMAP24XX_AUTO_I2C1_MASK (1 << 19) |
| 178 | #define OMAP24XX_AUTO_MCSPI2 (1 << 18) | 178 | #define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18) |
| 179 | #define OMAP24XX_AUTO_MCSPI1 (1 << 17) | 179 | #define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17) |
| 180 | #define OMAP24XX_AUTO_MCBSP2 (1 << 16) | 180 | #define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16) |
| 181 | #define OMAP24XX_AUTO_MCBSP1 (1 << 15) | 181 | #define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15) |
| 182 | #define OMAP24XX_AUTO_GPT12 (1 << 14) | 182 | #define OMAP24XX_AUTO_GPT12_MASK (1 << 14) |
| 183 | #define OMAP24XX_AUTO_GPT11 (1 << 13) | 183 | #define OMAP24XX_AUTO_GPT11_MASK (1 << 13) |
| 184 | #define OMAP24XX_AUTO_GPT10 (1 << 12) | 184 | #define OMAP24XX_AUTO_GPT10_MASK (1 << 12) |
| 185 | #define OMAP24XX_AUTO_GPT9 (1 << 11) | 185 | #define OMAP24XX_AUTO_GPT9_MASK (1 << 11) |
| 186 | #define OMAP24XX_AUTO_GPT8 (1 << 10) | 186 | #define OMAP24XX_AUTO_GPT8_MASK (1 << 10) |
| 187 | #define OMAP24XX_AUTO_GPT7 (1 << 9) | 187 | #define OMAP24XX_AUTO_GPT7_MASK (1 << 9) |
| 188 | #define OMAP24XX_AUTO_GPT6 (1 << 8) | 188 | #define OMAP24XX_AUTO_GPT6_MASK (1 << 8) |
| 189 | #define OMAP24XX_AUTO_GPT5 (1 << 7) | 189 | #define OMAP24XX_AUTO_GPT5_MASK (1 << 7) |
| 190 | #define OMAP24XX_AUTO_GPT4 (1 << 6) | 190 | #define OMAP24XX_AUTO_GPT4_MASK (1 << 6) |
| 191 | #define OMAP24XX_AUTO_GPT3 (1 << 5) | 191 | #define OMAP24XX_AUTO_GPT3_MASK (1 << 5) |
| 192 | #define OMAP24XX_AUTO_GPT2 (1 << 4) | 192 | #define OMAP24XX_AUTO_GPT2_MASK (1 << 4) |
| 193 | #define OMAP2420_AUTO_VLYNQ (1 << 3) | 193 | #define OMAP2420_AUTO_VLYNQ_MASK (1 << 3) |
| 194 | #define OMAP24XX_AUTO_DSS (1 << 0) | 194 | #define OMAP24XX_AUTO_DSS_MASK (1 << 0) |
| 195 | 195 | ||
| 196 | /* CM_AUTOIDLE2_CORE */ | 196 | /* CM_AUTOIDLE2_CORE */ |
| 197 | #define OMAP2430_AUTO_MDM_INTC (1 << 11) | 197 | #define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11) |
| 198 | #define OMAP2430_AUTO_GPIO5 (1 << 10) | 198 | #define OMAP2430_AUTO_GPIO5_MASK (1 << 10) |
| 199 | #define OMAP2430_AUTO_MCSPI3 (1 << 9) | 199 | #define OMAP2430_AUTO_MCSPI3_MASK (1 << 9) |
| 200 | #define OMAP2430_AUTO_MMCHS2 (1 << 8) | 200 | #define OMAP2430_AUTO_MMCHS2_MASK (1 << 8) |
| 201 | #define OMAP2430_AUTO_MMCHS1 (1 << 7) | 201 | #define OMAP2430_AUTO_MMCHS1_MASK (1 << 7) |
| 202 | #define OMAP2430_AUTO_USBHS (1 << 6) | 202 | #define OMAP2430_AUTO_USBHS_MASK (1 << 6) |
| 203 | #define OMAP2430_AUTO_MCBSP5 (1 << 5) | 203 | #define OMAP2430_AUTO_MCBSP5_MASK (1 << 5) |
| 204 | #define OMAP2430_AUTO_MCBSP4 (1 << 4) | 204 | #define OMAP2430_AUTO_MCBSP4_MASK (1 << 4) |
| 205 | #define OMAP2430_AUTO_MCBSP3 (1 << 3) | 205 | #define OMAP2430_AUTO_MCBSP3_MASK (1 << 3) |
| 206 | #define OMAP24XX_AUTO_UART3 (1 << 2) | 206 | #define OMAP24XX_AUTO_UART3_MASK (1 << 2) |
| 207 | #define OMAP24XX_AUTO_SSI (1 << 1) | 207 | #define OMAP24XX_AUTO_SSI_MASK (1 << 1) |
| 208 | #define OMAP24XX_AUTO_USB (1 << 0) | 208 | #define OMAP24XX_AUTO_USB_MASK (1 << 0) |
| 209 | 209 | ||
| 210 | /* CM_AUTOIDLE3_CORE */ | 210 | /* CM_AUTOIDLE3_CORE */ |
| 211 | #define OMAP24XX_AUTO_SDRC (1 << 2) | 211 | #define OMAP24XX_AUTO_SDRC_MASK (1 << 2) |
| 212 | #define OMAP24XX_AUTO_GPMC (1 << 1) | 212 | #define OMAP24XX_AUTO_GPMC_MASK (1 << 1) |
| 213 | #define OMAP24XX_AUTO_SDMA (1 << 0) | 213 | #define OMAP24XX_AUTO_SDMA_MASK (1 << 0) |
| 214 | 214 | ||
| 215 | /* CM_AUTOIDLE4_CORE */ | 215 | /* CM_AUTOIDLE4_CORE */ |
| 216 | #define OMAP24XX_AUTO_PKA (1 << 4) | 216 | #define OMAP24XX_AUTO_PKA_MASK (1 << 4) |
| 217 | #define OMAP24XX_AUTO_AES (1 << 3) | 217 | #define OMAP24XX_AUTO_AES_MASK (1 << 3) |
| 218 | #define OMAP24XX_AUTO_RNG (1 << 2) | 218 | #define OMAP24XX_AUTO_RNG_MASK (1 << 2) |
| 219 | #define OMAP24XX_AUTO_SHA (1 << 1) | 219 | #define OMAP24XX_AUTO_SHA_MASK (1 << 1) |
| 220 | #define OMAP24XX_AUTO_DES (1 << 0) | 220 | #define OMAP24XX_AUTO_DES_MASK (1 << 0) |
| 221 | 221 | ||
| 222 | /* CM_CLKSEL1_CORE */ | 222 | /* CM_CLKSEL1_CORE */ |
| 223 | #define OMAP24XX_CLKSEL_USB_SHIFT 25 | 223 | #define OMAP24XX_CLKSEL_USB_SHIFT 25 |
| @@ -269,9 +269,9 @@ | |||
| 269 | 269 | ||
| 270 | /* CM_FCLKEN_GFX */ | 270 | /* CM_FCLKEN_GFX */ |
| 271 | #define OMAP24XX_EN_3D_SHIFT 2 | 271 | #define OMAP24XX_EN_3D_SHIFT 2 |
| 272 | #define OMAP24XX_EN_3D (1 << 2) | 272 | #define OMAP24XX_EN_3D_MASK (1 << 2) |
| 273 | #define OMAP24XX_EN_2D_SHIFT 1 | 273 | #define OMAP24XX_EN_2D_SHIFT 1 |
| 274 | #define OMAP24XX_EN_2D (1 << 1) | 274 | #define OMAP24XX_EN_2D_MASK (1 << 1) |
| 275 | 275 | ||
| 276 | /* CM_ICLKEN_GFX specific bits */ | 276 | /* CM_ICLKEN_GFX specific bits */ |
| 277 | 277 | ||
| @@ -287,13 +287,13 @@ | |||
| 287 | 287 | ||
| 288 | /* CM_ICLKEN_WKUP specific bits */ | 288 | /* CM_ICLKEN_WKUP specific bits */ |
| 289 | #define OMAP2430_EN_ICR_SHIFT 6 | 289 | #define OMAP2430_EN_ICR_SHIFT 6 |
| 290 | #define OMAP2430_EN_ICR (1 << 6) | 290 | #define OMAP2430_EN_ICR_MASK (1 << 6) |
| 291 | #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 | 291 | #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 |
| 292 | #define OMAP24XX_EN_OMAPCTRL (1 << 5) | 292 | #define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5) |
| 293 | #define OMAP24XX_EN_WDT1_SHIFT 4 | 293 | #define OMAP24XX_EN_WDT1_SHIFT 4 |
| 294 | #define OMAP24XX_EN_WDT1 (1 << 4) | 294 | #define OMAP24XX_EN_WDT1_MASK (1 << 4) |
| 295 | #define OMAP24XX_EN_32KSYNC_SHIFT 1 | 295 | #define OMAP24XX_EN_32KSYNC_SHIFT 1 |
| 296 | #define OMAP24XX_EN_32KSYNC (1 << 1) | 296 | #define OMAP24XX_EN_32KSYNC_MASK (1 << 1) |
| 297 | 297 | ||
| 298 | /* CM_IDLEST_WKUP specific bits */ | 298 | /* CM_IDLEST_WKUP specific bits */ |
| 299 | #define OMAP2430_ST_ICR_SHIFT 6 | 299 | #define OMAP2430_ST_ICR_SHIFT 6 |
| @@ -308,12 +308,12 @@ | |||
| 308 | #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) | 308 | #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) |
| 309 | 309 | ||
| 310 | /* CM_AUTOIDLE_WKUP */ | 310 | /* CM_AUTOIDLE_WKUP */ |
| 311 | #define OMAP24XX_AUTO_OMAPCTRL (1 << 5) | 311 | #define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5) |
| 312 | #define OMAP24XX_AUTO_WDT1 (1 << 4) | 312 | #define OMAP24XX_AUTO_WDT1_MASK (1 << 4) |
| 313 | #define OMAP24XX_AUTO_MPU_WDT (1 << 3) | 313 | #define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3) |
| 314 | #define OMAP24XX_AUTO_GPIOS (1 << 2) | 314 | #define OMAP24XX_AUTO_GPIOS_MASK (1 << 2) |
| 315 | #define OMAP24XX_AUTO_32KSYNC (1 << 1) | 315 | #define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1) |
| 316 | #define OMAP24XX_AUTO_GPT1 (1 << 0) | 316 | #define OMAP24XX_AUTO_GPT1_MASK (1 << 0) |
| 317 | 317 | ||
| 318 | /* CM_CLKSEL_WKUP */ | 318 | /* CM_CLKSEL_WKUP */ |
| 319 | #define OMAP24XX_CLKSEL_GPT1_SHIFT 0 | 319 | #define OMAP24XX_CLKSEL_GPT1_SHIFT 0 |
| @@ -328,12 +328,12 @@ | |||
| 328 | #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) | 328 | #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) |
| 329 | 329 | ||
| 330 | /* CM_IDLEST_CKGEN */ | 330 | /* CM_IDLEST_CKGEN */ |
| 331 | #define OMAP24XX_ST_54M_APLL (1 << 9) | 331 | #define OMAP24XX_ST_54M_APLL_MASK (1 << 9) |
| 332 | #define OMAP24XX_ST_96M_APLL (1 << 8) | 332 | #define OMAP24XX_ST_96M_APLL_MASK (1 << 8) |
| 333 | #define OMAP24XX_ST_54M_CLK (1 << 6) | 333 | #define OMAP24XX_ST_54M_CLK_MASK (1 << 6) |
| 334 | #define OMAP24XX_ST_12M_CLK (1 << 5) | 334 | #define OMAP24XX_ST_12M_CLK_MASK (1 << 5) |
| 335 | #define OMAP24XX_ST_48M_CLK (1 << 4) | 335 | #define OMAP24XX_ST_48M_CLK_MASK (1 << 4) |
| 336 | #define OMAP24XX_ST_96M_CLK (1 << 2) | 336 | #define OMAP24XX_ST_96M_CLK_MASK (1 << 2) |
| 337 | #define OMAP24XX_ST_CORE_CLK_SHIFT 0 | 337 | #define OMAP24XX_ST_CORE_CLK_SHIFT 0 |
| 338 | #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) | 338 | #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) |
| 339 | 339 | ||
| @@ -355,11 +355,11 @@ | |||
| 355 | #define OMAP24XX_DPLL_DIV_SHIFT 8 | 355 | #define OMAP24XX_DPLL_DIV_SHIFT 8 |
| 356 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) | 356 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) |
| 357 | #define OMAP24XX_54M_SOURCE_SHIFT 5 | 357 | #define OMAP24XX_54M_SOURCE_SHIFT 5 |
| 358 | #define OMAP24XX_54M_SOURCE (1 << 5) | 358 | #define OMAP24XX_54M_SOURCE_MASK (1 << 5) |
| 359 | #define OMAP2430_96M_SOURCE_SHIFT 4 | 359 | #define OMAP2430_96M_SOURCE_SHIFT 4 |
| 360 | #define OMAP2430_96M_SOURCE (1 << 4) | 360 | #define OMAP2430_96M_SOURCE_MASK (1 << 4) |
| 361 | #define OMAP24XX_48M_SOURCE_SHIFT 3 | 361 | #define OMAP24XX_48M_SOURCE_SHIFT 3 |
| 362 | #define OMAP24XX_48M_SOURCE (1 << 3) | 362 | #define OMAP24XX_48M_SOURCE_MASK (1 << 3) |
| 363 | #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 | 363 | #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 |
| 364 | #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) | 364 | #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) |
| 365 | 365 | ||
| @@ -369,29 +369,29 @@ | |||
| 369 | 369 | ||
| 370 | /* CM_FCLKEN_DSP */ | 370 | /* CM_FCLKEN_DSP */ |
| 371 | #define OMAP2420_EN_IVA_COP_SHIFT 10 | 371 | #define OMAP2420_EN_IVA_COP_SHIFT 10 |
| 372 | #define OMAP2420_EN_IVA_COP (1 << 10) | 372 | #define OMAP2420_EN_IVA_COP_MASK (1 << 10) |
| 373 | #define OMAP2420_EN_IVA_MPU_SHIFT 8 | 373 | #define OMAP2420_EN_IVA_MPU_SHIFT 8 |
| 374 | #define OMAP2420_EN_IVA_MPU (1 << 8) | 374 | #define OMAP2420_EN_IVA_MPU_MASK (1 << 8) |
| 375 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 | 375 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 |
| 376 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0) | 376 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0) |
| 377 | 377 | ||
| 378 | /* CM_ICLKEN_DSP */ | 378 | /* CM_ICLKEN_DSP */ |
| 379 | #define OMAP2420_EN_DSP_IPI_SHIFT 1 | 379 | #define OMAP2420_EN_DSP_IPI_SHIFT 1 |
| 380 | #define OMAP2420_EN_DSP_IPI (1 << 1) | 380 | #define OMAP2420_EN_DSP_IPI_MASK (1 << 1) |
| 381 | 381 | ||
| 382 | /* CM_IDLEST_DSP */ | 382 | /* CM_IDLEST_DSP */ |
| 383 | #define OMAP2420_ST_IVA (1 << 8) | 383 | #define OMAP2420_ST_IVA_MASK (1 << 8) |
| 384 | #define OMAP2420_ST_IPI (1 << 1) | 384 | #define OMAP2420_ST_IPI_MASK (1 << 1) |
| 385 | #define OMAP24XX_ST_DSP (1 << 0) | 385 | #define OMAP24XX_ST_DSP_MASK (1 << 0) |
| 386 | 386 | ||
| 387 | /* CM_AUTOIDLE_DSP */ | 387 | /* CM_AUTOIDLE_DSP */ |
| 388 | #define OMAP2420_AUTO_DSP_IPI (1 << 1) | 388 | #define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1) |
| 389 | 389 | ||
| 390 | /* CM_CLKSEL_DSP */ | 390 | /* CM_CLKSEL_DSP */ |
| 391 | #define OMAP2420_SYNC_IVA (1 << 13) | 391 | #define OMAP2420_SYNC_IVA_MASK (1 << 13) |
| 392 | #define OMAP2420_CLKSEL_IVA_SHIFT 8 | 392 | #define OMAP2420_CLKSEL_IVA_SHIFT 8 |
| 393 | #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) | 393 | #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) |
| 394 | #define OMAP24XX_SYNC_DSP (1 << 7) | 394 | #define OMAP24XX_SYNC_DSP_MASK (1 << 7) |
| 395 | #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 | 395 | #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 |
| 396 | #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) | 396 | #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) |
| 397 | #define OMAP24XX_CLKSEL_DSP_SHIFT 0 | 397 | #define OMAP24XX_CLKSEL_DSP_SHIFT 0 |
| @@ -406,24 +406,24 @@ | |||
| 406 | /* CM_FCLKEN_MDM */ | 406 | /* CM_FCLKEN_MDM */ |
| 407 | /* 2430 only */ | 407 | /* 2430 only */ |
| 408 | #define OMAP2430_EN_OSC_SHIFT 1 | 408 | #define OMAP2430_EN_OSC_SHIFT 1 |
| 409 | #define OMAP2430_EN_OSC (1 << 1) | 409 | #define OMAP2430_EN_OSC_MASK (1 << 1) |
| 410 | 410 | ||
| 411 | /* CM_ICLKEN_MDM */ | 411 | /* CM_ICLKEN_MDM */ |
| 412 | /* 2430 only */ | 412 | /* 2430 only */ |
| 413 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 | 413 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 |
| 414 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0) | 414 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0) |
| 415 | 415 | ||
| 416 | /* CM_IDLEST_MDM specific bits */ | 416 | /* CM_IDLEST_MDM specific bits */ |
| 417 | /* 2430 only */ | 417 | /* 2430 only */ |
| 418 | 418 | ||
| 419 | /* CM_AUTOIDLE_MDM */ | 419 | /* CM_AUTOIDLE_MDM */ |
| 420 | /* 2430 only */ | 420 | /* 2430 only */ |
| 421 | #define OMAP2430_AUTO_OSC (1 << 1) | 421 | #define OMAP2430_AUTO_OSC_MASK (1 << 1) |
| 422 | #define OMAP2430_AUTO_MDM (1 << 0) | 422 | #define OMAP2430_AUTO_MDM_MASK (1 << 0) |
| 423 | 423 | ||
| 424 | /* CM_CLKSEL_MDM */ | 424 | /* CM_CLKSEL_MDM */ |
| 425 | /* 2430 only */ | 425 | /* 2430 only */ |
| 426 | #define OMAP2430_SYNC_MDM (1 << 4) | 426 | #define OMAP2430_SYNC_MDM_MASK (1 << 4) |
| 427 | #define OMAP2430_CLKSEL_MDM_SHIFT 0 | 427 | #define OMAP2430_CLKSEL_MDM_SHIFT 0 |
| 428 | #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) | 428 | #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) |
| 429 | 429 | ||