diff options
Diffstat (limited to 'arch/arm/mach-omap2/clockdomains.h')
-rw-r--r-- | arch/arm/mach-omap2/clockdomains.h | 118 |
1 files changed, 89 insertions, 29 deletions
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index cd86dcc7b424..281d5da19188 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h | |||
@@ -14,12 +14,29 @@ | |||
14 | 14 | ||
15 | /* | 15 | /* |
16 | * OMAP2/3-common clockdomains | 16 | * OMAP2/3-common clockdomains |
17 | * | ||
18 | * Even though the 2420 has a single PRCM module from the | ||
19 | * interconnect's perspective, internally it does appear to have | ||
20 | * separate PRM and CM clockdomains. The usual test case is | ||
21 | * sys_clkout/sys_clkout2. | ||
17 | */ | 22 | */ |
18 | 23 | ||
19 | /* This is an implicit clockdomain - it is never defined as such in TRM */ | 24 | /* This is an implicit clockdomain - it is never defined as such in TRM */ |
20 | static struct clockdomain wkup_clkdm = { | 25 | static struct clockdomain wkup_clkdm = { |
21 | .name = "wkup_clkdm", | 26 | .name = "wkup_clkdm", |
22 | .pwrdm_name = "wkup_pwrdm", | 27 | .pwrdm = { .name = "wkup_pwrdm" }, |
28 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | ||
29 | }; | ||
30 | |||
31 | static struct clockdomain prm_clkdm = { | ||
32 | .name = "prm_clkdm", | ||
33 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
34 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | ||
35 | }; | ||
36 | |||
37 | static struct clockdomain cm_clkdm = { | ||
38 | .name = "cm_clkdm", | ||
39 | .pwrdm = { .name = "core_pwrdm" }, | ||
23 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | 40 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), |
24 | }; | 41 | }; |
25 | 42 | ||
@@ -31,7 +48,7 @@ static struct clockdomain wkup_clkdm = { | |||
31 | 48 | ||
32 | static struct clockdomain mpu_2420_clkdm = { | 49 | static struct clockdomain mpu_2420_clkdm = { |
33 | .name = "mpu_clkdm", | 50 | .name = "mpu_clkdm", |
34 | .pwrdm_name = "mpu_pwrdm", | 51 | .pwrdm = { .name = "mpu_pwrdm" }, |
35 | .flags = CLKDM_CAN_HWSUP, | 52 | .flags = CLKDM_CAN_HWSUP, |
36 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 53 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
37 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 54 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
@@ -39,7 +56,7 @@ static struct clockdomain mpu_2420_clkdm = { | |||
39 | 56 | ||
40 | static struct clockdomain iva1_2420_clkdm = { | 57 | static struct clockdomain iva1_2420_clkdm = { |
41 | .name = "iva1_clkdm", | 58 | .name = "iva1_clkdm", |
42 | .pwrdm_name = "dsp_pwrdm", | 59 | .pwrdm = { .name = "dsp_pwrdm" }, |
43 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 60 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
44 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, | 61 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, |
45 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 62 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
@@ -56,7 +73,7 @@ static struct clockdomain iva1_2420_clkdm = { | |||
56 | 73 | ||
57 | static struct clockdomain mpu_2430_clkdm = { | 74 | static struct clockdomain mpu_2430_clkdm = { |
58 | .name = "mpu_clkdm", | 75 | .name = "mpu_clkdm", |
59 | .pwrdm_name = "mpu_pwrdm", | 76 | .pwrdm = { .name = "mpu_pwrdm" }, |
60 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 77 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
61 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 78 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
62 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
@@ -64,7 +81,7 @@ static struct clockdomain mpu_2430_clkdm = { | |||
64 | 81 | ||
65 | static struct clockdomain mdm_clkdm = { | 82 | static struct clockdomain mdm_clkdm = { |
66 | .name = "mdm_clkdm", | 83 | .name = "mdm_clkdm", |
67 | .pwrdm_name = "mdm_pwrdm", | 84 | .pwrdm = { .name = "mdm_pwrdm" }, |
68 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 85 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
69 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, | 86 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, |
70 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
@@ -81,7 +98,7 @@ static struct clockdomain mdm_clkdm = { | |||
81 | 98 | ||
82 | static struct clockdomain dsp_clkdm = { | 99 | static struct clockdomain dsp_clkdm = { |
83 | .name = "dsp_clkdm", | 100 | .name = "dsp_clkdm", |
84 | .pwrdm_name = "dsp_pwrdm", | 101 | .pwrdm = { .name = "dsp_pwrdm" }, |
85 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 102 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
86 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, | 103 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, |
87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 104 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
@@ -89,7 +106,7 @@ static struct clockdomain dsp_clkdm = { | |||
89 | 106 | ||
90 | static struct clockdomain gfx_24xx_clkdm = { | 107 | static struct clockdomain gfx_24xx_clkdm = { |
91 | .name = "gfx_clkdm", | 108 | .name = "gfx_clkdm", |
92 | .pwrdm_name = "gfx_pwrdm", | 109 | .pwrdm = { .name = "gfx_pwrdm" }, |
93 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 110 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
94 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, | 111 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, |
95 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 112 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
@@ -97,7 +114,7 @@ static struct clockdomain gfx_24xx_clkdm = { | |||
97 | 114 | ||
98 | static struct clockdomain core_l3_24xx_clkdm = { | 115 | static struct clockdomain core_l3_24xx_clkdm = { |
99 | .name = "core_l3_clkdm", | 116 | .name = "core_l3_clkdm", |
100 | .pwrdm_name = "core_pwrdm", | 117 | .pwrdm = { .name = "core_pwrdm" }, |
101 | .flags = CLKDM_CAN_HWSUP, | 118 | .flags = CLKDM_CAN_HWSUP, |
102 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, | 119 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, |
103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 120 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
@@ -105,7 +122,7 @@ static struct clockdomain core_l3_24xx_clkdm = { | |||
105 | 122 | ||
106 | static struct clockdomain core_l4_24xx_clkdm = { | 123 | static struct clockdomain core_l4_24xx_clkdm = { |
107 | .name = "core_l4_clkdm", | 124 | .name = "core_l4_clkdm", |
108 | .pwrdm_name = "core_pwrdm", | 125 | .pwrdm = { .name = "core_pwrdm" }, |
109 | .flags = CLKDM_CAN_HWSUP, | 126 | .flags = CLKDM_CAN_HWSUP, |
110 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, | 127 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, |
111 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 128 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
@@ -113,7 +130,7 @@ static struct clockdomain core_l4_24xx_clkdm = { | |||
113 | 130 | ||
114 | static struct clockdomain dss_24xx_clkdm = { | 131 | static struct clockdomain dss_24xx_clkdm = { |
115 | .name = "dss_clkdm", | 132 | .name = "dss_clkdm", |
116 | .pwrdm_name = "core_pwrdm", | 133 | .pwrdm = { .name = "core_pwrdm" }, |
117 | .flags = CLKDM_CAN_HWSUP, | 134 | .flags = CLKDM_CAN_HWSUP, |
118 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, | 135 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, |
119 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 136 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
@@ -130,7 +147,7 @@ static struct clockdomain dss_24xx_clkdm = { | |||
130 | 147 | ||
131 | static struct clockdomain mpu_34xx_clkdm = { | 148 | static struct clockdomain mpu_34xx_clkdm = { |
132 | .name = "mpu_clkdm", | 149 | .name = "mpu_clkdm", |
133 | .pwrdm_name = "mpu_pwrdm", | 150 | .pwrdm = { .name = "mpu_pwrdm" }, |
134 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, | 151 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, |
135 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, | 152 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, |
136 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 153 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
@@ -138,7 +155,7 @@ static struct clockdomain mpu_34xx_clkdm = { | |||
138 | 155 | ||
139 | static struct clockdomain neon_clkdm = { | 156 | static struct clockdomain neon_clkdm = { |
140 | .name = "neon_clkdm", | 157 | .name = "neon_clkdm", |
141 | .pwrdm_name = "neon_pwrdm", | 158 | .pwrdm = { .name = "neon_pwrdm" }, |
142 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 159 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
143 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, | 160 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, |
144 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 161 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
@@ -146,7 +163,7 @@ static struct clockdomain neon_clkdm = { | |||
146 | 163 | ||
147 | static struct clockdomain iva2_clkdm = { | 164 | static struct clockdomain iva2_clkdm = { |
148 | .name = "iva2_clkdm", | 165 | .name = "iva2_clkdm", |
149 | .pwrdm_name = "iva2_pwrdm", | 166 | .pwrdm = { .name = "iva2_pwrdm" }, |
150 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 167 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
151 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, | 168 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, |
152 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 169 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
@@ -154,7 +171,7 @@ static struct clockdomain iva2_clkdm = { | |||
154 | 171 | ||
155 | static struct clockdomain gfx_3430es1_clkdm = { | 172 | static struct clockdomain gfx_3430es1_clkdm = { |
156 | .name = "gfx_clkdm", | 173 | .name = "gfx_clkdm", |
157 | .pwrdm_name = "gfx_pwrdm", | 174 | .pwrdm = { .name = "gfx_pwrdm" }, |
158 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 175 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
159 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, | 176 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, |
160 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), | 177 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), |
@@ -162,10 +179,10 @@ static struct clockdomain gfx_3430es1_clkdm = { | |||
162 | 179 | ||
163 | static struct clockdomain sgx_clkdm = { | 180 | static struct clockdomain sgx_clkdm = { |
164 | .name = "sgx_clkdm", | 181 | .name = "sgx_clkdm", |
165 | .pwrdm_name = "sgx_pwrdm", | 182 | .pwrdm = { .name = "sgx_pwrdm" }, |
166 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 183 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
167 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, | 184 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, |
168 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 185 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
169 | }; | 186 | }; |
170 | 187 | ||
171 | /* | 188 | /* |
@@ -177,7 +194,7 @@ static struct clockdomain sgx_clkdm = { | |||
177 | */ | 194 | */ |
178 | static struct clockdomain d2d_clkdm = { | 195 | static struct clockdomain d2d_clkdm = { |
179 | .name = "d2d_clkdm", | 196 | .name = "d2d_clkdm", |
180 | .pwrdm_name = "core_pwrdm", | 197 | .pwrdm = { .name = "core_pwrdm" }, |
181 | .flags = CLKDM_CAN_HWSUP, | 198 | .flags = CLKDM_CAN_HWSUP, |
182 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, | 199 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, |
183 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 200 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
@@ -185,7 +202,7 @@ static struct clockdomain d2d_clkdm = { | |||
185 | 202 | ||
186 | static struct clockdomain core_l3_34xx_clkdm = { | 203 | static struct clockdomain core_l3_34xx_clkdm = { |
187 | .name = "core_l3_clkdm", | 204 | .name = "core_l3_clkdm", |
188 | .pwrdm_name = "core_pwrdm", | 205 | .pwrdm = { .name = "core_pwrdm" }, |
189 | .flags = CLKDM_CAN_HWSUP, | 206 | .flags = CLKDM_CAN_HWSUP, |
190 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, | 207 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, |
191 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 208 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
@@ -193,7 +210,7 @@ static struct clockdomain core_l3_34xx_clkdm = { | |||
193 | 210 | ||
194 | static struct clockdomain core_l4_34xx_clkdm = { | 211 | static struct clockdomain core_l4_34xx_clkdm = { |
195 | .name = "core_l4_clkdm", | 212 | .name = "core_l4_clkdm", |
196 | .pwrdm_name = "core_pwrdm", | 213 | .pwrdm = { .name = "core_pwrdm" }, |
197 | .flags = CLKDM_CAN_HWSUP, | 214 | .flags = CLKDM_CAN_HWSUP, |
198 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, | 215 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, |
199 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 216 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
@@ -201,7 +218,7 @@ static struct clockdomain core_l4_34xx_clkdm = { | |||
201 | 218 | ||
202 | static struct clockdomain dss_34xx_clkdm = { | 219 | static struct clockdomain dss_34xx_clkdm = { |
203 | .name = "dss_clkdm", | 220 | .name = "dss_clkdm", |
204 | .pwrdm_name = "dss_pwrdm", | 221 | .pwrdm = { .name = "dss_pwrdm" }, |
205 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 222 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
206 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, | 223 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, |
207 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 224 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
@@ -209,7 +226,7 @@ static struct clockdomain dss_34xx_clkdm = { | |||
209 | 226 | ||
210 | static struct clockdomain cam_clkdm = { | 227 | static struct clockdomain cam_clkdm = { |
211 | .name = "cam_clkdm", | 228 | .name = "cam_clkdm", |
212 | .pwrdm_name = "cam_pwrdm", | 229 | .pwrdm = { .name = "cam_pwrdm" }, |
213 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 230 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
214 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, | 231 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, |
215 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 232 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
@@ -217,28 +234,62 @@ static struct clockdomain cam_clkdm = { | |||
217 | 234 | ||
218 | static struct clockdomain usbhost_clkdm = { | 235 | static struct clockdomain usbhost_clkdm = { |
219 | .name = "usbhost_clkdm", | 236 | .name = "usbhost_clkdm", |
220 | .pwrdm_name = "usbhost_pwrdm", | 237 | .pwrdm = { .name = "usbhost_pwrdm" }, |
221 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 238 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
222 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, | 239 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, |
223 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 240 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
224 | }; | 241 | }; |
225 | 242 | ||
226 | static struct clockdomain per_clkdm = { | 243 | static struct clockdomain per_clkdm = { |
227 | .name = "per_clkdm", | 244 | .name = "per_clkdm", |
228 | .pwrdm_name = "per_pwrdm", | 245 | .pwrdm = { .name = "per_pwrdm" }, |
229 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 246 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
230 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, | 247 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, |
231 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 248 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
232 | }; | 249 | }; |
233 | 250 | ||
251 | /* | ||
252 | * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is | ||
253 | * switched of even if sdti is in use | ||
254 | */ | ||
234 | static struct clockdomain emu_clkdm = { | 255 | static struct clockdomain emu_clkdm = { |
235 | .name = "emu_clkdm", | 256 | .name = "emu_clkdm", |
236 | .pwrdm_name = "emu_pwrdm", | 257 | .pwrdm = { .name = "emu_pwrdm" }, |
237 | .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP, | 258 | .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, |
238 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, | 259 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, |
239 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 260 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
240 | }; | 261 | }; |
241 | 262 | ||
263 | static struct clockdomain dpll1_clkdm = { | ||
264 | .name = "dpll1_clkdm", | ||
265 | .pwrdm = { .name = "dpll1_pwrdm" }, | ||
266 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
267 | }; | ||
268 | |||
269 | static struct clockdomain dpll2_clkdm = { | ||
270 | .name = "dpll2_clkdm", | ||
271 | .pwrdm = { .name = "dpll2_pwrdm" }, | ||
272 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
273 | }; | ||
274 | |||
275 | static struct clockdomain dpll3_clkdm = { | ||
276 | .name = "dpll3_clkdm", | ||
277 | .pwrdm = { .name = "dpll3_pwrdm" }, | ||
278 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
279 | }; | ||
280 | |||
281 | static struct clockdomain dpll4_clkdm = { | ||
282 | .name = "dpll4_clkdm", | ||
283 | .pwrdm = { .name = "dpll4_pwrdm" }, | ||
284 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
285 | }; | ||
286 | |||
287 | static struct clockdomain dpll5_clkdm = { | ||
288 | .name = "dpll5_clkdm", | ||
289 | .pwrdm = { .name = "dpll5_pwrdm" }, | ||
290 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | ||
291 | }; | ||
292 | |||
242 | #endif /* CONFIG_ARCH_OMAP34XX */ | 293 | #endif /* CONFIG_ARCH_OMAP34XX */ |
243 | 294 | ||
244 | /* | 295 | /* |
@@ -247,14 +298,16 @@ static struct clockdomain emu_clkdm = { | |||
247 | 298 | ||
248 | static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { | 299 | static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { |
249 | { | 300 | { |
250 | .pwrdm_name = "mpu_pwrdm", | 301 | .pwrdm = { .name = "mpu_pwrdm" }, |
251 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 302 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
252 | }, | 303 | }, |
253 | { | 304 | { |
254 | .pwrdm_name = "iva2_pwrdm", | 305 | .pwrdm = { .name = "iva2_pwrdm" }, |
255 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 306 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
256 | }, | 307 | }, |
257 | { NULL } | 308 | { |
309 | .pwrdm = { .name = NULL }, | ||
310 | } | ||
258 | }; | 311 | }; |
259 | 312 | ||
260 | /* | 313 | /* |
@@ -264,6 +317,8 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { | |||
264 | static struct clockdomain *clockdomains_omap[] = { | 317 | static struct clockdomain *clockdomains_omap[] = { |
265 | 318 | ||
266 | &wkup_clkdm, | 319 | &wkup_clkdm, |
320 | &cm_clkdm, | ||
321 | &prm_clkdm, | ||
267 | 322 | ||
268 | #ifdef CONFIG_ARCH_OMAP2420 | 323 | #ifdef CONFIG_ARCH_OMAP2420 |
269 | &mpu_2420_clkdm, | 324 | &mpu_2420_clkdm, |
@@ -297,6 +352,11 @@ static struct clockdomain *clockdomains_omap[] = { | |||
297 | &usbhost_clkdm, | 352 | &usbhost_clkdm, |
298 | &per_clkdm, | 353 | &per_clkdm, |
299 | &emu_clkdm, | 354 | &emu_clkdm, |
355 | &dpll1_clkdm, | ||
356 | &dpll2_clkdm, | ||
357 | &dpll3_clkdm, | ||
358 | &dpll4_clkdm, | ||
359 | &dpll5_clkdm, | ||
300 | #endif | 360 | #endif |
301 | 361 | ||
302 | NULL, | 362 | NULL, |