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Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c674
1 files changed, 474 insertions, 200 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 217cce489738..c426adccad06 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -30,11 +30,18 @@
30 30
31#include "clock.h" 31#include "clock.h"
32#include "clock44xx.h" 32#include "clock44xx.h"
33#include "cm.h" 33#include "cm1_44xx.h"
34#include "cm2_44xx.h"
34#include "cm-regbits-44xx.h" 35#include "cm-regbits-44xx.h"
35#include "prm.h" 36#include "prm44xx.h"
37#include "prm44xx.h"
36#include "prm-regbits-44xx.h" 38#include "prm-regbits-44xx.h"
37#include "control.h" 39#include "control.h"
40#include "scrm44xx.h"
41
42/* OMAP4 modulemode control */
43#define OMAP4430_MODULEMODE_HWCTRL 0
44#define OMAP4430_MODULEMODE_SWCTRL 1
38 45
39/* Root clocks */ 46/* Root clocks */
40 47
@@ -47,7 +54,9 @@ static struct clk extalt_clkin_ck = {
47static struct clk pad_clks_ck = { 54static struct clk pad_clks_ck = {
48 .name = "pad_clks_ck", 55 .name = "pad_clks_ck",
49 .rate = 12000000, 56 .rate = 12000000,
50 .ops = &clkops_null, 57 .ops = &clkops_omap2_dflt,
58 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
59 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
51}; 60};
52 61
53static struct clk pad_slimbus_core_clks_ck = { 62static struct clk pad_slimbus_core_clks_ck = {
@@ -65,7 +74,9 @@ static struct clk secure_32k_clk_src_ck = {
65static struct clk slimbus_clk = { 74static struct clk slimbus_clk = {
66 .name = "slimbus_clk", 75 .name = "slimbus_clk",
67 .rate = 12000000, 76 .rate = 12000000,
68 .ops = &clkops_null, 77 .ops = &clkops_omap2_dflt,
78 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
79 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
69}; 80};
70 81
71static struct clk sys_32k_ck = { 82static struct clk sys_32k_ck = {
@@ -265,18 +276,71 @@ static struct clk dpll_abe_ck = {
265 .set_rate = &omap3_noncore_dpll_set_rate, 276 .set_rate = &omap3_noncore_dpll_set_rate,
266}; 277};
267 278
279static struct clk dpll_abe_x2_ck = {
280 .name = "dpll_abe_x2_ck",
281 .parent = &dpll_abe_ck,
282 .ops = &clkops_null,
283 .recalc = &omap3_clkoutx2_recalc,
284};
285
286static const struct clksel_rate div31_1to31_rates[] = {
287 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
288 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
289 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
290 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
291 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
292 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
293 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
294 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
295 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
296 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
297 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
298 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
299 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
300 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
301 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
302 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
303 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
304 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
305 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
306 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
307 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
308 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
309 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
310 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
311 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
312 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
313 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
314 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
315 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
316 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
317 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
318 { .div = 0 },
319};
320
321static const struct clksel dpll_abe_m2x2_div[] = {
322 { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
323 { .parent = NULL },
324};
325
268static struct clk dpll_abe_m2x2_ck = { 326static struct clk dpll_abe_m2x2_ck = {
269 .name = "dpll_abe_m2x2_ck", 327 .name = "dpll_abe_m2x2_ck",
270 .parent = &dpll_abe_ck, 328 .parent = &dpll_abe_x2_ck,
329 .clksel = dpll_abe_m2x2_div,
330 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
331 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
271 .ops = &clkops_null, 332 .ops = &clkops_null,
272 .recalc = &followparent_recalc, 333 .recalc = &omap2_clksel_recalc,
334 .round_rate = &omap2_clksel_round_rate,
335 .set_rate = &omap2_clksel_set_rate,
273}; 336};
274 337
275static struct clk abe_24m_fclk = { 338static struct clk abe_24m_fclk = {
276 .name = "abe_24m_fclk", 339 .name = "abe_24m_fclk",
277 .parent = &dpll_abe_m2x2_ck, 340 .parent = &dpll_abe_m2x2_ck,
278 .ops = &clkops_null, 341 .ops = &clkops_null,
279 .recalc = &followparent_recalc, 342 .fixed_div = 8,
343 .recalc = &omap_fixed_divisor_recalc,
280}; 344};
281 345
282static const struct clksel_rate div3_1to4_rates[] = { 346static const struct clksel_rate div3_1to4_rates[] = {
@@ -326,50 +390,10 @@ static struct clk aess_fclk = {
326 .set_rate = &omap2_clksel_set_rate, 390 .set_rate = &omap2_clksel_set_rate,
327}; 391};
328 392
329static const struct clksel_rate div31_1to31_rates[] = { 393static struct clk dpll_abe_m3x2_ck = {
330 { .div = 1, .val = 1, .flags = RATE_IN_4430 }, 394 .name = "dpll_abe_m3x2_ck",
331 { .div = 2, .val = 2, .flags = RATE_IN_4430 }, 395 .parent = &dpll_abe_x2_ck,
332 { .div = 3, .val = 3, .flags = RATE_IN_4430 }, 396 .clksel = dpll_abe_m2x2_div,
333 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
334 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
335 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
336 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
337 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
338 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
339 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
340 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
341 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
342 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
343 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
344 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
345 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
346 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
347 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
348 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
349 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
350 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
351 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
352 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
353 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
354 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
355 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
356 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
357 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
358 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
359 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
360 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
361 { .div = 0 },
362};
363
364static const struct clksel dpll_abe_m3_div[] = {
365 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
366 { .parent = NULL },
367};
368
369static struct clk dpll_abe_m3_ck = {
370 .name = "dpll_abe_m3_ck",
371 .parent = &dpll_abe_ck,
372 .clksel = dpll_abe_m3_div,
373 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, 397 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
374 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 398 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
375 .ops = &clkops_null, 399 .ops = &clkops_null,
@@ -380,7 +404,7 @@ static struct clk dpll_abe_m3_ck = {
380 404
381static const struct clksel core_hsd_byp_clk_mux_sel[] = { 405static const struct clksel core_hsd_byp_clk_mux_sel[] = {
382 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 406 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
383 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, 407 { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
384 { .parent = NULL }, 408 { .parent = NULL },
385}; 409};
386 410
@@ -424,15 +448,22 @@ static struct clk dpll_core_ck = {
424 .recalc = &omap3_dpll_recalc, 448 .recalc = &omap3_dpll_recalc,
425}; 449};
426 450
427static const struct clksel dpll_core_m6_div[] = { 451static struct clk dpll_core_x2_ck = {
428 { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, 452 .name = "dpll_core_x2_ck",
453 .parent = &dpll_core_ck,
454 .ops = &clkops_null,
455 .recalc = &omap3_clkoutx2_recalc,
456};
457
458static const struct clksel dpll_core_m6x2_div[] = {
459 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
429 { .parent = NULL }, 460 { .parent = NULL },
430}; 461};
431 462
432static struct clk dpll_core_m6_ck = { 463static struct clk dpll_core_m6x2_ck = {
433 .name = "dpll_core_m6_ck", 464 .name = "dpll_core_m6x2_ck",
434 .parent = &dpll_core_ck, 465 .parent = &dpll_core_x2_ck,
435 .clksel = dpll_core_m6_div, 466 .clksel = dpll_core_m6x2_div,
436 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, 467 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
437 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, 468 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
438 .ops = &clkops_null, 469 .ops = &clkops_null,
@@ -443,7 +474,7 @@ static struct clk dpll_core_m6_ck = {
443 474
444static const struct clksel dbgclk_mux_sel[] = { 475static const struct clksel dbgclk_mux_sel[] = {
445 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 476 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
446 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, 477 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
447 { .parent = NULL }, 478 { .parent = NULL },
448}; 479};
449 480
@@ -454,10 +485,15 @@ static struct clk dbgclk_mux_ck = {
454 .recalc = &followparent_recalc, 485 .recalc = &followparent_recalc,
455}; 486};
456 487
488static const struct clksel dpll_core_m2_div[] = {
489 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
490 { .parent = NULL },
491};
492
457static struct clk dpll_core_m2_ck = { 493static struct clk dpll_core_m2_ck = {
458 .name = "dpll_core_m2_ck", 494 .name = "dpll_core_m2_ck",
459 .parent = &dpll_core_ck, 495 .parent = &dpll_core_ck,
460 .clksel = dpll_core_m6_div, 496 .clksel = dpll_core_m2_div,
461 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, 497 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
462 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 498 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
463 .ops = &clkops_null, 499 .ops = &clkops_null,
@@ -470,13 +506,14 @@ static struct clk ddrphy_ck = {
470 .name = "ddrphy_ck", 506 .name = "ddrphy_ck",
471 .parent = &dpll_core_m2_ck, 507 .parent = &dpll_core_m2_ck,
472 .ops = &clkops_null, 508 .ops = &clkops_null,
473 .recalc = &followparent_recalc, 509 .fixed_div = 2,
510 .recalc = &omap_fixed_divisor_recalc,
474}; 511};
475 512
476static struct clk dpll_core_m5_ck = { 513static struct clk dpll_core_m5x2_ck = {
477 .name = "dpll_core_m5_ck", 514 .name = "dpll_core_m5x2_ck",
478 .parent = &dpll_core_ck, 515 .parent = &dpll_core_x2_ck,
479 .clksel = dpll_core_m6_div, 516 .clksel = dpll_core_m6x2_div,
480 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, 517 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
481 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, 518 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
482 .ops = &clkops_null, 519 .ops = &clkops_null,
@@ -486,13 +523,13 @@ static struct clk dpll_core_m5_ck = {
486}; 523};
487 524
488static const struct clksel div_core_div[] = { 525static const struct clksel div_core_div[] = {
489 { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates }, 526 { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
490 { .parent = NULL }, 527 { .parent = NULL },
491}; 528};
492 529
493static struct clk div_core_ck = { 530static struct clk div_core_ck = {
494 .name = "div_core_ck", 531 .name = "div_core_ck",
495 .parent = &dpll_core_m5_ck, 532 .parent = &dpll_core_m5x2_ck,
496 .clksel = div_core_div, 533 .clksel = div_core_div,
497 .clksel_reg = OMAP4430_CM_CLKSEL_CORE, 534 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
498 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, 535 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
@@ -511,13 +548,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
511}; 548};
512 549
513static const struct clksel div_iva_hs_clk_div[] = { 550static const struct clksel div_iva_hs_clk_div[] = {
514 { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates }, 551 { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
515 { .parent = NULL }, 552 { .parent = NULL },
516}; 553};
517 554
518static struct clk div_iva_hs_clk = { 555static struct clk div_iva_hs_clk = {
519 .name = "div_iva_hs_clk", 556 .name = "div_iva_hs_clk",
520 .parent = &dpll_core_m5_ck, 557 .parent = &dpll_core_m5x2_ck,
521 .clksel = div_iva_hs_clk_div, 558 .clksel = div_iva_hs_clk_div,
522 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, 559 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
523 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, 560 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
@@ -529,7 +566,7 @@ static struct clk div_iva_hs_clk = {
529 566
530static struct clk div_mpu_hs_clk = { 567static struct clk div_mpu_hs_clk = {
531 .name = "div_mpu_hs_clk", 568 .name = "div_mpu_hs_clk",
532 .parent = &dpll_core_m5_ck, 569 .parent = &dpll_core_m5x2_ck,
533 .clksel = div_iva_hs_clk_div, 570 .clksel = div_iva_hs_clk_div,
534 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, 571 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
535 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, 572 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
@@ -539,10 +576,10 @@ static struct clk div_mpu_hs_clk = {
539 .set_rate = &omap2_clksel_set_rate, 576 .set_rate = &omap2_clksel_set_rate,
540}; 577};
541 578
542static struct clk dpll_core_m4_ck = { 579static struct clk dpll_core_m4x2_ck = {
543 .name = "dpll_core_m4_ck", 580 .name = "dpll_core_m4x2_ck",
544 .parent = &dpll_core_ck, 581 .parent = &dpll_core_x2_ck,
545 .clksel = dpll_core_m6_div, 582 .clksel = dpll_core_m6x2_div,
546 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, 583 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
547 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, 584 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
548 .ops = &clkops_null, 585 .ops = &clkops_null,
@@ -553,15 +590,21 @@ static struct clk dpll_core_m4_ck = {
553 590
554static struct clk dll_clk_div_ck = { 591static struct clk dll_clk_div_ck = {
555 .name = "dll_clk_div_ck", 592 .name = "dll_clk_div_ck",
556 .parent = &dpll_core_m4_ck, 593 .parent = &dpll_core_m4x2_ck,
557 .ops = &clkops_null, 594 .ops = &clkops_null,
558 .recalc = &followparent_recalc, 595 .fixed_div = 2,
596 .recalc = &omap_fixed_divisor_recalc,
597};
598
599static const struct clksel dpll_abe_m2_div[] = {
600 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
601 { .parent = NULL },
559}; 602};
560 603
561static struct clk dpll_abe_m2_ck = { 604static struct clk dpll_abe_m2_ck = {
562 .name = "dpll_abe_m2_ck", 605 .name = "dpll_abe_m2_ck",
563 .parent = &dpll_abe_ck, 606 .parent = &dpll_abe_ck,
564 .clksel = dpll_abe_m3_div, 607 .clksel = dpll_abe_m2_div,
565 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, 608 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
566 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 609 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
567 .ops = &clkops_null, 610 .ops = &clkops_null,
@@ -570,22 +613,24 @@ static struct clk dpll_abe_m2_ck = {
570 .set_rate = &omap2_clksel_set_rate, 613 .set_rate = &omap2_clksel_set_rate,
571}; 614};
572 615
573static struct clk dpll_core_m3_ck = { 616static struct clk dpll_core_m3x2_ck = {
574 .name = "dpll_core_m3_ck", 617 .name = "dpll_core_m3x2_ck",
575 .parent = &dpll_core_ck, 618 .parent = &dpll_core_x2_ck,
576 .clksel = dpll_core_m6_div, 619 .clksel = dpll_core_m6x2_div,
577 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, 620 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
578 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 621 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
579 .ops = &clkops_null, 622 .ops = &clkops_omap2_dflt,
623 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
624 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
580 .recalc = &omap2_clksel_recalc, 625 .recalc = &omap2_clksel_recalc,
581 .round_rate = &omap2_clksel_round_rate, 626 .round_rate = &omap2_clksel_round_rate,
582 .set_rate = &omap2_clksel_set_rate, 627 .set_rate = &omap2_clksel_set_rate,
583}; 628};
584 629
585static struct clk dpll_core_m7_ck = { 630static struct clk dpll_core_m7x2_ck = {
586 .name = "dpll_core_m7_ck", 631 .name = "dpll_core_m7x2_ck",
587 .parent = &dpll_core_ck, 632 .parent = &dpll_core_x2_ck,
588 .clksel = dpll_core_m6_div, 633 .clksel = dpll_core_m6x2_div,
589 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, 634 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
590 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, 635 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
591 .ops = &clkops_null, 636 .ops = &clkops_null,
@@ -603,8 +648,12 @@ static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
603static struct clk iva_hsd_byp_clk_mux_ck = { 648static struct clk iva_hsd_byp_clk_mux_ck = {
604 .name = "iva_hsd_byp_clk_mux_ck", 649 .name = "iva_hsd_byp_clk_mux_ck",
605 .parent = &sys_clkin_ck, 650 .parent = &sys_clkin_ck,
651 .clksel = iva_hsd_byp_clk_mux_sel,
652 .init = &omap2_init_clksel_parent,
653 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
654 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
606 .ops = &clkops_null, 655 .ops = &clkops_null,
607 .recalc = &followparent_recalc, 656 .recalc = &omap2_clksel_recalc,
608}; 657};
609 658
610/* DPLL_IVA */ 659/* DPLL_IVA */
@@ -638,15 +687,22 @@ static struct clk dpll_iva_ck = {
638 .set_rate = &omap3_noncore_dpll_set_rate, 687 .set_rate = &omap3_noncore_dpll_set_rate,
639}; 688};
640 689
641static const struct clksel dpll_iva_m4_div[] = { 690static struct clk dpll_iva_x2_ck = {
642 { .parent = &dpll_iva_ck, .rates = div31_1to31_rates }, 691 .name = "dpll_iva_x2_ck",
692 .parent = &dpll_iva_ck,
693 .ops = &clkops_null,
694 .recalc = &omap3_clkoutx2_recalc,
695};
696
697static const struct clksel dpll_iva_m4x2_div[] = {
698 { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
643 { .parent = NULL }, 699 { .parent = NULL },
644}; 700};
645 701
646static struct clk dpll_iva_m4_ck = { 702static struct clk dpll_iva_m4x2_ck = {
647 .name = "dpll_iva_m4_ck", 703 .name = "dpll_iva_m4x2_ck",
648 .parent = &dpll_iva_ck, 704 .parent = &dpll_iva_x2_ck,
649 .clksel = dpll_iva_m4_div, 705 .clksel = dpll_iva_m4x2_div,
650 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, 706 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
651 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, 707 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
652 .ops = &clkops_null, 708 .ops = &clkops_null,
@@ -655,10 +711,10 @@ static struct clk dpll_iva_m4_ck = {
655 .set_rate = &omap2_clksel_set_rate, 711 .set_rate = &omap2_clksel_set_rate,
656}; 712};
657 713
658static struct clk dpll_iva_m5_ck = { 714static struct clk dpll_iva_m5x2_ck = {
659 .name = "dpll_iva_m5_ck", 715 .name = "dpll_iva_m5x2_ck",
660 .parent = &dpll_iva_ck, 716 .parent = &dpll_iva_x2_ck,
661 .clksel = dpll_iva_m4_div, 717 .clksel = dpll_iva_m4x2_div,
662 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, 718 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
663 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, 719 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
664 .ops = &clkops_null, 720 .ops = &clkops_null,
@@ -717,9 +773,10 @@ static struct clk dpll_mpu_m2_ck = {
717 773
718static struct clk per_hs_clk_div_ck = { 774static struct clk per_hs_clk_div_ck = {
719 .name = "per_hs_clk_div_ck", 775 .name = "per_hs_clk_div_ck",
720 .parent = &dpll_abe_m3_ck, 776 .parent = &dpll_abe_m3x2_ck,
721 .ops = &clkops_null, 777 .ops = &clkops_null,
722 .recalc = &followparent_recalc, 778 .fixed_div = 2,
779 .recalc = &omap_fixed_divisor_recalc,
723}; 780};
724 781
725static const struct clksel per_hsd_byp_clk_mux_sel[] = { 782static const struct clksel per_hsd_byp_clk_mux_sel[] = {
@@ -787,29 +844,48 @@ static struct clk dpll_per_m2_ck = {
787 .set_rate = &omap2_clksel_set_rate, 844 .set_rate = &omap2_clksel_set_rate,
788}; 845};
789 846
847static struct clk dpll_per_x2_ck = {
848 .name = "dpll_per_x2_ck",
849 .parent = &dpll_per_ck,
850 .ops = &clkops_null,
851 .recalc = &omap3_clkoutx2_recalc,
852};
853
854static const struct clksel dpll_per_m2x2_div[] = {
855 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
856 { .parent = NULL },
857};
858
790static struct clk dpll_per_m2x2_ck = { 859static struct clk dpll_per_m2x2_ck = {
791 .name = "dpll_per_m2x2_ck", 860 .name = "dpll_per_m2x2_ck",
792 .parent = &dpll_per_ck, 861 .parent = &dpll_per_x2_ck,
862 .clksel = dpll_per_m2x2_div,
863 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
864 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
793 .ops = &clkops_null, 865 .ops = &clkops_null,
794 .recalc = &followparent_recalc, 866 .recalc = &omap2_clksel_recalc,
867 .round_rate = &omap2_clksel_round_rate,
868 .set_rate = &omap2_clksel_set_rate,
795}; 869};
796 870
797static struct clk dpll_per_m3_ck = { 871static struct clk dpll_per_m3x2_ck = {
798 .name = "dpll_per_m3_ck", 872 .name = "dpll_per_m3x2_ck",
799 .parent = &dpll_per_ck, 873 .parent = &dpll_per_x2_ck,
800 .clksel = dpll_per_m2_div, 874 .clksel = dpll_per_m2x2_div,
801 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, 875 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
802 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 876 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
803 .ops = &clkops_null, 877 .ops = &clkops_omap2_dflt,
878 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
879 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
804 .recalc = &omap2_clksel_recalc, 880 .recalc = &omap2_clksel_recalc,
805 .round_rate = &omap2_clksel_round_rate, 881 .round_rate = &omap2_clksel_round_rate,
806 .set_rate = &omap2_clksel_set_rate, 882 .set_rate = &omap2_clksel_set_rate,
807}; 883};
808 884
809static struct clk dpll_per_m4_ck = { 885static struct clk dpll_per_m4x2_ck = {
810 .name = "dpll_per_m4_ck", 886 .name = "dpll_per_m4x2_ck",
811 .parent = &dpll_per_ck, 887 .parent = &dpll_per_x2_ck,
812 .clksel = dpll_per_m2_div, 888 .clksel = dpll_per_m2x2_div,
813 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, 889 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
814 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, 890 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
815 .ops = &clkops_null, 891 .ops = &clkops_null,
@@ -818,10 +894,10 @@ static struct clk dpll_per_m4_ck = {
818 .set_rate = &omap2_clksel_set_rate, 894 .set_rate = &omap2_clksel_set_rate,
819}; 895};
820 896
821static struct clk dpll_per_m5_ck = { 897static struct clk dpll_per_m5x2_ck = {
822 .name = "dpll_per_m5_ck", 898 .name = "dpll_per_m5x2_ck",
823 .parent = &dpll_per_ck, 899 .parent = &dpll_per_x2_ck,
824 .clksel = dpll_per_m2_div, 900 .clksel = dpll_per_m2x2_div,
825 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, 901 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
826 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, 902 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
827 .ops = &clkops_null, 903 .ops = &clkops_null,
@@ -830,10 +906,10 @@ static struct clk dpll_per_m5_ck = {
830 .set_rate = &omap2_clksel_set_rate, 906 .set_rate = &omap2_clksel_set_rate,
831}; 907};
832 908
833static struct clk dpll_per_m6_ck = { 909static struct clk dpll_per_m6x2_ck = {
834 .name = "dpll_per_m6_ck", 910 .name = "dpll_per_m6x2_ck",
835 .parent = &dpll_per_ck, 911 .parent = &dpll_per_x2_ck,
836 .clksel = dpll_per_m2_div, 912 .clksel = dpll_per_m2x2_div,
837 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, 913 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
838 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, 914 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
839 .ops = &clkops_null, 915 .ops = &clkops_null,
@@ -842,10 +918,10 @@ static struct clk dpll_per_m6_ck = {
842 .set_rate = &omap2_clksel_set_rate, 918 .set_rate = &omap2_clksel_set_rate,
843}; 919};
844 920
845static struct clk dpll_per_m7_ck = { 921static struct clk dpll_per_m7x2_ck = {
846 .name = "dpll_per_m7_ck", 922 .name = "dpll_per_m7x2_ck",
847 .parent = &dpll_per_ck, 923 .parent = &dpll_per_x2_ck,
848 .clksel = dpll_per_m2_div, 924 .clksel = dpll_per_m2x2_div,
849 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, 925 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
850 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, 926 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
851 .ops = &clkops_null, 927 .ops = &clkops_null,
@@ -868,6 +944,7 @@ static struct dpll_data dpll_unipro_dd = {
868 .enable_mask = OMAP4430_DPLL_EN_MASK, 944 .enable_mask = OMAP4430_DPLL_EN_MASK,
869 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 945 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
870 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 946 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
947 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
871 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 948 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
872 .max_divider = OMAP4430_MAX_DPLL_DIV, 949 .max_divider = OMAP4430_MAX_DPLL_DIV,
873 .min_divider = 1, 950 .min_divider = 1,
@@ -885,14 +962,21 @@ static struct clk dpll_unipro_ck = {
885 .set_rate = &omap3_noncore_dpll_set_rate, 962 .set_rate = &omap3_noncore_dpll_set_rate,
886}; 963};
887 964
965static struct clk dpll_unipro_x2_ck = {
966 .name = "dpll_unipro_x2_ck",
967 .parent = &dpll_unipro_ck,
968 .ops = &clkops_null,
969 .recalc = &omap3_clkoutx2_recalc,
970};
971
888static const struct clksel dpll_unipro_m2x2_div[] = { 972static const struct clksel dpll_unipro_m2x2_div[] = {
889 { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates }, 973 { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
890 { .parent = NULL }, 974 { .parent = NULL },
891}; 975};
892 976
893static struct clk dpll_unipro_m2x2_ck = { 977static struct clk dpll_unipro_m2x2_ck = {
894 .name = "dpll_unipro_m2x2_ck", 978 .name = "dpll_unipro_m2x2_ck",
895 .parent = &dpll_unipro_ck, 979 .parent = &dpll_unipro_x2_ck,
896 .clksel = dpll_unipro_m2x2_div, 980 .clksel = dpll_unipro_m2x2_div,
897 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, 981 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
898 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 982 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
@@ -904,16 +988,17 @@ static struct clk dpll_unipro_m2x2_ck = {
904 988
905static struct clk usb_hs_clk_div_ck = { 989static struct clk usb_hs_clk_div_ck = {
906 .name = "usb_hs_clk_div_ck", 990 .name = "usb_hs_clk_div_ck",
907 .parent = &dpll_abe_m3_ck, 991 .parent = &dpll_abe_m3x2_ck,
908 .ops = &clkops_null, 992 .ops = &clkops_null,
909 .recalc = &followparent_recalc, 993 .fixed_div = 3,
994 .recalc = &omap_fixed_divisor_recalc,
910}; 995};
911 996
912/* DPLL_USB */ 997/* DPLL_USB */
913static struct dpll_data dpll_usb_dd = { 998static struct dpll_data dpll_usb_dd = {
914 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, 999 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
915 .clk_bypass = &usb_hs_clk_div_ck, 1000 .clk_bypass = &usb_hs_clk_div_ck,
916 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL, 1001 .flags = DPLL_J_TYPE,
917 .clk_ref = &sys_clkin_ck, 1002 .clk_ref = &sys_clkin_ck,
918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, 1003 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 1004 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -967,7 +1052,7 @@ static struct clk dpll_usb_m2_ck = {
967 1052
968static const struct clksel ducati_clk_mux_sel[] = { 1053static const struct clksel ducati_clk_mux_sel[] = {
969 { .parent = &div_core_ck, .rates = div_1_0_rates }, 1054 { .parent = &div_core_ck, .rates = div_1_0_rates },
970 { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates }, 1055 { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
971 { .parent = NULL }, 1056 { .parent = NULL },
972}; 1057};
973 1058
@@ -986,21 +1071,24 @@ static struct clk func_12m_fclk = {
986 .name = "func_12m_fclk", 1071 .name = "func_12m_fclk",
987 .parent = &dpll_per_m2x2_ck, 1072 .parent = &dpll_per_m2x2_ck,
988 .ops = &clkops_null, 1073 .ops = &clkops_null,
989 .recalc = &followparent_recalc, 1074 .fixed_div = 16,
1075 .recalc = &omap_fixed_divisor_recalc,
990}; 1076};
991 1077
992static struct clk func_24m_clk = { 1078static struct clk func_24m_clk = {
993 .name = "func_24m_clk", 1079 .name = "func_24m_clk",
994 .parent = &dpll_per_m2_ck, 1080 .parent = &dpll_per_m2_ck,
995 .ops = &clkops_null, 1081 .ops = &clkops_null,
996 .recalc = &followparent_recalc, 1082 .fixed_div = 4,
1083 .recalc = &omap_fixed_divisor_recalc,
997}; 1084};
998 1085
999static struct clk func_24mc_fclk = { 1086static struct clk func_24mc_fclk = {
1000 .name = "func_24mc_fclk", 1087 .name = "func_24mc_fclk",
1001 .parent = &dpll_per_m2x2_ck, 1088 .parent = &dpll_per_m2x2_ck,
1002 .ops = &clkops_null, 1089 .ops = &clkops_null,
1003 .recalc = &followparent_recalc, 1090 .fixed_div = 8,
1091 .recalc = &omap_fixed_divisor_recalc,
1004}; 1092};
1005 1093
1006static const struct clksel_rate div2_4to8_rates[] = { 1094static const struct clksel_rate div2_4to8_rates[] = {
@@ -1030,7 +1118,8 @@ static struct clk func_48mc_fclk = {
1030 .name = "func_48mc_fclk", 1118 .name = "func_48mc_fclk",
1031 .parent = &dpll_per_m2x2_ck, 1119 .parent = &dpll_per_m2x2_ck,
1032 .ops = &clkops_null, 1120 .ops = &clkops_null,
1033 .recalc = &followparent_recalc, 1121 .fixed_div = 4,
1122 .recalc = &omap_fixed_divisor_recalc,
1034}; 1123};
1035 1124
1036static const struct clksel_rate div2_2to4_rates[] = { 1125static const struct clksel_rate div2_2to4_rates[] = {
@@ -1040,13 +1129,13 @@ static const struct clksel_rate div2_2to4_rates[] = {
1040}; 1129};
1041 1130
1042static const struct clksel func_64m_fclk_div[] = { 1131static const struct clksel func_64m_fclk_div[] = {
1043 { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates }, 1132 { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1044 { .parent = NULL }, 1133 { .parent = NULL },
1045}; 1134};
1046 1135
1047static struct clk func_64m_fclk = { 1136static struct clk func_64m_fclk = {
1048 .name = "func_64m_fclk", 1137 .name = "func_64m_fclk",
1049 .parent = &dpll_per_m4_ck, 1138 .parent = &dpll_per_m4x2_ck,
1050 .clksel = func_64m_fclk_div, 1139 .clksel = func_64m_fclk_div,
1051 .clksel_reg = OMAP4430_CM_SCALE_FCLK, 1140 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1052 .clksel_mask = OMAP4430_SCALE_FCLK_MASK, 1141 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
@@ -1147,7 +1236,8 @@ static struct clk lp_clk_div_ck = {
1147 .name = "lp_clk_div_ck", 1236 .name = "lp_clk_div_ck",
1148 .parent = &dpll_abe_m2x2_ck, 1237 .parent = &dpll_abe_m2x2_ck,
1149 .ops = &clkops_null, 1238 .ops = &clkops_null,
1150 .recalc = &followparent_recalc, 1239 .fixed_div = 16,
1240 .recalc = &omap_fixed_divisor_recalc,
1151}; 1241};
1152 1242
1153static const struct clksel l4_wkup_clk_mux_sel[] = { 1243static const struct clksel l4_wkup_clk_mux_sel[] = {
@@ -1215,12 +1305,13 @@ static struct clk per_abe_24m_fclk = {
1215 .name = "per_abe_24m_fclk", 1305 .name = "per_abe_24m_fclk",
1216 .parent = &dpll_abe_m2_ck, 1306 .parent = &dpll_abe_m2_ck,
1217 .ops = &clkops_null, 1307 .ops = &clkops_null,
1218 .recalc = &followparent_recalc, 1308 .fixed_div = 4,
1309 .recalc = &omap_fixed_divisor_recalc,
1219}; 1310};
1220 1311
1221static const struct clksel pmd_stm_clock_mux_sel[] = { 1312static const struct clksel pmd_stm_clock_mux_sel[] = {
1222 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1313 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1223 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, 1314 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1224 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, 1315 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1225 { .parent = NULL }, 1316 { .parent = NULL },
1226}; 1317};
@@ -1354,7 +1445,7 @@ static struct clk dsp_fck = {
1354 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, 1445 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1355 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1446 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1356 .clkdm_name = "tesla_clkdm", 1447 .clkdm_name = "tesla_clkdm",
1357 .parent = &dpll_iva_m4_ck, 1448 .parent = &dpll_iva_m4x2_ck,
1358 .recalc = &followparent_recalc, 1449 .recalc = &followparent_recalc,
1359}; 1450};
1360 1451
@@ -1384,7 +1475,7 @@ static struct clk dss_dss_clk = {
1384 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1475 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1385 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, 1476 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1386 .clkdm_name = "l3_dss_clkdm", 1477 .clkdm_name = "l3_dss_clkdm",
1387 .parent = &dpll_per_m5_ck, 1478 .parent = &dpll_per_m5x2_ck,
1388 .recalc = &followparent_recalc, 1479 .recalc = &followparent_recalc,
1389}; 1480};
1390 1481
@@ -1441,14 +1532,14 @@ static struct clk emif2_fck = {
1441}; 1532};
1442 1533
1443static const struct clksel fdif_fclk_div[] = { 1534static const struct clksel fdif_fclk_div[] = {
1444 { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates }, 1535 { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1445 { .parent = NULL }, 1536 { .parent = NULL },
1446}; 1537};
1447 1538
1448/* Merged fdif_fclk into fdif */ 1539/* Merged fdif_fclk into fdif */
1449static struct clk fdif_fck = { 1540static struct clk fdif_fck = {
1450 .name = "fdif_fck", 1541 .name = "fdif_fck",
1451 .parent = &dpll_per_m4_ck, 1542 .parent = &dpll_per_m4x2_ck,
1452 .clksel = fdif_fclk_div, 1543 .clksel = fdif_fclk_div,
1453 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, 1544 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1454 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, 1545 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
@@ -1602,15 +1693,15 @@ static struct clk gpmc_ick = {
1602}; 1693};
1603 1694
1604static const struct clksel sgx_clk_mux_sel[] = { 1695static const struct clksel sgx_clk_mux_sel[] = {
1605 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, 1696 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1606 { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates }, 1697 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1607 { .parent = NULL }, 1698 { .parent = NULL },
1608}; 1699};
1609 1700
1610/* Merged sgx_clk_mux into gpu */ 1701/* Merged sgx_clk_mux into gpu */
1611static struct clk gpu_fck = { 1702static struct clk gpu_fck = {
1612 .name = "gpu_fck", 1703 .name = "gpu_fck",
1613 .parent = &dpll_core_m7_ck, 1704 .parent = &dpll_core_m7x2_ck,
1614 .clksel = sgx_clk_mux_sel, 1705 .clksel = sgx_clk_mux_sel,
1615 .init = &omap2_init_clksel_parent, 1706 .init = &omap2_init_clksel_parent,
1616 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, 1707 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
@@ -1729,7 +1820,7 @@ static struct clk iva_fck = {
1729 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, 1820 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1730 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1821 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1731 .clkdm_name = "ivahd_clkdm", 1822 .clkdm_name = "ivahd_clkdm",
1732 .parent = &dpll_iva_m5_ck, 1823 .parent = &dpll_iva_m5x2_ck,
1733 .recalc = &followparent_recalc, 1824 .recalc = &followparent_recalc,
1734}; 1825};
1735 1826
@@ -1749,6 +1840,7 @@ static struct clk l3_instr_ick = {
1749 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 1840 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1750 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1841 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1751 .clkdm_name = "l3_instr_clkdm", 1842 .clkdm_name = "l3_instr_clkdm",
1843 .flags = ENABLE_ON_INIT,
1752 .parent = &l3_div_ck, 1844 .parent = &l3_div_ck,
1753 .recalc = &followparent_recalc, 1845 .recalc = &followparent_recalc,
1754}; 1846};
@@ -1759,6 +1851,7 @@ static struct clk l3_main_3_ick = {
1759 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 1851 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1760 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1852 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1761 .clkdm_name = "l3_instr_clkdm", 1853 .clkdm_name = "l3_instr_clkdm",
1854 .flags = ENABLE_ON_INIT,
1762 .parent = &l3_div_ck, 1855 .parent = &l3_div_ck,
1763 .recalc = &followparent_recalc, 1856 .recalc = &followparent_recalc,
1764}; 1857};
@@ -2063,6 +2156,7 @@ static struct clk ocp_wp_noc_ick = {
2063 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, 2156 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2064 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2157 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2065 .clkdm_name = "l3_instr_clkdm", 2158 .clkdm_name = "l3_instr_clkdm",
2159 .flags = ENABLE_ON_INIT,
2066 .parent = &l3_div_ck, 2160 .parent = &l3_div_ck,
2067 .recalc = &followparent_recalc, 2161 .recalc = &followparent_recalc,
2068}; 2162};
@@ -2093,7 +2187,7 @@ static struct clk sl2if_ick = {
2093 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, 2187 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2094 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2188 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2095 .clkdm_name = "ivahd_clkdm", 2189 .clkdm_name = "ivahd_clkdm",
2096 .parent = &dpll_iva_m5_ck, 2190 .parent = &dpll_iva_m5x2_ck,
2097 .recalc = &followparent_recalc, 2191 .recalc = &followparent_recalc,
2098}; 2192};
2099 2193
@@ -2438,36 +2532,6 @@ static struct clk usb_host_fs_fck = {
2438 .recalc = &followparent_recalc, 2532 .recalc = &followparent_recalc,
2439}; 2533};
2440 2534
2441static struct clk usb_host_hs_utmi_p3_clk = {
2442 .name = "usb_host_hs_utmi_p3_clk",
2443 .ops = &clkops_omap2_dflt,
2444 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2445 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2446 .clkdm_name = "l3_init_clkdm",
2447 .parent = &init_60m_fclk,
2448 .recalc = &followparent_recalc,
2449};
2450
2451static struct clk usb_host_hs_hsic60m_p1_clk = {
2452 .name = "usb_host_hs_hsic60m_p1_clk",
2453 .ops = &clkops_omap2_dflt,
2454 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2455 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2456 .clkdm_name = "l3_init_clkdm",
2457 .parent = &init_60m_fclk,
2458 .recalc = &followparent_recalc,
2459};
2460
2461static struct clk usb_host_hs_hsic60m_p2_clk = {
2462 .name = "usb_host_hs_hsic60m_p2_clk",
2463 .ops = &clkops_omap2_dflt,
2464 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2465 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2466 .clkdm_name = "l3_init_clkdm",
2467 .parent = &init_60m_fclk,
2468 .recalc = &followparent_recalc,
2469};
2470
2471static const struct clksel utmi_p1_gfclk_sel[] = { 2535static const struct clksel utmi_p1_gfclk_sel[] = {
2472 { .parent = &init_60m_fclk, .rates = div_1_0_rates }, 2536 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2473 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, 2537 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
@@ -2522,6 +2586,16 @@ static struct clk usb_host_hs_utmi_p2_clk = {
2522 .recalc = &followparent_recalc, 2586 .recalc = &followparent_recalc,
2523}; 2587};
2524 2588
2589static struct clk usb_host_hs_utmi_p3_clk = {
2590 .name = "usb_host_hs_utmi_p3_clk",
2591 .ops = &clkops_omap2_dflt,
2592 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2593 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2594 .clkdm_name = "l3_init_clkdm",
2595 .parent = &init_60m_fclk,
2596 .recalc = &followparent_recalc,
2597};
2598
2525static struct clk usb_host_hs_hsic480m_p1_clk = { 2599static struct clk usb_host_hs_hsic480m_p1_clk = {
2526 .name = "usb_host_hs_hsic480m_p1_clk", 2600 .name = "usb_host_hs_hsic480m_p1_clk",
2527 .ops = &clkops_omap2_dflt, 2601 .ops = &clkops_omap2_dflt,
@@ -2532,6 +2606,26 @@ static struct clk usb_host_hs_hsic480m_p1_clk = {
2532 .recalc = &followparent_recalc, 2606 .recalc = &followparent_recalc,
2533}; 2607};
2534 2608
2609static struct clk usb_host_hs_hsic60m_p1_clk = {
2610 .name = "usb_host_hs_hsic60m_p1_clk",
2611 .ops = &clkops_omap2_dflt,
2612 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2613 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2614 .clkdm_name = "l3_init_clkdm",
2615 .parent = &init_60m_fclk,
2616 .recalc = &followparent_recalc,
2617};
2618
2619static struct clk usb_host_hs_hsic60m_p2_clk = {
2620 .name = "usb_host_hs_hsic60m_p2_clk",
2621 .ops = &clkops_omap2_dflt,
2622 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2623 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2624 .clkdm_name = "l3_init_clkdm",
2625 .parent = &init_60m_fclk,
2626 .recalc = &followparent_recalc,
2627};
2628
2535static struct clk usb_host_hs_hsic480m_p2_clk = { 2629static struct clk usb_host_hs_hsic480m_p2_clk = {
2536 .name = "usb_host_hs_hsic480m_p2_clk", 2630 .name = "usb_host_hs_hsic480m_p2_clk",
2537 .ops = &clkops_omap2_dflt, 2631 .ops = &clkops_omap2_dflt,
@@ -2656,13 +2750,13 @@ static const struct clksel_rate div2_14to18_rates[] = {
2656}; 2750};
2657 2751
2658static const struct clksel usim_fclk_div[] = { 2752static const struct clksel usim_fclk_div[] = {
2659 { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates }, 2753 { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2660 { .parent = NULL }, 2754 { .parent = NULL },
2661}; 2755};
2662 2756
2663static struct clk usim_ck = { 2757static struct clk usim_ck = {
2664 .name = "usim_ck", 2758 .name = "usim_ck",
2665 .parent = &dpll_per_m4_ck, 2759 .parent = &dpll_per_m4x2_ck,
2666 .clksel = usim_fclk_div, 2760 .clksel = usim_fclk_div,
2667 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2761 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2668 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, 2762 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
@@ -2747,6 +2841,168 @@ static struct clk trace_clk_div_ck = {
2747 .set_rate = &omap2_clksel_set_rate, 2841 .set_rate = &omap2_clksel_set_rate,
2748}; 2842};
2749 2843
2844/* SCRM aux clk nodes */
2845
2846static const struct clksel auxclk_sel[] = {
2847 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2848 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2849 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2850 { .parent = NULL },
2851};
2852
2853static struct clk auxclk0_ck = {
2854 .name = "auxclk0_ck",
2855 .parent = &sys_clkin_ck,
2856 .init = &omap2_init_clksel_parent,
2857 .ops = &clkops_omap2_dflt,
2858 .clksel = auxclk_sel,
2859 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2860 .clksel_mask = OMAP4_SRCSELECT_MASK,
2861 .recalc = &omap2_clksel_recalc,
2862 .enable_reg = OMAP4_SCRM_AUXCLK0,
2863 .enable_bit = OMAP4_ENABLE_SHIFT,
2864};
2865
2866static struct clk auxclk1_ck = {
2867 .name = "auxclk1_ck",
2868 .parent = &sys_clkin_ck,
2869 .init = &omap2_init_clksel_parent,
2870 .ops = &clkops_omap2_dflt,
2871 .clksel = auxclk_sel,
2872 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2873 .clksel_mask = OMAP4_SRCSELECT_MASK,
2874 .recalc = &omap2_clksel_recalc,
2875 .enable_reg = OMAP4_SCRM_AUXCLK1,
2876 .enable_bit = OMAP4_ENABLE_SHIFT,
2877};
2878
2879static struct clk auxclk2_ck = {
2880 .name = "auxclk2_ck",
2881 .parent = &sys_clkin_ck,
2882 .init = &omap2_init_clksel_parent,
2883 .ops = &clkops_omap2_dflt,
2884 .clksel = auxclk_sel,
2885 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2886 .clksel_mask = OMAP4_SRCSELECT_MASK,
2887 .recalc = &omap2_clksel_recalc,
2888 .enable_reg = OMAP4_SCRM_AUXCLK2,
2889 .enable_bit = OMAP4_ENABLE_SHIFT,
2890};
2891static struct clk auxclk3_ck = {
2892 .name = "auxclk3_ck",
2893 .parent = &sys_clkin_ck,
2894 .init = &omap2_init_clksel_parent,
2895 .ops = &clkops_omap2_dflt,
2896 .clksel = auxclk_sel,
2897 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2898 .clksel_mask = OMAP4_SRCSELECT_MASK,
2899 .recalc = &omap2_clksel_recalc,
2900 .enable_reg = OMAP4_SCRM_AUXCLK3,
2901 .enable_bit = OMAP4_ENABLE_SHIFT,
2902};
2903
2904static struct clk auxclk4_ck = {
2905 .name = "auxclk4_ck",
2906 .parent = &sys_clkin_ck,
2907 .init = &omap2_init_clksel_parent,
2908 .ops = &clkops_omap2_dflt,
2909 .clksel = auxclk_sel,
2910 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2911 .clksel_mask = OMAP4_SRCSELECT_MASK,
2912 .recalc = &omap2_clksel_recalc,
2913 .enable_reg = OMAP4_SCRM_AUXCLK4,
2914 .enable_bit = OMAP4_ENABLE_SHIFT,
2915};
2916
2917static struct clk auxclk5_ck = {
2918 .name = "auxclk5_ck",
2919 .parent = &sys_clkin_ck,
2920 .init = &omap2_init_clksel_parent,
2921 .ops = &clkops_omap2_dflt,
2922 .clksel = auxclk_sel,
2923 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2924 .clksel_mask = OMAP4_SRCSELECT_MASK,
2925 .recalc = &omap2_clksel_recalc,
2926 .enable_reg = OMAP4_SCRM_AUXCLK5,
2927 .enable_bit = OMAP4_ENABLE_SHIFT,
2928};
2929
2930static const struct clksel auxclkreq_sel[] = {
2931 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2932 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2933 { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2934 { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2935 { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2936 { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2937 { .parent = NULL },
2938};
2939
2940static struct clk auxclkreq0_ck = {
2941 .name = "auxclkreq0_ck",
2942 .parent = &auxclk0_ck,
2943 .init = &omap2_init_clksel_parent,
2944 .ops = &clkops_null,
2945 .clksel = auxclkreq_sel,
2946 .clksel_reg = OMAP4_SCRM_AUXCLKREQ0,
2947 .clksel_mask = OMAP4_MAPPING_MASK,
2948 .recalc = &omap2_clksel_recalc,
2949};
2950
2951static struct clk auxclkreq1_ck = {
2952 .name = "auxclkreq1_ck",
2953 .parent = &auxclk1_ck,
2954 .init = &omap2_init_clksel_parent,
2955 .ops = &clkops_null,
2956 .clksel = auxclkreq_sel,
2957 .clksel_reg = OMAP4_SCRM_AUXCLKREQ1,
2958 .clksel_mask = OMAP4_MAPPING_MASK,
2959 .recalc = &omap2_clksel_recalc,
2960};
2961
2962static struct clk auxclkreq2_ck = {
2963 .name = "auxclkreq2_ck",
2964 .parent = &auxclk2_ck,
2965 .init = &omap2_init_clksel_parent,
2966 .ops = &clkops_null,
2967 .clksel = auxclkreq_sel,
2968 .clksel_reg = OMAP4_SCRM_AUXCLKREQ2,
2969 .clksel_mask = OMAP4_MAPPING_MASK,
2970 .recalc = &omap2_clksel_recalc,
2971};
2972
2973static struct clk auxclkreq3_ck = {
2974 .name = "auxclkreq3_ck",
2975 .parent = &auxclk3_ck,
2976 .init = &omap2_init_clksel_parent,
2977 .ops = &clkops_null,
2978 .clksel = auxclkreq_sel,
2979 .clksel_reg = OMAP4_SCRM_AUXCLKREQ3,
2980 .clksel_mask = OMAP4_MAPPING_MASK,
2981 .recalc = &omap2_clksel_recalc,
2982};
2983
2984static struct clk auxclkreq4_ck = {
2985 .name = "auxclkreq4_ck",
2986 .parent = &auxclk4_ck,
2987 .init = &omap2_init_clksel_parent,
2988 .ops = &clkops_null,
2989 .clksel = auxclkreq_sel,
2990 .clksel_reg = OMAP4_SCRM_AUXCLKREQ4,
2991 .clksel_mask = OMAP4_MAPPING_MASK,
2992 .recalc = &omap2_clksel_recalc,
2993};
2994
2995static struct clk auxclkreq5_ck = {
2996 .name = "auxclkreq5_ck",
2997 .parent = &auxclk5_ck,
2998 .init = &omap2_init_clksel_parent,
2999 .ops = &clkops_null,
3000 .clksel = auxclkreq_sel,
3001 .clksel_reg = OMAP4_SCRM_AUXCLKREQ5,
3002 .clksel_mask = OMAP4_MAPPING_MASK,
3003 .recalc = &omap2_clksel_recalc,
3004};
3005
2750/* 3006/*
2751 * clkdev 3007 * clkdev
2752 */ 3008 */
@@ -2774,43 +3030,48 @@ static struct omap_clk omap44xx_clks[] = {
2774 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), 3030 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
2775 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), 3031 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
2776 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), 3032 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
3033 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
2777 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), 3034 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
2778 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), 3035 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
2779 CLK(NULL, "abe_clk", &abe_clk, CK_443X), 3036 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
2780 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), 3037 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
2781 CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X), 3038 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
2782 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), 3039 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
2783 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), 3040 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
2784 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X), 3041 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
3042 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
2785 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), 3043 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
2786 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), 3044 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
2787 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), 3045 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
2788 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X), 3046 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
2789 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), 3047 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
2790 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), 3048 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
2791 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), 3049 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
2792 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X), 3050 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
2793 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), 3051 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
2794 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), 3052 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
2795 CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X), 3053 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
2796 CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X), 3054 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
2797 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), 3055 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
2798 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), 3056 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
2799 CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X), 3057 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
2800 CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X), 3058 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
3059 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
2801 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), 3060 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
2802 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), 3061 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
2803 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), 3062 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
2804 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), 3063 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
2805 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), 3064 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
2806 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), 3065 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
3066 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
2807 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), 3067 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
2808 CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X), 3068 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
2809 CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X), 3069 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
2810 CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X), 3070 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
2811 CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X), 3071 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
2812 CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X), 3072 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
2813 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), 3073 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
3074 CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
2814 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), 3075 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
2815 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), 3076 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
2816 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), 3077 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
@@ -2856,17 +3117,17 @@ static struct omap_clk omap44xx_clks[] = {
2856 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), 3117 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
2857 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 3118 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
2858 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), 3119 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
2859 CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), 3120 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
2860 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), 3121 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
2861 CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), 3122 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
2862 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), 3123 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
2863 CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), 3124 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
2864 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), 3125 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
2865 CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), 3126 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
2866 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), 3127 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
2867 CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), 3128 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
2868 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), 3129 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
2869 CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), 3130 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
2870 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 3131 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2871 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), 3132 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
2872 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), 3133 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
@@ -2937,14 +3198,14 @@ static struct omap_clk omap44xx_clks[] = {
2937 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 3198 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2938 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 3199 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
2939 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 3200 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
2940 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
2941 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
2942 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
2943 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 3201 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
2944 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), 3202 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
2945 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), 3203 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
2946 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), 3204 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
3205 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
2947 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), 3206 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
3207 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
3208 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
2948 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), 3209 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
2949 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), 3210 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
2950 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), 3211 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
@@ -2960,6 +3221,7 @@ static struct omap_clk omap44xx_clks[] = {
2960 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 3221 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2961 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 3222 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2962 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), 3223 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
3224 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
2963 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), 3225 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
2964 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 3226 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2965 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 3227 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
@@ -2997,6 +3259,18 @@ static struct omap_clk omap44xx_clks[] = {
2997 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 3259 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
2998 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), 3260 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
2999 CLK("omap_wdt", "ick", &dummy_ck, CK_443X), 3261 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3262 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3263 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3264 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3265 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3266 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3267 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3268 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3269 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3270 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3271 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3272 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3273 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3000}; 3274};
3001 3275
3002int __init omap4xxx_clk_init(void) 3276int __init omap4xxx_clk_init(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 08:10:42 -0500