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-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c1312
1 files changed, 811 insertions, 501 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index e10db7a90cb2..1599836ba3d9 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -17,13 +17,15 @@
17 * This program is free software; you can redistribute it and/or modify 17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as 18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation. 19 * published by the Free Software Foundation.
20 *
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
23 * in.
20 */ 24 */
21 25
22#include <linux/kernel.h> 26#include <linux/kernel.h>
23#include <linux/list.h> 27#include <linux/list.h>
24#include <linux/clk.h> 28#include <linux/clk.h>
25
26#include <plat/control.h>
27#include <plat/clkdev_omap.h> 29#include <plat/clkdev_omap.h>
28 30
29#include "clock.h" 31#include "clock.h"
@@ -32,6 +34,7 @@
32#include "cm-regbits-44xx.h" 34#include "cm-regbits-44xx.h"
33#include "prm.h" 35#include "prm.h"
34#include "prm-regbits-44xx.h" 36#include "prm-regbits-44xx.h"
37#include "control.h"
35 38
36/* Root clocks */ 39/* Root clocks */
37 40
@@ -175,21 +178,27 @@ static struct clk sys_clkin_ck = {
175 .recalc = &omap2_clksel_recalc, 178 .recalc = &omap2_clksel_recalc,
176}; 179};
177 180
181static struct clk tie_low_clock_ck = {
182 .name = "tie_low_clock_ck",
183 .rate = 0,
184 .ops = &clkops_null,
185};
186
178static struct clk utmi_phy_clkout_ck = { 187static struct clk utmi_phy_clkout_ck = {
179 .name = "utmi_phy_clkout_ck", 188 .name = "utmi_phy_clkout_ck",
180 .rate = 12000000, 189 .rate = 60000000,
181 .ops = &clkops_null, 190 .ops = &clkops_null,
182}; 191};
183 192
184static struct clk xclk60mhsp1_ck = { 193static struct clk xclk60mhsp1_ck = {
185 .name = "xclk60mhsp1_ck", 194 .name = "xclk60mhsp1_ck",
186 .rate = 12000000, 195 .rate = 60000000,
187 .ops = &clkops_null, 196 .ops = &clkops_null,
188}; 197};
189 198
190static struct clk xclk60mhsp2_ck = { 199static struct clk xclk60mhsp2_ck = {
191 .name = "xclk60mhsp2_ck", 200 .name = "xclk60mhsp2_ck",
192 .rate = 12000000, 201 .rate = 60000000,
193 .ops = &clkops_null, 202 .ops = &clkops_null,
194}; 203};
195 204
@@ -201,39 +210,23 @@ static struct clk xclk60motg_ck = {
201 210
202/* Module clocks and DPLL outputs */ 211/* Module clocks and DPLL outputs */
203 212
204static const struct clksel_rate div2_1to2_rates[] = { 213static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
205 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 214 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
206 { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 215 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
207 { .div = 0 },
208};
209
210static const struct clksel dpll_sys_ref_clk_div[] = {
211 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
212 { .parent = NULL }, 216 { .parent = NULL },
213}; 217};
214 218
215static struct clk dpll_sys_ref_clk = { 219static struct clk abe_dpll_bypass_clk_mux_ck = {
216 .name = "dpll_sys_ref_clk", 220 .name = "abe_dpll_bypass_clk_mux_ck",
217 .parent = &sys_clkin_ck, 221 .parent = &sys_clkin_ck,
218 .clksel = dpll_sys_ref_clk_div,
219 .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
220 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
221 .ops = &clkops_null, 222 .ops = &clkops_null,
222 .recalc = &omap2_clksel_recalc, 223 .recalc = &followparent_recalc,
223 .round_rate = &omap2_clksel_round_rate,
224 .set_rate = &omap2_clksel_set_rate,
225};
226
227static const struct clksel abe_dpll_refclk_mux_sel[] = {
228 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
229 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
230 { .parent = NULL },
231}; 224};
232 225
233static struct clk abe_dpll_refclk_mux_ck = { 226static struct clk abe_dpll_refclk_mux_ck = {
234 .name = "abe_dpll_refclk_mux_ck", 227 .name = "abe_dpll_refclk_mux_ck",
235 .parent = &dpll_sys_ref_clk, 228 .parent = &sys_clkin_ck,
236 .clksel = abe_dpll_refclk_mux_sel, 229 .clksel = abe_dpll_bypass_clk_mux_sel,
237 .init = &omap2_init_clksel_parent, 230 .init = &omap2_init_clksel_parent,
238 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, 231 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
239 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, 232 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
@@ -244,7 +237,7 @@ static struct clk abe_dpll_refclk_mux_ck = {
244/* DPLL_ABE */ 237/* DPLL_ABE */
245static struct dpll_data dpll_abe_dd = { 238static struct dpll_data dpll_abe_dd = {
246 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, 239 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
247 .clk_bypass = &sys_clkin_ck, 240 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
248 .clk_ref = &abe_dpll_refclk_mux_ck, 241 .clk_ref = &abe_dpll_refclk_mux_ck,
249 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, 242 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
250 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 243 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -310,6 +303,12 @@ static struct clk abe_clk = {
310 .set_rate = &omap2_clksel_set_rate, 303 .set_rate = &omap2_clksel_set_rate,
311}; 304};
312 305
306static const struct clksel_rate div2_1to2_rates[] = {
307 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
308 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
309 { .div = 0 },
310};
311
313static const struct clksel aess_fclk_div[] = { 312static const struct clksel aess_fclk_div[] = {
314 { .parent = &abe_clk, .rates = div2_1to2_rates }, 313 { .parent = &abe_clk, .rates = div2_1to2_rates },
315 { .parent = NULL }, 314 { .parent = NULL },
@@ -380,14 +379,14 @@ static struct clk dpll_abe_m3_ck = {
380}; 379};
381 380
382static const struct clksel core_hsd_byp_clk_mux_sel[] = { 381static const struct clksel core_hsd_byp_clk_mux_sel[] = {
383 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, 382 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
384 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, 383 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
385 { .parent = NULL }, 384 { .parent = NULL },
386}; 385};
387 386
388static struct clk core_hsd_byp_clk_mux_ck = { 387static struct clk core_hsd_byp_clk_mux_ck = {
389 .name = "core_hsd_byp_clk_mux_ck", 388 .name = "core_hsd_byp_clk_mux_ck",
390 .parent = &dpll_sys_ref_clk, 389 .parent = &sys_clkin_ck,
391 .clksel = core_hsd_byp_clk_mux_sel, 390 .clksel = core_hsd_byp_clk_mux_sel,
392 .init = &omap2_init_clksel_parent, 391 .init = &omap2_init_clksel_parent,
393 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, 392 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
@@ -400,7 +399,7 @@ static struct clk core_hsd_byp_clk_mux_ck = {
400static struct dpll_data dpll_core_dd = { 399static struct dpll_data dpll_core_dd = {
401 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, 400 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
402 .clk_bypass = &core_hsd_byp_clk_mux_ck, 401 .clk_bypass = &core_hsd_byp_clk_mux_ck,
403 .clk_ref = &dpll_sys_ref_clk, 402 .clk_ref = &sys_clkin_ck,
404 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, 403 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
405 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 404 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
406 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, 405 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
@@ -418,7 +417,7 @@ static struct dpll_data dpll_core_dd = {
418 417
419static struct clk dpll_core_ck = { 418static struct clk dpll_core_ck = {
420 .name = "dpll_core_ck", 419 .name = "dpll_core_ck",
421 .parent = &dpll_sys_ref_clk, 420 .parent = &sys_clkin_ck,
422 .dpll_data = &dpll_core_dd, 421 .dpll_data = &dpll_core_dd,
423 .init = &omap2_init_dpll_parent, 422 .init = &omap2_init_dpll_parent,
424 .ops = &clkops_null, 423 .ops = &clkops_null,
@@ -596,14 +595,14 @@ static struct clk dpll_core_m7_ck = {
596}; 595};
597 596
598static const struct clksel iva_hsd_byp_clk_mux_sel[] = { 597static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
599 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, 598 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
600 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, 599 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
601 { .parent = NULL }, 600 { .parent = NULL },
602}; 601};
603 602
604static struct clk iva_hsd_byp_clk_mux_ck = { 603static struct clk iva_hsd_byp_clk_mux_ck = {
605 .name = "iva_hsd_byp_clk_mux_ck", 604 .name = "iva_hsd_byp_clk_mux_ck",
606 .parent = &dpll_sys_ref_clk, 605 .parent = &sys_clkin_ck,
607 .ops = &clkops_null, 606 .ops = &clkops_null,
608 .recalc = &followparent_recalc, 607 .recalc = &followparent_recalc,
609}; 608};
@@ -612,7 +611,7 @@ static struct clk iva_hsd_byp_clk_mux_ck = {
612static struct dpll_data dpll_iva_dd = { 611static struct dpll_data dpll_iva_dd = {
613 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, 612 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
614 .clk_bypass = &iva_hsd_byp_clk_mux_ck, 613 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
615 .clk_ref = &dpll_sys_ref_clk, 614 .clk_ref = &sys_clkin_ck,
616 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, 615 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
617 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 616 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
618 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, 617 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
@@ -630,7 +629,7 @@ static struct dpll_data dpll_iva_dd = {
630 629
631static struct clk dpll_iva_ck = { 630static struct clk dpll_iva_ck = {
632 .name = "dpll_iva_ck", 631 .name = "dpll_iva_ck",
633 .parent = &dpll_sys_ref_clk, 632 .parent = &sys_clkin_ck,
634 .dpll_data = &dpll_iva_dd, 633 .dpll_data = &dpll_iva_dd,
635 .init = &omap2_init_dpll_parent, 634 .init = &omap2_init_dpll_parent,
636 .ops = &clkops_omap3_noncore_dpll_ops, 635 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -672,7 +671,7 @@ static struct clk dpll_iva_m5_ck = {
672static struct dpll_data dpll_mpu_dd = { 671static struct dpll_data dpll_mpu_dd = {
673 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, 672 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
674 .clk_bypass = &div_mpu_hs_clk, 673 .clk_bypass = &div_mpu_hs_clk,
675 .clk_ref = &dpll_sys_ref_clk, 674 .clk_ref = &sys_clkin_ck,
676 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, 675 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
677 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 676 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
678 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, 677 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
@@ -690,7 +689,7 @@ static struct dpll_data dpll_mpu_dd = {
690 689
691static struct clk dpll_mpu_ck = { 690static struct clk dpll_mpu_ck = {
692 .name = "dpll_mpu_ck", 691 .name = "dpll_mpu_ck",
693 .parent = &dpll_sys_ref_clk, 692 .parent = &sys_clkin_ck,
694 .dpll_data = &dpll_mpu_dd, 693 .dpll_data = &dpll_mpu_dd,
695 .init = &omap2_init_dpll_parent, 694 .init = &omap2_init_dpll_parent,
696 .ops = &clkops_omap3_noncore_dpll_ops, 695 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -724,14 +723,14 @@ static struct clk per_hs_clk_div_ck = {
724}; 723};
725 724
726static const struct clksel per_hsd_byp_clk_mux_sel[] = { 725static const struct clksel per_hsd_byp_clk_mux_sel[] = {
727 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, 726 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
728 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, 727 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
729 { .parent = NULL }, 728 { .parent = NULL },
730}; 729};
731 730
732static struct clk per_hsd_byp_clk_mux_ck = { 731static struct clk per_hsd_byp_clk_mux_ck = {
733 .name = "per_hsd_byp_clk_mux_ck", 732 .name = "per_hsd_byp_clk_mux_ck",
734 .parent = &dpll_sys_ref_clk, 733 .parent = &sys_clkin_ck,
735 .clksel = per_hsd_byp_clk_mux_sel, 734 .clksel = per_hsd_byp_clk_mux_sel,
736 .init = &omap2_init_clksel_parent, 735 .init = &omap2_init_clksel_parent,
737 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, 736 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
@@ -744,7 +743,7 @@ static struct clk per_hsd_byp_clk_mux_ck = {
744static struct dpll_data dpll_per_dd = { 743static struct dpll_data dpll_per_dd = {
745 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, 744 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
746 .clk_bypass = &per_hsd_byp_clk_mux_ck, 745 .clk_bypass = &per_hsd_byp_clk_mux_ck,
747 .clk_ref = &dpll_sys_ref_clk, 746 .clk_ref = &sys_clkin_ck,
748 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, 747 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
749 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 748 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
750 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, 749 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
@@ -762,7 +761,7 @@ static struct dpll_data dpll_per_dd = {
762 761
763static struct clk dpll_per_ck = { 762static struct clk dpll_per_ck = {
764 .name = "dpll_per_ck", 763 .name = "dpll_per_ck",
765 .parent = &dpll_sys_ref_clk, 764 .parent = &sys_clkin_ck,
766 .dpll_data = &dpll_per_dd, 765 .dpll_data = &dpll_per_dd,
767 .init = &omap2_init_dpll_parent, 766 .init = &omap2_init_dpll_parent,
768 .ops = &clkops_omap3_noncore_dpll_ops, 767 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -858,8 +857,8 @@ static struct clk dpll_per_m7_ck = {
858/* DPLL_UNIPRO */ 857/* DPLL_UNIPRO */
859static struct dpll_data dpll_unipro_dd = { 858static struct dpll_data dpll_unipro_dd = {
860 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, 859 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
861 .clk_bypass = &dpll_sys_ref_clk, 860 .clk_bypass = &sys_clkin_ck,
862 .clk_ref = &dpll_sys_ref_clk, 861 .clk_ref = &sys_clkin_ck,
863 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, 862 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
864 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 863 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
865 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, 864 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
@@ -877,7 +876,7 @@ static struct dpll_data dpll_unipro_dd = {
877 876
878static struct clk dpll_unipro_ck = { 877static struct clk dpll_unipro_ck = {
879 .name = "dpll_unipro_ck", 878 .name = "dpll_unipro_ck",
880 .parent = &dpll_sys_ref_clk, 879 .parent = &sys_clkin_ck,
881 .dpll_data = &dpll_unipro_dd, 880 .dpll_data = &dpll_unipro_dd,
882 .init = &omap2_init_dpll_parent, 881 .init = &omap2_init_dpll_parent,
883 .ops = &clkops_omap3_noncore_dpll_ops, 882 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -914,7 +913,8 @@ static struct clk usb_hs_clk_div_ck = {
914static struct dpll_data dpll_usb_dd = { 913static struct dpll_data dpll_usb_dd = {
915 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, 914 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
916 .clk_bypass = &usb_hs_clk_div_ck, 915 .clk_bypass = &usb_hs_clk_div_ck,
917 .clk_ref = &dpll_sys_ref_clk, 916 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
917 .clk_ref = &sys_clkin_ck,
918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, 918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
920 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, 920 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
@@ -927,13 +927,12 @@ static struct dpll_data dpll_usb_dd = {
927 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 927 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
928 .max_divider = OMAP4430_MAX_DPLL_DIV, 928 .max_divider = OMAP4430_MAX_DPLL_DIV,
929 .min_divider = 1, 929 .min_divider = 1,
930 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
931}; 930};
932 931
933 932
934static struct clk dpll_usb_ck = { 933static struct clk dpll_usb_ck = {
935 .name = "dpll_usb_ck", 934 .name = "dpll_usb_ck",
936 .parent = &dpll_sys_ref_clk, 935 .parent = &sys_clkin_ck,
937 .dpll_data = &dpll_usb_dd, 936 .dpll_data = &dpll_usb_dd,
938 .init = &omap2_init_dpll_parent, 937 .init = &omap2_init_dpll_parent,
939 .ops = &clkops_omap3_noncore_dpll_ops, 938 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -1222,7 +1221,7 @@ static struct clk per_abe_24m_fclk = {
1222static const struct clksel pmd_stm_clock_mux_sel[] = { 1221static const struct clksel pmd_stm_clock_mux_sel[] = {
1223 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1222 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1224 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, 1223 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
1225 { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates }, 1224 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1226 { .parent = NULL }, 1225 { .parent = NULL },
1227}; 1226};
1228 1227
@@ -1240,10 +1239,15 @@ static struct clk pmd_trace_clk_mux_ck = {
1240 .recalc = &followparent_recalc, 1239 .recalc = &followparent_recalc,
1241}; 1240};
1242 1241
1242static const struct clksel syc_clk_div_div[] = {
1243 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1244 { .parent = NULL },
1245};
1246
1243static struct clk syc_clk_div_ck = { 1247static struct clk syc_clk_div_ck = {
1244 .name = "syc_clk_div_ck", 1248 .name = "syc_clk_div_ck",
1245 .parent = &sys_clkin_ck, 1249 .parent = &sys_clkin_ck,
1246 .clksel = dpll_sys_ref_clk_div, 1250 .clksel = syc_clk_div_div,
1247 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, 1251 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1248 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, 1252 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1249 .ops = &clkops_null, 1253 .ops = &clkops_null,
@@ -1284,13 +1288,13 @@ static struct clk aess_fck = {
1284 .recalc = &followparent_recalc, 1288 .recalc = &followparent_recalc,
1285}; 1289};
1286 1290
1287static struct clk cust_efuse_fck = { 1291static struct clk bandgap_fclk = {
1288 .name = "cust_efuse_fck", 1292 .name = "bandgap_fclk",
1289 .ops = &clkops_omap2_dflt, 1293 .ops = &clkops_omap2_dflt,
1290 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, 1294 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1295 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1292 .clkdm_name = "l4_cefuse_clkdm", 1296 .clkdm_name = "l4_wkup_clkdm",
1293 .parent = &sys_clkin_ck, 1297 .parent = &sys_32k_ck,
1294 .recalc = &followparent_recalc, 1298 .recalc = &followparent_recalc,
1295}; 1299};
1296 1300
@@ -1344,6 +1348,56 @@ static struct clk dmic_fck = {
1344 .clkdm_name = "abe_clkdm", 1348 .clkdm_name = "abe_clkdm",
1345}; 1349};
1346 1350
1351static struct clk dsp_fck = {
1352 .name = "dsp_fck",
1353 .ops = &clkops_omap2_dflt,
1354 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1355 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1356 .clkdm_name = "tesla_clkdm",
1357 .parent = &dpll_iva_m4_ck,
1358 .recalc = &followparent_recalc,
1359};
1360
1361static struct clk dss_sys_clk = {
1362 .name = "dss_sys_clk",
1363 .ops = &clkops_omap2_dflt,
1364 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1365 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1366 .clkdm_name = "l3_dss_clkdm",
1367 .parent = &syc_clk_div_ck,
1368 .recalc = &followparent_recalc,
1369};
1370
1371static struct clk dss_tv_clk = {
1372 .name = "dss_tv_clk",
1373 .ops = &clkops_omap2_dflt,
1374 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1375 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1376 .clkdm_name = "l3_dss_clkdm",
1377 .parent = &extalt_clkin_ck,
1378 .recalc = &followparent_recalc,
1379};
1380
1381static struct clk dss_dss_clk = {
1382 .name = "dss_dss_clk",
1383 .ops = &clkops_omap2_dflt,
1384 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1385 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1386 .clkdm_name = "l3_dss_clkdm",
1387 .parent = &dpll_per_m5_ck,
1388 .recalc = &followparent_recalc,
1389};
1390
1391static struct clk dss_48mhz_clk = {
1392 .name = "dss_48mhz_clk",
1393 .ops = &clkops_omap2_dflt,
1394 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1395 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1396 .clkdm_name = "l3_dss_clkdm",
1397 .parent = &func_48mc_fclk,
1398 .recalc = &followparent_recalc,
1399};
1400
1347static struct clk dss_fck = { 1401static struct clk dss_fck = {
1348 .name = "dss_fck", 1402 .name = "dss_fck",
1349 .ops = &clkops_omap2_dflt, 1403 .ops = &clkops_omap2_dflt,
@@ -1354,18 +1408,18 @@ static struct clk dss_fck = {
1354 .recalc = &followparent_recalc, 1408 .recalc = &followparent_recalc,
1355}; 1409};
1356 1410
1357static struct clk ducati_ick = { 1411static struct clk efuse_ctrl_cust_fck = {
1358 .name = "ducati_ick", 1412 .name = "efuse_ctrl_cust_fck",
1359 .ops = &clkops_omap2_dflt, 1413 .ops = &clkops_omap2_dflt,
1360 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, 1414 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1361 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1415 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1362 .clkdm_name = "ducati_clkdm", 1416 .clkdm_name = "l4_cefuse_clkdm",
1363 .parent = &ducati_clk_mux_ck, 1417 .parent = &sys_clkin_ck,
1364 .recalc = &followparent_recalc, 1418 .recalc = &followparent_recalc,
1365}; 1419};
1366 1420
1367static struct clk emif1_ick = { 1421static struct clk emif1_fck = {
1368 .name = "emif1_ick", 1422 .name = "emif1_fck",
1369 .ops = &clkops_omap2_dflt, 1423 .ops = &clkops_omap2_dflt,
1370 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, 1424 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1371 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1425 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1375,8 +1429,8 @@ static struct clk emif1_ick = {
1375 .recalc = &followparent_recalc, 1429 .recalc = &followparent_recalc,
1376}; 1430};
1377 1431
1378static struct clk emif2_ick = { 1432static struct clk emif2_fck = {
1379 .name = "emif2_ick", 1433 .name = "emif2_fck",
1380 .ops = &clkops_omap2_dflt, 1434 .ops = &clkops_omap2_dflt,
1381 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, 1435 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1382 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1436 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1407,42 +1461,24 @@ static struct clk fdif_fck = {
1407 .clkdm_name = "iss_clkdm", 1461 .clkdm_name = "iss_clkdm",
1408}; 1462};
1409 1463
1410static const struct clksel per_sgx_fclk_div[] = { 1464static struct clk fpka_fck = {
1411 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, 1465 .name = "fpka_fck",
1412 { .parent = NULL }, 1466 .ops = &clkops_omap2_dflt,
1413}; 1467 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1414 1468 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1415static struct clk per_sgx_fclk = { 1469 .clkdm_name = "l4_secure_clkdm",
1416 .name = "per_sgx_fclk", 1470 .parent = &l4_div_ck,
1417 .parent = &dpll_per_m2x2_ck, 1471 .recalc = &followparent_recalc,
1418 .clksel = per_sgx_fclk_div,
1419 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1420 .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK,
1421 .ops = &clkops_null,
1422 .recalc = &omap2_clksel_recalc,
1423 .round_rate = &omap2_clksel_round_rate,
1424 .set_rate = &omap2_clksel_set_rate,
1425};
1426
1427static const struct clksel sgx_clk_mux_sel[] = {
1428 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1429 { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
1430 { .parent = NULL },
1431}; 1472};
1432 1473
1433/* Merged sgx_clk_mux into gfx */ 1474static struct clk gpio1_dbclk = {
1434static struct clk gfx_fck = { 1475 .name = "gpio1_dbclk",
1435 .name = "gfx_fck",
1436 .parent = &dpll_core_m7_ck,
1437 .clksel = sgx_clk_mux_sel,
1438 .init = &omap2_init_clksel_parent,
1439 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1440 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1441 .ops = &clkops_omap2_dflt, 1476 .ops = &clkops_omap2_dflt,
1442 .recalc = &omap2_clksel_recalc, 1477 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1443 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, 1478 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1444 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1479 .clkdm_name = "l4_wkup_clkdm",
1445 .clkdm_name = "l3_gfx_clkdm", 1480 .parent = &sys_32k_ck,
1481 .recalc = &followparent_recalc,
1446}; 1482};
1447 1483
1448static struct clk gpio1_ick = { 1484static struct clk gpio1_ick = {
@@ -1455,6 +1491,16 @@ static struct clk gpio1_ick = {
1455 .recalc = &followparent_recalc, 1491 .recalc = &followparent_recalc,
1456}; 1492};
1457 1493
1494static struct clk gpio2_dbclk = {
1495 .name = "gpio2_dbclk",
1496 .ops = &clkops_omap2_dflt,
1497 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1498 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1499 .clkdm_name = "l4_per_clkdm",
1500 .parent = &sys_32k_ck,
1501 .recalc = &followparent_recalc,
1502};
1503
1458static struct clk gpio2_ick = { 1504static struct clk gpio2_ick = {
1459 .name = "gpio2_ick", 1505 .name = "gpio2_ick",
1460 .ops = &clkops_omap2_dflt, 1506 .ops = &clkops_omap2_dflt,
@@ -1465,6 +1511,16 @@ static struct clk gpio2_ick = {
1465 .recalc = &followparent_recalc, 1511 .recalc = &followparent_recalc,
1466}; 1512};
1467 1513
1514static struct clk gpio3_dbclk = {
1515 .name = "gpio3_dbclk",
1516 .ops = &clkops_omap2_dflt,
1517 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1518 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1519 .clkdm_name = "l4_per_clkdm",
1520 .parent = &sys_32k_ck,
1521 .recalc = &followparent_recalc,
1522};
1523
1468static struct clk gpio3_ick = { 1524static struct clk gpio3_ick = {
1469 .name = "gpio3_ick", 1525 .name = "gpio3_ick",
1470 .ops = &clkops_omap2_dflt, 1526 .ops = &clkops_omap2_dflt,
@@ -1475,6 +1531,16 @@ static struct clk gpio3_ick = {
1475 .recalc = &followparent_recalc, 1531 .recalc = &followparent_recalc,
1476}; 1532};
1477 1533
1534static struct clk gpio4_dbclk = {
1535 .name = "gpio4_dbclk",
1536 .ops = &clkops_omap2_dflt,
1537 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1538 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1539 .clkdm_name = "l4_per_clkdm",
1540 .parent = &sys_32k_ck,
1541 .recalc = &followparent_recalc,
1542};
1543
1478static struct clk gpio4_ick = { 1544static struct clk gpio4_ick = {
1479 .name = "gpio4_ick", 1545 .name = "gpio4_ick",
1480 .ops = &clkops_omap2_dflt, 1546 .ops = &clkops_omap2_dflt,
@@ -1485,6 +1551,16 @@ static struct clk gpio4_ick = {
1485 .recalc = &followparent_recalc, 1551 .recalc = &followparent_recalc,
1486}; 1552};
1487 1553
1554static struct clk gpio5_dbclk = {
1555 .name = "gpio5_dbclk",
1556 .ops = &clkops_omap2_dflt,
1557 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1558 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1559 .clkdm_name = "l4_per_clkdm",
1560 .parent = &sys_32k_ck,
1561 .recalc = &followparent_recalc,
1562};
1563
1488static struct clk gpio5_ick = { 1564static struct clk gpio5_ick = {
1489 .name = "gpio5_ick", 1565 .name = "gpio5_ick",
1490 .ops = &clkops_omap2_dflt, 1566 .ops = &clkops_omap2_dflt,
@@ -1495,6 +1571,16 @@ static struct clk gpio5_ick = {
1495 .recalc = &followparent_recalc, 1571 .recalc = &followparent_recalc,
1496}; 1572};
1497 1573
1574static struct clk gpio6_dbclk = {
1575 .name = "gpio6_dbclk",
1576 .ops = &clkops_omap2_dflt,
1577 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1578 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1579 .clkdm_name = "l4_per_clkdm",
1580 .parent = &sys_32k_ck,
1581 .recalc = &followparent_recalc,
1582};
1583
1498static struct clk gpio6_ick = { 1584static struct clk gpio6_ick = {
1499 .name = "gpio6_ick", 1585 .name = "gpio6_ick",
1500 .ops = &clkops_omap2_dflt, 1586 .ops = &clkops_omap2_dflt,
@@ -1515,214 +1601,25 @@ static struct clk gpmc_ick = {
1515 .recalc = &followparent_recalc, 1601 .recalc = &followparent_recalc,
1516}; 1602};
1517 1603
1518static const struct clksel dmt1_clk_mux_sel[] = { 1604static const struct clksel sgx_clk_mux_sel[] = {
1519 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1605 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1520 { .parent = &sys_32k_ck, .rates = div_1_1_rates }, 1606 { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
1521 { .parent = NULL },
1522};
1523
1524/*
1525 * Merged dmt1_clk_mux into gptimer1
1526 * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
1527 */
1528static struct clk gpt1_fck = {
1529 .name = "gpt1_fck",
1530 .parent = &sys_clkin_ck,
1531 .clksel = dmt1_clk_mux_sel,
1532 .init = &omap2_init_clksel_parent,
1533 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1534 .clksel_mask = OMAP4430_CLKSEL_MASK,
1535 .ops = &clkops_omap2_dflt,
1536 .recalc = &omap2_clksel_recalc,
1537 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1538 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1539 .clkdm_name = "l4_wkup_clkdm",
1540};
1541
1542/*
1543 * Merged cm2_dm10_mux into gptimer10
1544 * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
1545 */
1546static struct clk gpt10_fck = {
1547 .name = "gpt10_fck",
1548 .parent = &sys_clkin_ck,
1549 .clksel = dmt1_clk_mux_sel,
1550 .init = &omap2_init_clksel_parent,
1551 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1552 .clksel_mask = OMAP4430_CLKSEL_MASK,
1553 .ops = &clkops_omap2_dflt,
1554 .recalc = &omap2_clksel_recalc,
1555 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1556 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1557 .clkdm_name = "l4_per_clkdm",
1558};
1559
1560/*
1561 * Merged cm2_dm11_mux into gptimer11
1562 * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
1563 */
1564static struct clk gpt11_fck = {
1565 .name = "gpt11_fck",
1566 .parent = &sys_clkin_ck,
1567 .clksel = dmt1_clk_mux_sel,
1568 .init = &omap2_init_clksel_parent,
1569 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1570 .clksel_mask = OMAP4430_CLKSEL_MASK,
1571 .ops = &clkops_omap2_dflt,
1572 .recalc = &omap2_clksel_recalc,
1573 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1574 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1575 .clkdm_name = "l4_per_clkdm",
1576};
1577
1578/*
1579 * Merged cm2_dm2_mux into gptimer2
1580 * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
1581 */
1582static struct clk gpt2_fck = {
1583 .name = "gpt2_fck",
1584 .parent = &sys_clkin_ck,
1585 .clksel = dmt1_clk_mux_sel,
1586 .init = &omap2_init_clksel_parent,
1587 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1588 .clksel_mask = OMAP4430_CLKSEL_MASK,
1589 .ops = &clkops_omap2_dflt,
1590 .recalc = &omap2_clksel_recalc,
1591 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1592 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1593 .clkdm_name = "l4_per_clkdm",
1594};
1595
1596/*
1597 * Merged cm2_dm3_mux into gptimer3
1598 * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
1599 */
1600static struct clk gpt3_fck = {
1601 .name = "gpt3_fck",
1602 .parent = &sys_clkin_ck,
1603 .clksel = dmt1_clk_mux_sel,
1604 .init = &omap2_init_clksel_parent,
1605 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1606 .clksel_mask = OMAP4430_CLKSEL_MASK,
1607 .ops = &clkops_omap2_dflt,
1608 .recalc = &omap2_clksel_recalc,
1609 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1610 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1611 .clkdm_name = "l4_per_clkdm",
1612};
1613
1614/*
1615 * Merged cm2_dm4_mux into gptimer4
1616 * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
1617 */
1618static struct clk gpt4_fck = {
1619 .name = "gpt4_fck",
1620 .parent = &sys_clkin_ck,
1621 .clksel = dmt1_clk_mux_sel,
1622 .init = &omap2_init_clksel_parent,
1623 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1624 .clksel_mask = OMAP4430_CLKSEL_MASK,
1625 .ops = &clkops_omap2_dflt,
1626 .recalc = &omap2_clksel_recalc,
1627 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1628 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1629 .clkdm_name = "l4_per_clkdm",
1630};
1631
1632static const struct clksel timer5_sync_mux_sel[] = {
1633 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1634 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1635 { .parent = NULL }, 1607 { .parent = NULL },
1636}; 1608};
1637 1609
1638/* 1610/* Merged sgx_clk_mux into gpu */
1639 * Merged timer5_sync_mux into gptimer5 1611static struct clk gpu_fck = {
1640 * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention 1612 .name = "gpu_fck",
1641 */ 1613 .parent = &dpll_core_m7_ck,
1642static struct clk gpt5_fck = { 1614 .clksel = sgx_clk_mux_sel,
1643 .name = "gpt5_fck",
1644 .parent = &syc_clk_div_ck,
1645 .clksel = timer5_sync_mux_sel,
1646 .init = &omap2_init_clksel_parent,
1647 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1648 .clksel_mask = OMAP4430_CLKSEL_MASK,
1649 .ops = &clkops_omap2_dflt,
1650 .recalc = &omap2_clksel_recalc,
1651 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1652 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1653 .clkdm_name = "abe_clkdm",
1654};
1655
1656/*
1657 * Merged timer6_sync_mux into gptimer6
1658 * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
1659 */
1660static struct clk gpt6_fck = {
1661 .name = "gpt6_fck",
1662 .parent = &syc_clk_div_ck,
1663 .clksel = timer5_sync_mux_sel,
1664 .init = &omap2_init_clksel_parent,
1665 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1666 .clksel_mask = OMAP4430_CLKSEL_MASK,
1667 .ops = &clkops_omap2_dflt,
1668 .recalc = &omap2_clksel_recalc,
1669 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1670 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1671 .clkdm_name = "abe_clkdm",
1672};
1673
1674/*
1675 * Merged timer7_sync_mux into gptimer7
1676 * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
1677 */
1678static struct clk gpt7_fck = {
1679 .name = "gpt7_fck",
1680 .parent = &syc_clk_div_ck,
1681 .clksel = timer5_sync_mux_sel,
1682 .init = &omap2_init_clksel_parent,
1683 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1684 .clksel_mask = OMAP4430_CLKSEL_MASK,
1685 .ops = &clkops_omap2_dflt,
1686 .recalc = &omap2_clksel_recalc,
1687 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1688 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1689 .clkdm_name = "abe_clkdm",
1690};
1691
1692/*
1693 * Merged timer8_sync_mux into gptimer8
1694 * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
1695 */
1696static struct clk gpt8_fck = {
1697 .name = "gpt8_fck",
1698 .parent = &syc_clk_div_ck,
1699 .clksel = timer5_sync_mux_sel,
1700 .init = &omap2_init_clksel_parent,
1701 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1702 .clksel_mask = OMAP4430_CLKSEL_MASK,
1703 .ops = &clkops_omap2_dflt,
1704 .recalc = &omap2_clksel_recalc,
1705 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1706 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1707 .clkdm_name = "abe_clkdm",
1708};
1709
1710/*
1711 * Merged cm2_dm9_mux into gptimer9
1712 * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
1713 */
1714static struct clk gpt9_fck = {
1715 .name = "gpt9_fck",
1716 .parent = &sys_clkin_ck,
1717 .clksel = dmt1_clk_mux_sel,
1718 .init = &omap2_init_clksel_parent, 1615 .init = &omap2_init_clksel_parent,
1719 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 1616 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1720 .clksel_mask = OMAP4430_CLKSEL_MASK, 1617 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1721 .ops = &clkops_omap2_dflt, 1618 .ops = &clkops_omap2_dflt,
1722 .recalc = &omap2_clksel_recalc, 1619 .recalc = &omap2_clksel_recalc,
1723 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 1620 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1724 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1621 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1725 .clkdm_name = "l4_per_clkdm", 1622 .clkdm_name = "l3_gfx_clkdm",
1726}; 1623};
1727 1624
1728static struct clk hdq1w_fck = { 1625static struct clk hdq1w_fck = {
@@ -1735,11 +1632,16 @@ static struct clk hdq1w_fck = {
1735 .recalc = &followparent_recalc, 1632 .recalc = &followparent_recalc,
1736}; 1633};
1737 1634
1635static const struct clksel hsi_fclk_div[] = {
1636 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1637 { .parent = NULL },
1638};
1639
1738/* Merged hsi_fclk into hsi */ 1640/* Merged hsi_fclk into hsi */
1739static struct clk hsi_ick = { 1641static struct clk hsi_fck = {
1740 .name = "hsi_ick", 1642 .name = "hsi_fck",
1741 .parent = &dpll_per_m2x2_ck, 1643 .parent = &dpll_per_m2x2_ck,
1742 .clksel = per_sgx_fclk_div, 1644 .clksel = hsi_fclk_div,
1743 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 1645 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1744 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, 1646 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1745 .ops = &clkops_omap2_dflt, 1647 .ops = &clkops_omap2_dflt,
@@ -1791,6 +1693,26 @@ static struct clk i2c4_fck = {
1791 .recalc = &followparent_recalc, 1693 .recalc = &followparent_recalc,
1792}; 1694};
1793 1695
1696static struct clk ipu_fck = {
1697 .name = "ipu_fck",
1698 .ops = &clkops_omap2_dflt,
1699 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1700 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1701 .clkdm_name = "ducati_clkdm",
1702 .parent = &ducati_clk_mux_ck,
1703 .recalc = &followparent_recalc,
1704};
1705
1706static struct clk iss_ctrlclk = {
1707 .name = "iss_ctrlclk",
1708 .ops = &clkops_omap2_dflt,
1709 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1710 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1711 .clkdm_name = "iss_clkdm",
1712 .parent = &func_96m_fclk,
1713 .recalc = &followparent_recalc,
1714};
1715
1794static struct clk iss_fck = { 1716static struct clk iss_fck = {
1795 .name = "iss_fck", 1717 .name = "iss_fck",
1796 .ops = &clkops_omap2_dflt, 1718 .ops = &clkops_omap2_dflt,
@@ -1801,8 +1723,8 @@ static struct clk iss_fck = {
1801 .recalc = &followparent_recalc, 1723 .recalc = &followparent_recalc,
1802}; 1724};
1803 1725
1804static struct clk ivahd_ick = { 1726static struct clk iva_fck = {
1805 .name = "ivahd_ick", 1727 .name = "iva_fck",
1806 .ops = &clkops_omap2_dflt, 1728 .ops = &clkops_omap2_dflt,
1807 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, 1729 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1808 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1730 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1811,8 +1733,8 @@ static struct clk ivahd_ick = {
1811 .recalc = &followparent_recalc, 1733 .recalc = &followparent_recalc,
1812}; 1734};
1813 1735
1814static struct clk keyboard_fck = { 1736static struct clk kbd_fck = {
1815 .name = "keyboard_fck", 1737 .name = "kbd_fck",
1816 .ops = &clkops_omap2_dflt, 1738 .ops = &clkops_omap2_dflt,
1817 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, 1739 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1818 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1740 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1821,8 +1743,8 @@ static struct clk keyboard_fck = {
1821 .recalc = &followparent_recalc, 1743 .recalc = &followparent_recalc,
1822}; 1744};
1823 1745
1824static struct clk l3_instr_interconnect_ick = { 1746static struct clk l3_instr_ick = {
1825 .name = "l3_instr_interconnect_ick", 1747 .name = "l3_instr_ick",
1826 .ops = &clkops_omap2_dflt, 1748 .ops = &clkops_omap2_dflt,
1827 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 1749 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1828 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1750 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1831,8 +1753,8 @@ static struct clk l3_instr_interconnect_ick = {
1831 .recalc = &followparent_recalc, 1753 .recalc = &followparent_recalc,
1832}; 1754};
1833 1755
1834static struct clk l3_interconnect_3_ick = { 1756static struct clk l3_main_3_ick = {
1835 .name = "l3_interconnect_3_ick", 1757 .name = "l3_main_3_ick",
1836 .ops = &clkops_omap2_dflt, 1758 .ops = &clkops_omap2_dflt,
1837 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 1759 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1838 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1760 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2005,6 +1927,16 @@ static struct clk mcbsp4_fck = {
2005 .clkdm_name = "l4_per_clkdm", 1927 .clkdm_name = "l4_per_clkdm",
2006}; 1928};
2007 1929
1930static struct clk mcpdm_fck = {
1931 .name = "mcpdm_fck",
1932 .ops = &clkops_omap2_dflt,
1933 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1934 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1935 .clkdm_name = "abe_clkdm",
1936 .parent = &pad_clks_ck,
1937 .recalc = &followparent_recalc,
1938};
1939
2008static struct clk mcspi1_fck = { 1940static struct clk mcspi1_fck = {
2009 .name = "mcspi1_fck", 1941 .name = "mcspi1_fck",
2010 .ops = &clkops_omap2_dflt, 1942 .ops = &clkops_omap2_dflt,
@@ -2105,33 +2037,33 @@ static struct clk mmc5_fck = {
2105 .recalc = &followparent_recalc, 2037 .recalc = &followparent_recalc,
2106}; 2038};
2107 2039
2108static struct clk ocp_wp1_ick = { 2040static struct clk ocp2scp_usb_phy_phy_48m = {
2109 .name = "ocp_wp1_ick", 2041 .name = "ocp2scp_usb_phy_phy_48m",
2110 .ops = &clkops_omap2_dflt, 2042 .ops = &clkops_omap2_dflt,
2111 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, 2043 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2112 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2044 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2113 .clkdm_name = "l3_instr_clkdm", 2045 .clkdm_name = "l3_init_clkdm",
2114 .parent = &l3_div_ck, 2046 .parent = &func_48m_fclk,
2115 .recalc = &followparent_recalc, 2047 .recalc = &followparent_recalc,
2116}; 2048};
2117 2049
2118static struct clk pdm_fck = { 2050static struct clk ocp2scp_usb_phy_ick = {
2119 .name = "pdm_fck", 2051 .name = "ocp2scp_usb_phy_ick",
2120 .ops = &clkops_omap2_dflt, 2052 .ops = &clkops_omap2_dflt,
2121 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, 2053 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2122 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2054 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2123 .clkdm_name = "abe_clkdm", 2055 .clkdm_name = "l3_init_clkdm",
2124 .parent = &pad_clks_ck, 2056 .parent = &l4_div_ck,
2125 .recalc = &followparent_recalc, 2057 .recalc = &followparent_recalc,
2126}; 2058};
2127 2059
2128static struct clk pkaeip29_fck = { 2060static struct clk ocp_wp_noc_ick = {
2129 .name = "pkaeip29_fck", 2061 .name = "ocp_wp_noc_ick",
2130 .ops = &clkops_omap2_dflt, 2062 .ops = &clkops_omap2_dflt,
2131 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, 2063 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2132 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2064 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2133 .clkdm_name = "l4_secure_clkdm", 2065 .clkdm_name = "l3_instr_clkdm",
2134 .parent = &l4_div_ck, 2066 .parent = &l3_div_ck,
2135 .recalc = &followparent_recalc, 2067 .recalc = &followparent_recalc,
2136}; 2068};
2137 2069
@@ -2145,8 +2077,8 @@ static struct clk rng_ick = {
2145 .recalc = &followparent_recalc, 2077 .recalc = &followparent_recalc,
2146}; 2078};
2147 2079
2148static struct clk sha2md51_fck = { 2080static struct clk sha2md5_fck = {
2149 .name = "sha2md51_fck", 2081 .name = "sha2md5_fck",
2150 .ops = &clkops_omap2_dflt, 2082 .ops = &clkops_omap2_dflt,
2151 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 2083 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2152 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2084 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2155,8 +2087,8 @@ static struct clk sha2md51_fck = {
2155 .recalc = &followparent_recalc, 2087 .recalc = &followparent_recalc,
2156}; 2088};
2157 2089
2158static struct clk sl2_ick = { 2090static struct clk sl2if_ick = {
2159 .name = "sl2_ick", 2091 .name = "sl2if_ick",
2160 .ops = &clkops_omap2_dflt, 2092 .ops = &clkops_omap2_dflt,
2161 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, 2093 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2162 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2094 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2165,6 +2097,46 @@ static struct clk sl2_ick = {
2165 .recalc = &followparent_recalc, 2097 .recalc = &followparent_recalc,
2166}; 2098};
2167 2099
2100static struct clk slimbus1_fclk_1 = {
2101 .name = "slimbus1_fclk_1",
2102 .ops = &clkops_omap2_dflt,
2103 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2104 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2105 .clkdm_name = "abe_clkdm",
2106 .parent = &func_24m_clk,
2107 .recalc = &followparent_recalc,
2108};
2109
2110static struct clk slimbus1_fclk_0 = {
2111 .name = "slimbus1_fclk_0",
2112 .ops = &clkops_omap2_dflt,
2113 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2114 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2115 .clkdm_name = "abe_clkdm",
2116 .parent = &abe_24m_fclk,
2117 .recalc = &followparent_recalc,
2118};
2119
2120static struct clk slimbus1_fclk_2 = {
2121 .name = "slimbus1_fclk_2",
2122 .ops = &clkops_omap2_dflt,
2123 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2124 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2125 .clkdm_name = "abe_clkdm",
2126 .parent = &pad_clks_ck,
2127 .recalc = &followparent_recalc,
2128};
2129
2130static struct clk slimbus1_slimbus_clk = {
2131 .name = "slimbus1_slimbus_clk",
2132 .ops = &clkops_omap2_dflt,
2133 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2134 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2135 .clkdm_name = "abe_clkdm",
2136 .parent = &slimbus_clk,
2137 .recalc = &followparent_recalc,
2138};
2139
2168static struct clk slimbus1_fck = { 2140static struct clk slimbus1_fck = {
2169 .name = "slimbus1_fck", 2141 .name = "slimbus1_fck",
2170 .ops = &clkops_omap2_dflt, 2142 .ops = &clkops_omap2_dflt,
@@ -2175,6 +2147,36 @@ static struct clk slimbus1_fck = {
2175 .recalc = &followparent_recalc, 2147 .recalc = &followparent_recalc,
2176}; 2148};
2177 2149
2150static struct clk slimbus2_fclk_1 = {
2151 .name = "slimbus2_fclk_1",
2152 .ops = &clkops_omap2_dflt,
2153 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2154 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2155 .clkdm_name = "l4_per_clkdm",
2156 .parent = &per_abe_24m_fclk,
2157 .recalc = &followparent_recalc,
2158};
2159
2160static struct clk slimbus2_fclk_0 = {
2161 .name = "slimbus2_fclk_0",
2162 .ops = &clkops_omap2_dflt,
2163 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2164 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2165 .clkdm_name = "l4_per_clkdm",
2166 .parent = &func_24mc_fclk,
2167 .recalc = &followparent_recalc,
2168};
2169
2170static struct clk slimbus2_slimbus_clk = {
2171 .name = "slimbus2_slimbus_clk",
2172 .ops = &clkops_omap2_dflt,
2173 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2174 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2175 .clkdm_name = "l4_per_clkdm",
2176 .parent = &pad_slimbus_core_clks_ck,
2177 .recalc = &followparent_recalc,
2178};
2179
2178static struct clk slimbus2_fck = { 2180static struct clk slimbus2_fck = {
2179 .name = "slimbus2_fck", 2181 .name = "slimbus2_fck",
2180 .ops = &clkops_omap2_dflt, 2182 .ops = &clkops_omap2_dflt,
@@ -2185,8 +2187,8 @@ static struct clk slimbus2_fck = {
2185 .recalc = &followparent_recalc, 2187 .recalc = &followparent_recalc,
2186}; 2188};
2187 2189
2188static struct clk sr_core_fck = { 2190static struct clk smartreflex_core_fck = {
2189 .name = "sr_core_fck", 2191 .name = "smartreflex_core_fck",
2190 .ops = &clkops_omap2_dflt, 2192 .ops = &clkops_omap2_dflt,
2191 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 2193 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2192 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2194 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2195,8 +2197,8 @@ static struct clk sr_core_fck = {
2195 .recalc = &followparent_recalc, 2197 .recalc = &followparent_recalc,
2196}; 2198};
2197 2199
2198static struct clk sr_iva_fck = { 2200static struct clk smartreflex_iva_fck = {
2199 .name = "sr_iva_fck", 2201 .name = "smartreflex_iva_fck",
2200 .ops = &clkops_omap2_dflt, 2202 .ops = &clkops_omap2_dflt,
2201 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, 2203 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2202 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2204 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2205,8 +2207,8 @@ static struct clk sr_iva_fck = {
2205 .recalc = &followparent_recalc, 2207 .recalc = &followparent_recalc,
2206}; 2208};
2207 2209
2208static struct clk sr_mpu_fck = { 2210static struct clk smartreflex_mpu_fck = {
2209 .name = "sr_mpu_fck", 2211 .name = "smartreflex_mpu_fck",
2210 .ops = &clkops_omap2_dflt, 2212 .ops = &clkops_omap2_dflt,
2211 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, 2213 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2212 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2214 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2215,14 +2217,175 @@ static struct clk sr_mpu_fck = {
2215 .recalc = &followparent_recalc, 2217 .recalc = &followparent_recalc,
2216}; 2218};
2217 2219
2218static struct clk tesla_ick = { 2220/* Merged dmt1_clk_mux into timer1 */
2219 .name = "tesla_ick", 2221static struct clk timer1_fck = {
2222 .name = "timer1_fck",
2223 .parent = &sys_clkin_ck,
2224 .clksel = abe_dpll_bypass_clk_mux_sel,
2225 .init = &omap2_init_clksel_parent,
2226 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2227 .clksel_mask = OMAP4430_CLKSEL_MASK,
2220 .ops = &clkops_omap2_dflt, 2228 .ops = &clkops_omap2_dflt,
2221 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, 2229 .recalc = &omap2_clksel_recalc,
2222 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2230 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2223 .clkdm_name = "tesla_clkdm", 2231 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2224 .parent = &dpll_iva_m4_ck, 2232 .clkdm_name = "l4_wkup_clkdm",
2225 .recalc = &followparent_recalc, 2233};
2234
2235/* Merged cm2_dm10_mux into timer10 */
2236static struct clk timer10_fck = {
2237 .name = "timer10_fck",
2238 .parent = &sys_clkin_ck,
2239 .clksel = abe_dpll_bypass_clk_mux_sel,
2240 .init = &omap2_init_clksel_parent,
2241 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2242 .clksel_mask = OMAP4430_CLKSEL_MASK,
2243 .ops = &clkops_omap2_dflt,
2244 .recalc = &omap2_clksel_recalc,
2245 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2246 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2247 .clkdm_name = "l4_per_clkdm",
2248};
2249
2250/* Merged cm2_dm11_mux into timer11 */
2251static struct clk timer11_fck = {
2252 .name = "timer11_fck",
2253 .parent = &sys_clkin_ck,
2254 .clksel = abe_dpll_bypass_clk_mux_sel,
2255 .init = &omap2_init_clksel_parent,
2256 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2257 .clksel_mask = OMAP4430_CLKSEL_MASK,
2258 .ops = &clkops_omap2_dflt,
2259 .recalc = &omap2_clksel_recalc,
2260 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2261 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2262 .clkdm_name = "l4_per_clkdm",
2263};
2264
2265/* Merged cm2_dm2_mux into timer2 */
2266static struct clk timer2_fck = {
2267 .name = "timer2_fck",
2268 .parent = &sys_clkin_ck,
2269 .clksel = abe_dpll_bypass_clk_mux_sel,
2270 .init = &omap2_init_clksel_parent,
2271 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2272 .clksel_mask = OMAP4430_CLKSEL_MASK,
2273 .ops = &clkops_omap2_dflt,
2274 .recalc = &omap2_clksel_recalc,
2275 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2276 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2277 .clkdm_name = "l4_per_clkdm",
2278};
2279
2280/* Merged cm2_dm3_mux into timer3 */
2281static struct clk timer3_fck = {
2282 .name = "timer3_fck",
2283 .parent = &sys_clkin_ck,
2284 .clksel = abe_dpll_bypass_clk_mux_sel,
2285 .init = &omap2_init_clksel_parent,
2286 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2287 .clksel_mask = OMAP4430_CLKSEL_MASK,
2288 .ops = &clkops_omap2_dflt,
2289 .recalc = &omap2_clksel_recalc,
2290 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2292 .clkdm_name = "l4_per_clkdm",
2293};
2294
2295/* Merged cm2_dm4_mux into timer4 */
2296static struct clk timer4_fck = {
2297 .name = "timer4_fck",
2298 .parent = &sys_clkin_ck,
2299 .clksel = abe_dpll_bypass_clk_mux_sel,
2300 .init = &omap2_init_clksel_parent,
2301 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2302 .clksel_mask = OMAP4430_CLKSEL_MASK,
2303 .ops = &clkops_omap2_dflt,
2304 .recalc = &omap2_clksel_recalc,
2305 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2306 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2307 .clkdm_name = "l4_per_clkdm",
2308};
2309
2310static const struct clksel timer5_sync_mux_sel[] = {
2311 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2312 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2313 { .parent = NULL },
2314};
2315
2316/* Merged timer5_sync_mux into timer5 */
2317static struct clk timer5_fck = {
2318 .name = "timer5_fck",
2319 .parent = &syc_clk_div_ck,
2320 .clksel = timer5_sync_mux_sel,
2321 .init = &omap2_init_clksel_parent,
2322 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2323 .clksel_mask = OMAP4430_CLKSEL_MASK,
2324 .ops = &clkops_omap2_dflt,
2325 .recalc = &omap2_clksel_recalc,
2326 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2327 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2328 .clkdm_name = "abe_clkdm",
2329};
2330
2331/* Merged timer6_sync_mux into timer6 */
2332static struct clk timer6_fck = {
2333 .name = "timer6_fck",
2334 .parent = &syc_clk_div_ck,
2335 .clksel = timer5_sync_mux_sel,
2336 .init = &omap2_init_clksel_parent,
2337 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2338 .clksel_mask = OMAP4430_CLKSEL_MASK,
2339 .ops = &clkops_omap2_dflt,
2340 .recalc = &omap2_clksel_recalc,
2341 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2342 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2343 .clkdm_name = "abe_clkdm",
2344};
2345
2346/* Merged timer7_sync_mux into timer7 */
2347static struct clk timer7_fck = {
2348 .name = "timer7_fck",
2349 .parent = &syc_clk_div_ck,
2350 .clksel = timer5_sync_mux_sel,
2351 .init = &omap2_init_clksel_parent,
2352 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2353 .clksel_mask = OMAP4430_CLKSEL_MASK,
2354 .ops = &clkops_omap2_dflt,
2355 .recalc = &omap2_clksel_recalc,
2356 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2357 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2358 .clkdm_name = "abe_clkdm",
2359};
2360
2361/* Merged timer8_sync_mux into timer8 */
2362static struct clk timer8_fck = {
2363 .name = "timer8_fck",
2364 .parent = &syc_clk_div_ck,
2365 .clksel = timer5_sync_mux_sel,
2366 .init = &omap2_init_clksel_parent,
2367 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2368 .clksel_mask = OMAP4430_CLKSEL_MASK,
2369 .ops = &clkops_omap2_dflt,
2370 .recalc = &omap2_clksel_recalc,
2371 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2372 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2373 .clkdm_name = "abe_clkdm",
2374};
2375
2376/* Merged cm2_dm9_mux into timer9 */
2377static struct clk timer9_fck = {
2378 .name = "timer9_fck",
2379 .parent = &sys_clkin_ck,
2380 .clksel = abe_dpll_bypass_clk_mux_sel,
2381 .init = &omap2_init_clksel_parent,
2382 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2383 .clksel_mask = OMAP4430_CLKSEL_MASK,
2384 .ops = &clkops_omap2_dflt,
2385 .recalc = &omap2_clksel_recalc,
2386 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2387 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2388 .clkdm_name = "l4_per_clkdm",
2226}; 2389};
2227 2390
2228static struct clk uart1_fck = { 2391static struct clk uart1_fck = {
@@ -2265,105 +2428,148 @@ static struct clk uart4_fck = {
2265 .recalc = &followparent_recalc, 2428 .recalc = &followparent_recalc,
2266}; 2429};
2267 2430
2268static struct clk unipro1_fck = { 2431static struct clk usb_host_fs_fck = {
2269 .name = "unipro1_fck", 2432 .name = "usb_host_fs_fck",
2270 .ops = &clkops_omap2_dflt, 2433 .ops = &clkops_omap2_dflt,
2271 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, 2434 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2272 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2435 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2273 .clkdm_name = "l3_init_clkdm", 2436 .clkdm_name = "l3_init_clkdm",
2274 .parent = &func_96m_fclk, 2437 .parent = &func_48mc_fclk,
2275 .recalc = &followparent_recalc, 2438 .recalc = &followparent_recalc,
2276}; 2439};
2277 2440
2278static struct clk usb_host_fck = { 2441static struct clk usb_host_hs_utmi_p3_clk = {
2279 .name = "usb_host_fck", 2442 .name = "usb_host_hs_utmi_p3_clk",
2280 .ops = &clkops_omap2_dflt, 2443 .ops = &clkops_omap2_dflt,
2281 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2444 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2282 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2445 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2283 .clkdm_name = "l3_init_clkdm", 2446 .clkdm_name = "l3_init_clkdm",
2284 .parent = &init_60m_fclk, 2447 .parent = &init_60m_fclk,
2285 .recalc = &followparent_recalc, 2448 .recalc = &followparent_recalc,
2286}; 2449};
2287 2450
2288static struct clk usb_host_fs_fck = { 2451static struct clk usb_host_hs_hsic60m_p1_clk = {
2289 .name = "usb_host_fs_fck", 2452 .name = "usb_host_hs_hsic60m_p1_clk",
2290 .ops = &clkops_omap2_dflt, 2453 .ops = &clkops_omap2_dflt,
2291 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, 2454 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2292 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2455 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2293 .clkdm_name = "l3_init_clkdm", 2456 .clkdm_name = "l3_init_clkdm",
2294 .parent = &func_48mc_fclk, 2457 .parent = &init_60m_fclk,
2295 .recalc = &followparent_recalc, 2458 .recalc = &followparent_recalc,
2296}; 2459};
2297 2460
2298static struct clk usb_otg_ick = { 2461static struct clk usb_host_hs_hsic60m_p2_clk = {
2299 .name = "usb_otg_ick", 2462 .name = "usb_host_hs_hsic60m_p2_clk",
2300 .ops = &clkops_omap2_dflt, 2463 .ops = &clkops_omap2_dflt,
2301 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, 2464 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2302 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2465 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2303 .clkdm_name = "l3_init_clkdm", 2466 .clkdm_name = "l3_init_clkdm",
2304 .parent = &l3_div_ck, 2467 .parent = &init_60m_fclk,
2305 .recalc = &followparent_recalc, 2468 .recalc = &followparent_recalc,
2306}; 2469};
2307 2470
2308static struct clk usb_tll_ick = { 2471static const struct clksel utmi_p1_gfclk_sel[] = {
2309 .name = "usb_tll_ick", 2472 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2473 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2474 { .parent = NULL },
2475};
2476
2477static struct clk utmi_p1_gfclk = {
2478 .name = "utmi_p1_gfclk",
2479 .parent = &init_60m_fclk,
2480 .clksel = utmi_p1_gfclk_sel,
2481 .init = &omap2_init_clksel_parent,
2482 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2483 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2484 .ops = &clkops_null,
2485 .recalc = &omap2_clksel_recalc,
2486};
2487
2488static struct clk usb_host_hs_utmi_p1_clk = {
2489 .name = "usb_host_hs_utmi_p1_clk",
2310 .ops = &clkops_omap2_dflt, 2490 .ops = &clkops_omap2_dflt,
2311 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, 2491 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2312 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2492 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2313 .clkdm_name = "l3_init_clkdm", 2493 .clkdm_name = "l3_init_clkdm",
2314 .parent = &l4_div_ck, 2494 .parent = &utmi_p1_gfclk,
2315 .recalc = &followparent_recalc, 2495 .recalc = &followparent_recalc,
2316}; 2496};
2317 2497
2318static struct clk usbphyocp2scp_ick = { 2498static const struct clksel utmi_p2_gfclk_sel[] = {
2319 .name = "usbphyocp2scp_ick", 2499 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2500 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2501 { .parent = NULL },
2502};
2503
2504static struct clk utmi_p2_gfclk = {
2505 .name = "utmi_p2_gfclk",
2506 .parent = &init_60m_fclk,
2507 .clksel = utmi_p2_gfclk_sel,
2508 .init = &omap2_init_clksel_parent,
2509 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2510 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2511 .ops = &clkops_null,
2512 .recalc = &omap2_clksel_recalc,
2513};
2514
2515static struct clk usb_host_hs_utmi_p2_clk = {
2516 .name = "usb_host_hs_utmi_p2_clk",
2320 .ops = &clkops_omap2_dflt, 2517 .ops = &clkops_omap2_dflt,
2321 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, 2518 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2322 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2519 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2323 .clkdm_name = "l3_init_clkdm", 2520 .clkdm_name = "l3_init_clkdm",
2324 .parent = &l4_div_ck, 2521 .parent = &utmi_p2_gfclk,
2325 .recalc = &followparent_recalc, 2522 .recalc = &followparent_recalc,
2326}; 2523};
2327 2524
2328static struct clk usim_fck = { 2525static struct clk usb_host_hs_hsic480m_p1_clk = {
2329 .name = "usim_fck", 2526 .name = "usb_host_hs_hsic480m_p1_clk",
2330 .ops = &clkops_omap2_dflt, 2527 .ops = &clkops_omap2_dflt,
2331 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2528 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2332 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2529 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2333 .clkdm_name = "l4_wkup_clkdm", 2530 .clkdm_name = "l3_init_clkdm",
2334 .parent = &sys_32k_ck, 2531 .parent = &dpll_usb_m2_ck,
2335 .recalc = &followparent_recalc, 2532 .recalc = &followparent_recalc,
2336}; 2533};
2337 2534
2338static struct clk wdt2_fck = { 2535static struct clk usb_host_hs_hsic480m_p2_clk = {
2339 .name = "wdt2_fck", 2536 .name = "usb_host_hs_hsic480m_p2_clk",
2340 .ops = &clkops_omap2_dflt, 2537 .ops = &clkops_omap2_dflt,
2341 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, 2538 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2342 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2539 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2343 .clkdm_name = "l4_wkup_clkdm", 2540 .clkdm_name = "l3_init_clkdm",
2344 .parent = &sys_32k_ck, 2541 .parent = &dpll_usb_m2_ck,
2345 .recalc = &followparent_recalc, 2542 .recalc = &followparent_recalc,
2346}; 2543};
2347 2544
2348static struct clk wdt3_fck = { 2545static struct clk usb_host_hs_func48mclk = {
2349 .name = "wdt3_fck", 2546 .name = "usb_host_hs_func48mclk",
2350 .ops = &clkops_omap2_dflt, 2547 .ops = &clkops_omap2_dflt,
2351 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, 2548 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2549 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2550 .clkdm_name = "l3_init_clkdm",
2551 .parent = &func_48mc_fclk,
2552 .recalc = &followparent_recalc,
2553};
2554
2555static struct clk usb_host_hs_fck = {
2556 .name = "usb_host_hs_fck",
2557 .ops = &clkops_omap2_dflt,
2558 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2352 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2559 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2353 .clkdm_name = "abe_clkdm", 2560 .clkdm_name = "l3_init_clkdm",
2354 .parent = &sys_32k_ck, 2561 .parent = &init_60m_fclk,
2355 .recalc = &followparent_recalc, 2562 .recalc = &followparent_recalc,
2356}; 2563};
2357 2564
2358/* Remaining optional clocks */
2359static const struct clksel otg_60m_gfclk_sel[] = { 2565static const struct clksel otg_60m_gfclk_sel[] = {
2360 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, 2566 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2361 { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, 2567 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2362 { .parent = NULL }, 2568 { .parent = NULL },
2363}; 2569};
2364 2570
2365static struct clk otg_60m_gfclk_ck = { 2571static struct clk otg_60m_gfclk = {
2366 .name = "otg_60m_gfclk_ck", 2572 .name = "otg_60m_gfclk",
2367 .parent = &utmi_phy_clkout_ck, 2573 .parent = &utmi_phy_clkout_ck,
2368 .clksel = otg_60m_gfclk_sel, 2574 .clksel = otg_60m_gfclk_sel,
2369 .init = &omap2_init_clksel_parent, 2575 .init = &omap2_init_clksel_parent,
@@ -2373,38 +2579,74 @@ static struct clk otg_60m_gfclk_ck = {
2373 .recalc = &omap2_clksel_recalc, 2579 .recalc = &omap2_clksel_recalc,
2374}; 2580};
2375 2581
2376static const struct clksel stm_clk_div_div[] = { 2582static struct clk usb_otg_hs_xclk = {
2377 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, 2583 .name = "usb_otg_hs_xclk",
2378 { .parent = NULL }, 2584 .ops = &clkops_omap2_dflt,
2585 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2586 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2587 .clkdm_name = "l3_init_clkdm",
2588 .parent = &otg_60m_gfclk,
2589 .recalc = &followparent_recalc,
2379}; 2590};
2380 2591
2381static struct clk stm_clk_div_ck = { 2592static struct clk usb_otg_hs_ick = {
2382 .name = "stm_clk_div_ck", 2593 .name = "usb_otg_hs_ick",
2383 .parent = &pmd_stm_clock_mux_ck, 2594 .ops = &clkops_omap2_dflt,
2384 .clksel = stm_clk_div_div, 2595 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2385 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, 2596 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2386 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, 2597 .clkdm_name = "l3_init_clkdm",
2387 .ops = &clkops_null, 2598 .parent = &l3_div_ck,
2388 .recalc = &omap2_clksel_recalc, 2599 .recalc = &followparent_recalc,
2389 .round_rate = &omap2_clksel_round_rate,
2390 .set_rate = &omap2_clksel_set_rate,
2391}; 2600};
2392 2601
2393static const struct clksel trace_clk_div_div[] = { 2602static struct clk usb_phy_cm_clk32k = {
2394 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, 2603 .name = "usb_phy_cm_clk32k",
2395 { .parent = NULL }, 2604 .ops = &clkops_omap2_dflt,
2605 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2606 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2607 .clkdm_name = "l4_ao_clkdm",
2608 .parent = &sys_32k_ck,
2609 .recalc = &followparent_recalc,
2396}; 2610};
2397 2611
2398static struct clk trace_clk_div_ck = { 2612static struct clk usb_tll_hs_usb_ch2_clk = {
2399 .name = "trace_clk_div_ck", 2613 .name = "usb_tll_hs_usb_ch2_clk",
2400 .parent = &pmd_trace_clk_mux_ck, 2614 .ops = &clkops_omap2_dflt,
2401 .clksel = trace_clk_div_div, 2615 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2402 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, 2616 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2403 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, 2617 .clkdm_name = "l3_init_clkdm",
2404 .ops = &clkops_null, 2618 .parent = &init_60m_fclk,
2405 .recalc = &omap2_clksel_recalc, 2619 .recalc = &followparent_recalc,
2406 .round_rate = &omap2_clksel_round_rate, 2620};
2407 .set_rate = &omap2_clksel_set_rate, 2621
2622static struct clk usb_tll_hs_usb_ch0_clk = {
2623 .name = "usb_tll_hs_usb_ch0_clk",
2624 .ops = &clkops_omap2_dflt,
2625 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2626 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2627 .clkdm_name = "l3_init_clkdm",
2628 .parent = &init_60m_fclk,
2629 .recalc = &followparent_recalc,
2630};
2631
2632static struct clk usb_tll_hs_usb_ch1_clk = {
2633 .name = "usb_tll_hs_usb_ch1_clk",
2634 .ops = &clkops_omap2_dflt,
2635 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2636 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2637 .clkdm_name = "l3_init_clkdm",
2638 .parent = &init_60m_fclk,
2639 .recalc = &followparent_recalc,
2640};
2641
2642static struct clk usb_tll_hs_ick = {
2643 .name = "usb_tll_hs_ick",
2644 .ops = &clkops_omap2_dflt,
2645 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2646 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2647 .clkdm_name = "l3_init_clkdm",
2648 .parent = &l4_div_ck,
2649 .recalc = &followparent_recalc,
2408}; 2650};
2409 2651
2410static const struct clksel_rate div2_14to18_rates[] = { 2652static const struct clksel_rate div2_14to18_rates[] = {
@@ -2418,8 +2660,8 @@ static const struct clksel usim_fclk_div[] = {
2418 { .parent = NULL }, 2660 { .parent = NULL },
2419}; 2661};
2420 2662
2421static struct clk usim_fclk = { 2663static struct clk usim_ck = {
2422 .name = "usim_fclk", 2664 .name = "usim_ck",
2423 .parent = &dpll_per_m4_ck, 2665 .parent = &dpll_per_m4_ck,
2424 .clksel = usim_fclk_div, 2666 .clksel = usim_fclk_div,
2425 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2667 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
@@ -2430,38 +2672,79 @@ static struct clk usim_fclk = {
2430 .set_rate = &omap2_clksel_set_rate, 2672 .set_rate = &omap2_clksel_set_rate,
2431}; 2673};
2432 2674
2433static const struct clksel utmi_p1_gfclk_sel[] = { 2675static struct clk usim_fclk = {
2434 { .parent = &init_60m_fclk, .rates = div_1_0_rates }, 2676 .name = "usim_fclk",
2435 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, 2677 .ops = &clkops_omap2_dflt,
2678 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2679 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2680 .clkdm_name = "l4_wkup_clkdm",
2681 .parent = &usim_ck,
2682 .recalc = &followparent_recalc,
2683};
2684
2685static struct clk usim_fck = {
2686 .name = "usim_fck",
2687 .ops = &clkops_omap2_dflt,
2688 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2689 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2690 .clkdm_name = "l4_wkup_clkdm",
2691 .parent = &sys_32k_ck,
2692 .recalc = &followparent_recalc,
2693};
2694
2695static struct clk wd_timer2_fck = {
2696 .name = "wd_timer2_fck",
2697 .ops = &clkops_omap2_dflt,
2698 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2699 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2700 .clkdm_name = "l4_wkup_clkdm",
2701 .parent = &sys_32k_ck,
2702 .recalc = &followparent_recalc,
2703};
2704
2705static struct clk wd_timer3_fck = {
2706 .name = "wd_timer3_fck",
2707 .ops = &clkops_omap2_dflt,
2708 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2709 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2710 .clkdm_name = "abe_clkdm",
2711 .parent = &sys_32k_ck,
2712 .recalc = &followparent_recalc,
2713};
2714
2715/* Remaining optional clocks */
2716static const struct clksel stm_clk_div_div[] = {
2717 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2436 { .parent = NULL }, 2718 { .parent = NULL },
2437}; 2719};
2438 2720
2439static struct clk utmi_p1_gfclk_ck = { 2721static struct clk stm_clk_div_ck = {
2440 .name = "utmi_p1_gfclk_ck", 2722 .name = "stm_clk_div_ck",
2441 .parent = &init_60m_fclk, 2723 .parent = &pmd_stm_clock_mux_ck,
2442 .clksel = utmi_p1_gfclk_sel, 2724 .clksel = stm_clk_div_div,
2443 .init = &omap2_init_clksel_parent, 2725 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2444 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2726 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2445 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2446 .ops = &clkops_null, 2727 .ops = &clkops_null,
2447 .recalc = &omap2_clksel_recalc, 2728 .recalc = &omap2_clksel_recalc,
2729 .round_rate = &omap2_clksel_round_rate,
2730 .set_rate = &omap2_clksel_set_rate,
2448}; 2731};
2449 2732
2450static const struct clksel utmi_p2_gfclk_sel[] = { 2733static const struct clksel trace_clk_div_div[] = {
2451 { .parent = &init_60m_fclk, .rates = div_1_0_rates }, 2734 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2452 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2453 { .parent = NULL }, 2735 { .parent = NULL },
2454}; 2736};
2455 2737
2456static struct clk utmi_p2_gfclk_ck = { 2738static struct clk trace_clk_div_ck = {
2457 .name = "utmi_p2_gfclk_ck", 2739 .name = "trace_clk_div_ck",
2458 .parent = &init_60m_fclk, 2740 .parent = &pmd_trace_clk_mux_ck,
2459 .clksel = utmi_p2_gfclk_sel, 2741 .clksel = trace_clk_div_div,
2460 .init = &omap2_init_clksel_parent, 2742 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2461 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2743 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2462 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2463 .ops = &clkops_null, 2744 .ops = &clkops_null,
2464 .recalc = &omap2_clksel_recalc, 2745 .recalc = &omap2_clksel_recalc,
2746 .round_rate = &omap2_clksel_round_rate,
2747 .set_rate = &omap2_clksel_set_rate,
2465}; 2748};
2466 2749
2467/* 2750/*
@@ -2483,11 +2766,12 @@ static struct omap_clk omap44xx_clks[] = {
2483 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), 2766 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
2484 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), 2767 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
2485 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), 2768 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
2769 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
2486 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), 2770 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
2487 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), 2771 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
2488 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), 2772 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
2489 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), 2773 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
2490 CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X), 2774 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
2491 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), 2775 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
2492 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), 2776 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
2493 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), 2777 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
@@ -2557,46 +2841,48 @@ static struct omap_clk omap44xx_clks[] = {
2557 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 2841 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
2558 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 2842 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
2559 CLK(NULL, "aess_fck", &aess_fck, CK_443X), 2843 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
2560 CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X), 2844 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
2561 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), 2845 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
2562 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 2846 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2563 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 2847 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
2848 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
2849 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
2850 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
2851 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
2852 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
2564 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 2853 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
2565 CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), 2854 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
2566 CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), 2855 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
2567 CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), 2856 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
2568 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 2857 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
2569 CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), 2858 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
2570 CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), 2859 CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X),
2571 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), 2860 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
2861 CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X),
2572 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), 2862 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
2863 CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X),
2573 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), 2864 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
2865 CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X),
2574 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), 2866 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
2867 CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X),
2575 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), 2868 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
2869 CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X),
2576 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 2870 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2577 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), 2871 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
2578 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), 2872 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
2579 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X),
2580 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X),
2581 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X),
2582 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X),
2583 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X),
2584 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X),
2585 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X),
2586 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X),
2587 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X),
2588 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X),
2589 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), 2873 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
2590 CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), 2874 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
2591 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), 2875 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
2592 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), 2876 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
2593 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), 2877 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
2594 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), 2878 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
2879 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
2880 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
2595 CLK(NULL, "iss_fck", &iss_fck, CK_443X), 2881 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
2596 CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), 2882 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
2597 CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), 2883 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
2598 CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), 2884 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
2599 CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), 2885 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
2600 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 2886 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
2601 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 2887 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
2602 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 2888 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
@@ -2607,6 +2893,7 @@ static struct omap_clk omap44xx_clks[] = {
2607 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), 2893 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
2608 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 2894 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
2609 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), 2895 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
2896 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
2610 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), 2897 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
2611 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), 2898 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
2612 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), 2899 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
@@ -2616,43 +2903,66 @@ static struct omap_clk omap44xx_clks[] = {
2616 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), 2903 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
2617 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), 2904 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
2618 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), 2905 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
2619 CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), 2906 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
2620 CLK(NULL, "pdm_fck", &pdm_fck, CK_443X), 2907 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
2621 CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X), 2908 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
2622 CLK("omap_rng", "ick", &rng_ick, CK_443X), 2909 CLK("omap_rng", "ick", &rng_ick, CK_443X),
2623 CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), 2910 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
2624 CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), 2911 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
2912 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
2913 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
2914 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
2915 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
2625 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), 2916 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
2917 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
2918 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
2919 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
2626 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), 2920 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
2627 CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), 2921 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
2628 CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), 2922 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
2629 CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), 2923 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
2630 CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), 2924 CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
2925 CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
2926 CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
2927 CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
2928 CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
2929 CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
2930 CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
2931 CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
2932 CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
2933 CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
2934 CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
2631 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), 2935 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
2632 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), 2936 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
2633 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 2937 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2634 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 2938 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
2635 CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X),
2636 CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X),
2637 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 2939 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
2638 CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), 2940 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
2639 CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), 2941 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
2640 CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X), 2942 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
2943 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
2944 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
2945 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
2946 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
2947 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
2948 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
2949 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
2950 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
2951 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
2952 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
2953 CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X),
2954 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
2955 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
2956 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
2957 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
2958 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
2959 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
2960 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2641 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 2961 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2642 CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), 2962 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
2643 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), 2963 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
2644 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
2645 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 2964 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2646 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 2965 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
2647 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2648 CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
2649 CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
2650 CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X),
2651 CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X),
2652 CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X),
2653 CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X),
2654 CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X),
2655 CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X),
2656 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 2966 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
2657 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), 2967 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
2658 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), 2968 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
@@ -2669,19 +2979,19 @@ static struct omap_clk omap44xx_clks[] = {
2669 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), 2979 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
2670 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), 2980 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
2671 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), 2981 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
2982 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2983 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2984 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2985 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2986 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
2672 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), 2987 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
2673 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 2988 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
2674 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 2989 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
2675 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), 2990 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
2676 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), 2991 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
2677 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), 2992 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
2678 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), 2993 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
2679 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), 2994 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
2680 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2681 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2682 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2683 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2684 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
2685 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), 2995 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
2686 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 2996 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
2687 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 2997 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 08:34:14 -0400